silireg.h revision 1.16
1/* $OpenBSD: silireg.h,v 1.16 2007/04/05 09:57:50 dlg Exp $ */ 2 3/* 4 * Copyright (c) 2007 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19/* PCI Registers */ 20#define SILI_PCI_BAR_GLOBAL 0x10 /* Global Registers address */ 21#define SILI_PCI_BAR_PORT 0x18 /* Port Registers address */ 22#define SILI_PCI_BAR_INDIRECT 0x20 /* Indirect IO Registers address */ 23 24/* Global Registers */ 25#define SILI_REG_PORT0_STATUS 0x00 /* Port 0 Slot Status */ 26#define SILI_REG_PORT1_STATUS 0x04 /* Port 1 Slot Status */ 27#define SILI_REG_PORT2_STATUS 0x08 /* Port 2 Slot Status */ 28#define SILI_REG_PORT3_STATUS 0x0c /* Port 3 Slot Status */ 29#define SILI_REG_GC 0x40 /* Global Control */ 30#define SILI_REG_GC_GR (1<<31) /* Global Reset */ 31#define SILI_REG_GC_MSIACK (1<<30) /* MSI Acknowledge */ 32#define SILI_REG_GC_I2CINT (1<<29) /* I2C Interrupt Enable */ 33#define SILI_REG_GC_PERRDIS (1<<28) /* PCI Error Report Disable */ 34#define SILI_REG_GC_REQ64 (1<<20) /* latched PCI REQ64 */ 35#define SILI_REG_GC_DEVSEL (1<<19) /* latched PCI DEVSEL */ 36#define SILI_REG_GC_STOP (1<<18) /* latched PCI STOP */ 37#define SILI_REG_GC_TRDY (1<<17) /* latched PCI TRDY */ 38#define SILI_REG_GC_M66EN (1<<16) /* M66EN PCI bus signal */ 39#define SILI_REG_GC_PIE_MASK 0x0f 40#define SILI_FMT_GC "\020" "\040GR" "\037MSIACK" "\036I2CINT" \ 41 "\035PERRDIS" "\025REQ64" "\024DEVSEL" \ 42 "\023STOP" "\022TRDY" "\021M66EN" \ 43 "\004P3IE" "\003P2IE" "\002P1IE" "\001P0IE" 44#define SILI_REG_GIS 0x40 /* Global Interrupt Status */ 45#define SILI_REG_PHYCONF 0x48 /* PHY Configuration */ 46#define SILI_REG_BISTCTL 0x50 /* BIST Control */ 47#define SILI_REG_BISTPATTERN 0x54 /* BIST Pattern */ 48#define SILI_REG_BISTSTAT 0x58 /* BIST Status */ 49#define SILI_REG_FLASHADDR 0x70 /* Flash Address */ 50#define SILI_REG_FLASHDATA 0x74 /* Flash Memory Data / GPIO Control */ 51#define SILI_REG_GPIOCTL SILI_REG_FLASHDATA 52#define SILI_REG_IICADDR 0x78 /* I2C Address */ 53#define SILI_REG_IIC 0x7c /* I2C Data / Control */ 54 55#define SILI_PORT_SIZE 0x2000 56#define SILI_PORT_OFFSET(_p) ((_p) * SILI_PORT_SIZE) 57 58/* Port Registers */ 59#define SILI_PREG_LRAM 0x0000 /* Port LRAM */ 60#define SILI_PREG_SLOT_WIDTH 0x80 61#define SILI_PREG_SLOT(_s) (SILI_PREG_LRAM + (_s) * SILI_PREG_SLOT_WIDTH) 62/* XXX PMP Bits */ 63#define SILI_PREG_PCS 0x1000 /* Port Control Set / Status */ 64#define SILI_PREG_PCS_OOBB (1<<25) /* OOB Bypass */ 65#define SILI_PREG_PCS_ACTIVE(_x) (((_x)>>16) & 0xf) /* Active Slot */ 66#define SILI_PREG_PCS_LED_ON (1<<15) /* LED On */ 67#define SILI_PREG_PCS_AIA (1<<14) /* Auto Interlock Accept */ 68#define SILI_PREG_PCS_PMEN (1<<13) /* Port Mult Enable */ 69#define SILI_PREG_PCS_IA (1<<12) /* Interlock Accept */ 70#define SILI_PREG_PCS_IR (1<<11) /* Interlock Reject */ 71#define SILI_PREG_PCS_A32B (1<<10) /* 32-bit Activation */ 72#define SILI_PREG_PCS_SD (1<<9) /* Scrambler Disable */ 73#define SILI_PREG_PCS_CD (1<<8) /* CONT Disable */ 74#define SILI_PREG_PCS_TB (1<<7) /* Transmit BIST */ 75#define SILI_PREG_PCS_RESUME (1<<6) /* Resume */ 76#define SILI_PREG_PCS_PLEN (1<<5) /* Packet Length */ 77#define SILI_PREG_PCS_LEDDISABLE (1<<4) /* LED Disable */ 78#define SILI_PREG_PCS_NOINTCLR (1<<3) /* No Intr Clear on Read */ 79#define SILI_PREG_PCS_PORTINIT (1<<2) /* Port Initialize */ 80#define SILI_PREG_PCS_DEVRESET (1<<1) /* Device Reset */ 81#define SILI_PREG_PCS_PORTRESET (1<<0) /* Port Reset */ 82#define SILI_PFMT_PCS "\020" "\032OOBB" "\020LED_ON" "\017AIA" \ 83 "\016PMEN" "\015IA" "\014IR" "\013A32B" \ 84 "\012SD" "\011CD" "\010TB" "\007RESUME" \ 85 "\006PLEN" "\005LEDDISABLE" \ 86 "\004NOINTCLR" "\003PORTINIT" \ 87 "\002PORTINIT" "\001PORTRESET" 88#define SILI_PREG_PCC 0x1004 /* Port Control Clear */ 89#define SILI_PREG_PCC_OOBB (1<<25) /* OOB Bypass */ 90#define SILI_PREG_PCC_LED_ON (1<<15) /* LED On */ 91#define SILI_PREG_PCC_AIA (1<<14) /* Auto Interlock Accept */ 92#define SILI_PREG_PCC_PMEN (1<<13) /* Port Mult Enable */ 93#define SILI_PREG_PCC_IA (1<<12) /* Interlock Accept */ 94#define SILI_PREG_PCC_IR (1<<11) /* Interlock Reject */ 95#define SILI_PREG_PCC_A32B (1<<10) /* 32-bit Activation */ 96#define SILI_PREG_PCC_SD (1<<9) /* Scrambler Disable */ 97#define SILI_PREG_PCC_CD (1<<8) /* CONT Disable */ 98#define SILI_PREG_PCC_TB (1<<7) /* Transmit BIST */ 99#define SILI_PREG_PCC_RESUME (1<<6) /* Resume */ 100#define SILI_PREG_PCC_PLEN (1<<5) /* Packet Length */ 101#define SILI_PREG_PCC_LEDDISABLE (1<<4) /* LED Disable */ 102#define SILI_PREG_PCC_NOINTCLR (1<<3) /* No Intr Clear on Read */ 103#define SILI_PREG_PCC_PORTINIT (1<<2) /* Port Initialize */ 104#define SILI_PREG_PCC_DEVRESET (1<<1) /* Device Reset */ 105#define SILI_PREG_PCC_PORTRESET (1<<0) /* Port Reset */ 106#define SILI_PREG_IS 0x1008 /* Interrupt Status */ 107#define SILI_PREG_IES 0x1010 /* Interrupt Enable Set */ 108#define SILI_PREG_IEC 0x1014 /* Interrupt Enable Clear */ 109#define SILI_PREG_IE_SDB (1<<11) /* SDB Notify */ 110#define SILI_PREG_IE_DEVXCHG (1<<7) /* Device Exchange */ 111#define SILI_PREG_IE_UNRECFIS (1<<6) /* Unrecognized FIS Type */ 112#define SILI_PREG_IE_COMWAKE (1<<5) /* ComWake */ 113#define SILI_PREG_IE_PHYRDYCHG (1<<4) /* Phy Ready Change */ 114#define SILI_PREG_IE_PMCHG (1<<3) /* Power Mmgt Change */ 115#define SILI_PREG_IE_PORTRDY (1<<2) /* Port Ready */ 116#define SILI_PREG_IE_CMDERR (1<<1) /* Command Error */ 117#define SILI_PREG_IE_CMDCOMP (1<<0) /* Command Completion */ 118#define SILI_PREG_AUA 0x101c /* Activation Upper Address */ 119#define SILI_PREG_FIFO 0x1020 /* Command Execution FIFO */ 120#define SILI_PREG_CE 0x1024 /* Command Error */ 121#define SILI_PREG_FC 0x1028 /* FIS Configuration */ 122#define SILI_PREG_RFT 0x102c /* Request FIFO Threshold */ 123#define SILI_PREG_DEC 0x1040 /* 8b/10b Decode Error Counter */ 124#define SILI_PREG_CEC 0x1044 /* CRC Error Counter */ 125#define SILI_PREG_HEC 0x1048 /* Handshake Error Counter */ 126#define SILI_PREG_PHYCONF 0x1050 /* Port PHY Configuration */ 127#define SILI_PREG_PSS 0x1800 /* Port Slot Status */ 128#define SILI_PREG_CAR 0x1c00 /* Command Activation Registers */ 129 /* XXX up to 0x1cf7 is more of these */ 130#define SILI_PREG_CONTEXT 0x1e0f /* Port Context Register */ 131#define SILI_PREG_SCTL 0x1f00 /* SControl */ 132#define SILI_PREG_SSTS 0x1f04 /* SStatus */ 133#define SILI_PREG_SERR 0x1f08 /* SError */ 134#define SILI_PREG_SACT 0x1f0c /* SActive */ 135 136 137struct sili_sge { 138 u_int32_t addr_lo; 139 u_int32_t addr_hi; 140 u_int32_t data_count; 141 u_int32_t flags; 142#define SILI_SGE_TRM (1<<31) 143#define SILI_SGE_LNK (1<<30) 144#define SILI_SGE_DRD (1<<29) 145#define SILI_SGE_XCF (1<<28) 146} __packed; 147 148struct sili_sgt { 149 struct sili_sge sgl[4]; 150} __packed; 151 152#define SILI_PRB_PROTOCOL_OVERRIDE (1<<0) 153#define SILI_PRB_RETRANSMIT (1<<1) 154#define SILI_PRB_EXTERNAL_COMMAND (1<<2) 155#define SILI_PRB_RECEIVE (1<<3) 156#define SILI_PRB_PACKET_READ (1<<4) 157#define SILI_PRB_PACKET_WRITE (1<<5) 158#define SILI_PRB_INTERRUPT_MASK (1<<6) 159#define SILI_PRB_SOFT_RESET (1<<7) 160 161struct sili_prb_ata { 162 u_int16_t control; 163 u_int16_t protocol_override; 164 u_int32_t rx_count; 165 166 u_int8_t fis[ATA_FIS_LENGTH]; 167 168 u_int32_t reserved; 169 170 struct sili_sge sgl[2]; 171} __packed; 172 173struct sili_prb_packet { 174 u_int16_t control; 175 u_int16_t protocol_override; 176 u_int32_t rx_count; 177 178 u_int8_t fis[ATA_FIS_LENGTH]; 179 180 u_int32_t reserved; 181 182 u_int8_t cdb[16]; 183 184 struct sili_sge sgl[1]; 185} __packed; 186 187struct sili_prb_softreset { 188 u_int16_t control; 189 u_int16_t reserved1; 190 u_int32_t reserved2; 191 192 u_int8_t fis[ATA_FIS_LENGTH]; 193 194 u_int32_t reserved3[9]; 195} __packed; 196 197#define SILI_MAX_CMDS 31 198#define SILI_PRB_LENGTH 64 199#define SILI_SGT_LENGTH 64 200