silireg.h revision 1.10
1/* $OpenBSD: silireg.h,v 1.10 2007/03/31 08:08:15 dlg Exp $ */ 2 3/* 4 * Copyright (c) 2007 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19/* PCI Registers */ 20#define SILI_PCI_BAR_GLOBAL 0x10 /* Global Registers address */ 21#define SILI_PCI_BAR_PORT 0x18 /* Port Registers address */ 22#define SILI_PCI_BAR_INDIRECT 0x20 /* Indirect IO Registers address */ 23 24/* Global Registers */ 25#define SILI_REG_PORT0_STATUS 0x00 /* Port 0 Slot Status */ 26#define SILI_REG_PORT1_STATUS 0x04 /* Port 1 Slot Status */ 27#define SILI_REG_PORT2_STATUS 0x08 /* Port 2 Slot Status */ 28#define SILI_REG_PORT3_STATUS 0x0c /* Port 3 Slot Status */ 29#define SILI_REG_GC 0x40 /* Global Control */ 30#define SILI_REG_GC_GR (1<<31) /* Global Reset */ 31#define SILI_REG_GC_MSIACK (1<<30) /* MSI Acknowledge */ 32#define SILI_REG_GC_I2CINT (1<<29) /* I2C Interrupt Enable */ 33#define SILI_REG_GC_PERRDIS (1<<28) /* PCI Error Report Disable */ 34#define SILI_REG_GC_REQ64 (1<<20) /* latched PCI REQ64 */ 35#define SILI_REG_GC_DEVSEL (1<<19) /* latched PCI DEVSEL */ 36#define SILI_REG_GC_STOP (1<<18) /* latched PCI STOP */ 37#define SILI_REG_GC_TRDY (1<<17) /* latched PCI TRDY */ 38#define SILI_REG_GC_M66EN (1<<16) /* M66EN PCI bus signal */ 39#define SILI_REG_GC_PIE_MASK 0x0f 40#define SILI_FMT_GC "\020" "\040GR" "\037MSIACK" "\036I2CINT" \ 41 "\035PERRDIS" "\025REQ64" "\024DEVSEL" \ 42 "\023STOP" "\022TRDY" "\021M66EN" \ 43 "\004P3IE" "\003P2IE" "\002P1IE" "\001P0IE" 44#define SILI_REG_GIS 0x40 /* Global Interrupt Status */ 45#define SILI_REG_PHYCONF 0x48 /* PHY Configuration */ 46#define SILI_REG_BISTCTL 0x50 /* BIST Control */ 47#define SILI_REG_BISTPATTERN 0x54 /* BIST Pattern */ 48#define SILI_REG_BISTSTAT 0x58 /* BIST Status */ 49#define SILI_REG_FLASHADDR 0x70 /* Flash Address */ 50#define SILI_REG_FLASHDATA 0x74 /* Flash Memory Data / GPIO Control */ 51#define SILI_REG_GPIOCTL SILI_REG_FLASHDATA 52#define SILI_REG_IICADDR 0x78 /* I2C Address */ 53#define SILI_REG_IIC 0x7c /* I2C Data / Control */ 54 55#define SILI_PORT_SIZE 0x2000 56#define SILI_PORT_OFFSET(_p) ((_p) * SILI_PORT_SIZE) 57 58/* Port Registers */ 59#define SILI_PREG_LRAM 0x0000 /* Port LRAM */ 60 /* XXX 31 slots and port multiplier stuff sits in here */ 61#define SILI_PREG_PCS 0x1000 /* Port Control Set / Status */ 62#define SILI_PREG_PCS_OOBB (1<<25) /* OOB Bypass */ 63#define SILI_PREG_PCS_LED_ON (1<<15) /* LED On */ 64#define SILI_PREG_PCS_AIA (1<<14) /* Auto Interlock Accept */ 65#define SILI_PREG_PCS_PMEN (1<<13) /* Port Mult Enable */ 66#define SILI_PREG_PCS_IA (1<<12) /* Interlock Accept */ 67#define SILI_PREG_PCS_IR (1<<11) /* Interlock Reject */ 68#define SILI_PREG_PCS_A32B (1<<10) /* 32-bit Activation */ 69#define SILI_PREG_PCS_SD (1<<9) /* Scrambler Disable */ 70#define SILI_PREG_PCS_CD (1<<8) /* CONT Disable */ 71#define SILI_PREG_PCS_TB (1<<7) /* Transmit BIST */ 72#define SILI_PREG_PCS_RESUME (1<<6) /* Resume */ 73#define SILI_PREG_PCS_PLEN (1<<5) /* Packet Length */ 74#define SILI_PREG_PCS_PLEN_12 (0<<5) 75#define SILI_PREG_PCS_PLEN_16 (1<<5) 76#define SILI_PREG_PCS_LEDDISABLE (1<<4) /* LED Disable */ 77#define SILI_PREG_PCS_NOINTCLR (1<<3) /* No Intr Clear on Read */ 78#define SILI_PREG_PCS_PORTINIT (1<<2) /* Port Initialize */ 79#define SILI_PREG_PCS_DEVRESET (1<<1) /* Device Reset */ 80#define SILI_PREG_PCS_PORTRESET (1<<0) /* Port Reset */ 81#define SILI_PREG_PCC 0x1004 /* Port Control Clear */ 82#define SILI_PREG_IS 0x1008 /* Interrupt Status */ 83#define SILI_PREG_IES 0x1008 /* Interrupt Enable Set */ 84#define SILI_PREG_IEC 0x1008 /* Interrupt Enable Clear */ 85#define SILI_PREG_AUA 0x101c /* Activation Upper Address */ 86#define SILI_PREG_FIFO 0x1020 /* Command Execution FIFO */ 87#define SILI_PREG_CE 0x1024 /* Command Error */ 88#define SILI_PREG_FC 0x1028 /* FIS Configuration */ 89#define SILI_PREG_RFT 0x102c /* Request FIFO Threshold */ 90#define SILI_PREG_DEC 0x1040 /* 8b/10b Decode Error Counter */ 91#define SILI_PREG_CEC 0x1044 /* CRC Error Counter */ 92#define SILI_PREG_HEC 0x1048 /* Handshake Error Counter */ 93#define SILI_PREG_PHYCONF 0x1050 /* Port PHY Configuration */ 94#define SILI_PREG_PSS 0x1800 /* Port Slot Status */ 95#define SILI_PREG_CAR 0x1c00 /* Command Activation Registers */ 96 /* XXX up to 0x1cf7 is more of these */ 97#define SILI_PREG_CONTEXT 0x1e0f /* Port Context Register */ 98#define SILI_PREG_SCTL 0x1f00 /* SControl */ 99#define SILI_PREG_SSTS 0x1f04 /* SStatus */ 100#define SILI_PREG_SERR 0x1f08 /* SError */ 101#define SILI_PREG_SACT 0x1f0c /* SActive */ 102 103 104#define SILI_MAX_CMDS 31 105