1/* $OpenBSD: rtwreg.h,v 1.15 2022/01/09 05:42:42 jsg Exp $ */ 2/* $NetBSD: rtwreg.h,v 1.12 2005/01/16 11:50:43 dyoung Exp $ */ 3/*- 4 * Copyright (c) 2004, 2005 David Young. All rights reserved. 5 * 6 * Programmed for NetBSD by David Young. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of David Young may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 24 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 26 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33/* Macros for bit twiddling. */ 34/* TBD factor w/ dev/ic/atwreg.h. */ 35 36#ifndef _BIT_TWIDDLE 37#define _BIT_TWIDDLE 38 39/* find least significant bit that is set */ 40#define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x)) 41 42/* for x a power of two and p a non-negative integer, is x a greater 43 * power than 2**p? 44 */ 45#define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0) 46 47#define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0) 48 49#define MASK_TO_SHIFT4(m) \ 50 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \ 51 ? 2 + MASK_TO_SHIFT2((m) >> 2) \ 52 : MASK_TO_SHIFT2((m))) 53 54#define MASK_TO_SHIFT8(m) \ 55 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \ 56 ? 4 + MASK_TO_SHIFT4((m) >> 4) \ 57 : MASK_TO_SHIFT4((m))) 58 59#define MASK_TO_SHIFT16(m) \ 60 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \ 61 ? 8 + MASK_TO_SHIFT8((m) >> 8) \ 62 : MASK_TO_SHIFT8((m))) 63 64#define MASK_TO_SHIFT(m) \ 65 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \ 66 ? 16 + MASK_TO_SHIFT16((m) >> 16) \ 67 : MASK_TO_SHIFT16((m))) 68 69#define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask)) 70#define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask)) 71#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask)) 72#define PRESHIFT(m) MASK_AND_RSHIFT((m), (m)) 73 74#endif /* _BIT_TWIDDLE */ 75 76/* RTL8180/RTL8185 Host Control and Status Registers */ 77 78#define RTW_IDR0 0x00 /* ID Register: MAC addr, 6 bytes. 79 * Auto-loaded from EEPROM. Read by byte, 80 * by word, or by double word, but write 81 * only by double word. 82 */ 83#define RTW_IDR1 0x04 84 85#define RTW_MAR0 0x08 /* Multicast filter, 64b. */ 86#define RTW_MAR1 0x0c 87 88#define RTW_TSFTRL 0x18 /* Timing Synchronization Function Timer 89 * Register, low word, 32b, read-only. 90 */ 91#define RTW_TSFTRH 0x1c /* High word, 32b, read-only. */ 92#define RTW_TLPDA 0x20 /* Transmit Low Priority Descriptors Start 93 * Address, 32b, 256-byte alignment. 94 */ 95#define RTW_TNPDA 0x24 /* Transmit Normal Priority Descriptors Start 96 * Address, 32b, 256-byte alignment. 97 */ 98#define RTW_THPDA 0x28 /* Transmit High Priority Descriptors Start 99 * Address, 32b, 256-byte alignment. 100 */ 101 102#define RTW_BRSR 0x2c /* Basic Rate Set Register, 16b */ 103#define RTW8180_BRSR_BPLCP (1<<8) /* 1: Short PLCP CTS/ACK header */ 104#define RTW8180_BRSR_MBR_MASK 0x3 /* Basic Service Rate */ 105#define RTW8180_BRSR_MBR_1MBPS LSHIFT(0, RTW8180_BRSR_MBR_MASK) 106#define RTW8180_BRSR_MBR_2MBPS LSHIFT(1, RTW8180_BRSR_MBR_MASK) 107#define RTW8180_BRSR_MBR_5MBPS LSHIFT(2, RTW8180_BRSR_MBR_MASK) 108#define RTW8180_BRSR_MBR_11MBPS LSHIFT(3, RTW8180_BRSR_MBR_MASK) 109#define RTW8185_BRSR_MBR_MASK 0xfff /* Basic Service Rate */ 110#define RTW8185_BRSR_MBR_1MBPS (1<<0) 111#define RTW8185_BRSR_MBR_2MBPS (1<<1) 112#define RTW8185_BRSR_MBR_5MBPS (1<<2) 113#define RTW8185_BRSR_MBR_11MBPS (1<<3) 114#define RTW8185_BRSR_MBR_6MBPS (1<<4) 115#define RTW8185_BRSR_MBR_9MBPS (1<<5) 116#define RTW8185_BRSR_MBR_12MBPS (1<<6) 117#define RTW8185_BRSR_MBR_18MBPS (1<<7) 118#define RTW8185_BRSR_MBR_24MBPS (1<<8) 119#define RTW8185_BRSR_MBR_36MBPS (1<<9) 120#define RTW8185_BRSR_MBR_48MBPS (1<<10) 121#define RTW8185_BRSR_MBR_54MBPS (1<<11) 122 123#define RTW_BSSID 0x2e 124/* BSSID, 6 bytes */ 125#define RTW_BSSID16 0x2e /* first two bytes */ 126#define RTW_BSSID32 (0x2e + 4) /* remaining four bytes */ 127#define RTW_BSSID0 RTW_BSSID16 /* BSSID[0], 8b */ 128#define RTW_BSSID1 (RTW_BSSID0 + 1) /* BSSID[1], 8b */ 129#define RTW_BSSID2 (RTW_BSSID1 + 1) /* BSSID[2], 8b */ 130#define RTW_BSSID3 (RTW_BSSID2 + 1) /* BSSID[3], 8b */ 131#define RTW_BSSID4 (RTW_BSSID3 + 1) /* BSSID[4], 8b */ 132#define RTW_BSSID5 (RTW_BSSID4 + 1) /* BSSID[5], 8b */ 133 134#define RTW8185_RR 0x34 /* Response Rate Register, 8b */ 135#define RTW8185_RR_MAX BIT(7, 4) 136#define RTW8185_RR_MAX_1MPBS LSHIFT(0, RTW8185_RR_MAX_MASK) 137#define RTW8185_RR_MAX_2MPBS LSHIFT(1, RTW8185_RR_MAX_MASK) 138#define RTW8185_RR_MAX_5MPBS LSHIFT(2, RTW8185_RR_MAX_MASK) 139#define RTW8185_RR_MAX_11MPBS LSHIFT(3, RTW8185_RR_MAX_MASK) 140#define RTW8185_RR_MAX_6MPBS LSHIFT(4, RTW8185_RR_MAX_MASK) 141#define RTW8185_RR_MAX_9MPBS LSHIFT(5, RTW8185_RR_MAX_MASK) 142#define RTW8185_RR_MAX_12MPBS LSHIFT(6, RTW8185_RR_MAX_MASK) 143#define RTW8185_RR_MAX_18MPBS LSHIFT(7, RTW8185_RR_MAX_MASK) 144#define RTW8185_RR_MAX_24MPBS LSHIFT(8, RTW8185_RR_MAX_MASK) 145#define RTW8185_RR_MAX_36MPBS LSHIFT(9, RTW8185_RR_MAX_MASK) 146#define RTW8185_RR_MAX_48MPBS LSHIFT(10, RTW8185_RR_MAX_MASK) 147#define RTW8185_RR_MAX_54MPBS LSHIFT(11, RTW8185_RR_MAX_MASK) 148#define RTW8185_RR_MIN_MASK BIT(3, 0) 149#define RTW8185_RR_MIN_1MPBS LSHIFT(0, RTW8185_RR_MIN_MASK) 150#define RTW8185_RR_MIN_2MPBS LSHIFT(1, RTW8185_RR_MIN_MASK) 151#define RTW8185_RR_MIN_5MPBS LSHIFT(2, RTW8185_RR_MIN_MASK) 152#define RTW8185_RR_MIN_11MPBS LSHIFT(3, RTW8185_RR_MIN_MASK) 153#define RTW8185_RR_MIN_6MPBS LSHIFT(4, RTW8185_RR_MIN_MASK) 154#define RTW8185_RR_MIN_9MPBS LSHIFT(5, RTW8185_RR_MIN_MASK) 155#define RTW8185_RR_MIN_12MPBS LSHIFT(6, RTW8185_RR_MIN_MASK) 156#define RTW8185_RR_MIN_18MPBS LSHIFT(7, RTW8185_RR_MIN_MASK) 157#define RTW8185_RR_MIN_24MPBS LSHIFT(8, RTW8185_RR_MIN_MASK) 158#define RTW8185_RR_MIN_36MPBS LSHIFT(9, RTW8185_RR_MIN_MASK) 159#define RTW8185_RR_MIN_48MPBS LSHIFT(10, RTW8185_RR_MIN_MASK) 160#define RTW8185_RR_MIN_54MPBS LSHIFT(11, RTW8185_RR_MIN_MASK) 161 162#define RTW8185_EIFS_TIMER 0x35 /* Extended IFS Register, 16b ??? */ 163 164#define RTW_CR 0x37 /* Command Register, 8b */ 165#define RTW_CR_RST (1<<4) /* Reset: host sets to 1 to disable 166 * transmitter & receiver, reinitialize FIFO. 167 * RTL8180L sets to 0 to signal completion. 168 */ 169#define RTW_CR_RE (1<<3) /* Receiver Enable: host enables receiver 170 * by writing 1. RTL8180L indicates receiver 171 * is active with 1. After power-up, host 172 * must wait for reset before writing. 173 */ 174#define RTW_CR_TE (1<<2) /* Transmitter Enable: host enables transmitter 175 * by writing 1. RTL8180L indicates transmitter 176 * is active with 1. After power-up, host 177 * must wait for reset before writing. 178 */ 179#define RTW_CR_MULRW (1<<0) /* PCI Multiple Read/Write enable: 1 enables, 180 * 0 disables. XXX RTL8180, only? 181 */ 182 183#define RTW_IMR 0x3c /* Interrupt Mask Register, 16b */ 184#define RTW_ISR 0x3e /* Interrupt Status Register, 16b */ 185 186#define RTW_INTR_TXFOVW (1<<15) /* Tx FIFO underflow */ 187#define RTW_INTR_TIMEOUT (1<<14) /* Time Out: 1 indicates 188 * RTW_TSFTR[0:31] = RTW_TINT 189 */ 190#define RTW_INTR_BCNINT (1<<13) /* Beacon Time Out: time for host to 191 * prepare beacon: 192 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 193 * (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV) 194 */ 195#define RTW_INTR_ATIMINT (1<<12) 196 /* ATIM Time Out: ATIM interval will pass, 197 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) = 198 * (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV) 199 */ 200#define RTW_INTR_TBDER (1<<11) /* Tx Beacon Descriptor Error: 201 * beacon transmission aborted because 202 * frame Rx'd 203 */ 204#define RTW_INTR_TBDOK (1<<10) /* Tx Beacon Descriptor OK */ 205#define RTW_INTR_THPDER (1<<9) /* Tx High Priority Descriptor Error: 206 * reached short/long retry limit 207 */ 208#define RTW_INTR_THPDOK (1<<8) /* Tx High Priority Descriptor OK */ 209#define RTW_INTR_TNPDER (1<<7) /* Tx Normal Priority Descriptor Error: 210 * reached short/long retry limit 211 */ 212#define RTW_INTR_TNPDOK (1<<6) /* Tx Normal Priority Descriptor OK */ 213#define RTW_INTR_RXFOVW (1<<5) /* Rx FIFO Overflow: either RDU (see below) 214 * or PCI bus too slow/busy 215 */ 216#define RTW_INTR_RDU (1<<4) /* Rx Descriptor Unavailable */ 217#define RTW_INTR_TLPDER (1<<3) /* Tx Normal Priority Descriptor Error 218 * reached short/long retry limit 219 */ 220#define RTW_INTR_TLPDOK (1<<2) /* Tx Normal Priority Descriptor OK */ 221#define RTW_INTR_RER (1<<1) /* Rx Error: CRC32 or ICV error */ 222#define RTW_INTR_ROK (1<<0) /* Rx OK */ 223 224/* Convenient interrupt conjunctions. */ 225#define RTW_INTR_RX (RTW_INTR_RER|RTW_INTR_ROK) 226#define RTW_INTR_TX (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\ 227 RTW_INTR_THPDOK|RTW_INTR_TNPDER|RTW_INTR_TNPDOK|\ 228 RTW_INTR_TBDER|RTW_INTR_TBDOK) 229#define RTW_INTR_BEACON (RTW_INTR_BCNINT|RTW_INTR_TBDER|RTW_INTR_TBDOK) 230#define RTW_INTR_IOERROR (RTW_INTR_TXFOVW|RTW_INTR_RXFOVW|RTW_INTR_RDU) 231 232#define RTW_TCR 0x40 /* Transmit Configuration Register, 32b */ 233#define RTW_TCR_CWMIN (1<<31) /* 1: CWmin = 8, 0: CWmin = 32. */ 234#define RTW_TCR_SWSEQ (1<<30) /* 1: host assigns 802.11 sequence number, 235 * 0: hardware assigns sequence number 236 */ 237#define RTW8185_TCR_NOPROBERSPTO (1<<29) /* No Probe Rsp timeout */ 238/* Hardware version ID, read-only */ 239#define RTW_TCR_HWVERID_MASK 0xe000000 240#define RTW_TCR_HWVERID_RTL8180D (1<<26) 241#define RTW_TCR_HWVERID_RTL8180F 0x6000000 242#define RTW_TCR_HWVERID_RTL8185 ((1<<27) | (1<<25)) 243/* Set ACK/CTS Timeout (EIFS). 244 * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?) 245 * 0: ACK rate = 1Mbps 246 */ 247#define RTW8180_TCR_SAT (1<<24) 248/* 1: Software PLCP length, 249 * 0: Hardware PLCP length 250 */ 251#define RTW8185_TCR_PLCPLENGTH (1<<24) 252/* Max DMA Burst Size per Tx DMA Burst */ 253#define RTW_TCR_MXDMA_MASK 0xe00000 254#define RTW_TCR_MXDMA_16 LSHIFT(0, RTW_TCR_MXDMA_MASK) 255#define RTW_TCR_MXDMA_32 LSHIFT(1, RTW_TCR_MXDMA_MASK) 256#define RTW_TCR_MXDMA_64 LSHIFT(2, RTW_TCR_MXDMA_MASK) 257#define RTW_TCR_MXDMA_128 LSHIFT(3, RTW_TCR_MXDMA_MASK) 258#define RTW_TCR_MXDMA_256 LSHIFT(4, RTW_TCR_MXDMA_MASK) 259#define RTW_TCR_MXDMA_512 LSHIFT(5, RTW_TCR_MXDMA_MASK) 260#define RTW_TCR_MXDMA_1024 LSHIFT(6, RTW_TCR_MXDMA_MASK) 261#define RTW_TCR_MXDMA_2048 LSHIFT(7, RTW_TCR_MXDMA_MASK) 262 263#define RTW_TCR_DISCW (1<<20) /* disable 802.11 random backoff */ 264 265#define RTW_TCR_ICV (1<<19) /* host lets RTL8180 append ICV to 266 * WEP packets 267 */ 268 269/* Loopback Test: disables TXI/TXQ outputs. */ 270#define RTW_TCR_LBK_MASK 0x60000 271#define RTW_TCR_LBK_NORMAL LSHIFT(0, RTW_TCR_LBK_MASK) /* normal ops */ 272#define RTW_TCR_LBK_MAC LSHIFT(1, RTW_TCR_LBK_MASK) /* MAC loopback */ 273#define RTW_TCR_LBK_BBP LSHIFT(2, RTW_TCR_LBK_MASK) /* baseband loop. */ 274#define RTW_TCR_LBK_CONT LSHIFT(3, RTW_TCR_LBK_MASK) /* continuous Tx */ 275 276#define RTW_TCR_CRC (1<<16) /* 0: RTL8180 appends CRC32 277 * 1: host appends CRC32 278 * 279 * (I *think* this is right. 280 * The docs have a mysterious 281 * description in the 282 * passive voice.) 283 */ 284#define RTW_TCR_SRL_MASK 0xff00 /* Short Retry Limit */ 285#define RTW_TCR_LRL_MASK 0xff /* Long Retry Limit */ 286 287#define RTW_RCR 0x44 /* Receive Configuration Register, 32b */ 288#define RTW_RCR_ONLYERLPKT (1<<31) /* only do Early Rx on packets 289 * longer than 1536 bytes 290 */ 291#define RTW_RCR_ENCS2 (1<<30) /* enable carrier sense method 2 */ 292#define RTW_RCR_ENCS1 (1<<29) /* enable carrier sense method 1 */ 293#define RTW_RCR_ENMARP (1<<28) /* enable MAC auto-reset PHY */ 294#define RTW_RCR_CBSSID (1<<23) /* Check BSSID/ToDS/FromDS: set 295 * "Link On" when received BSSID 296 * matches RTW_BSSID and received 297 * ToDS/FromDS are appropriate 298 * according to RTW_MSR_NETYPE. 299 */ 300#define RTW_RCR_APWRMGT (1<<22) /* accept packets w/ PWRMGMT bit set */ 301#define RTW_RCR_ADD3 (1<<21) /* when RTW_MSR_NETYPE == 302 * RTW_MSR_NETYPE_INFRA_OK, accept 303 * broadcast/multicast packets whose 304 * 3rd address matches RTL8180's MAC. 305 */ 306#define RTW_RCR_AMF (1<<20) /* accept management frames */ 307#define RTW_RCR_ACF (1<<19) /* accept control frames */ 308#define RTW_RCR_ADF (1<<18) /* accept data frames */ 309/* Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data 310 * bytes are received 311 */ 312#define RTW8180_RCR_RXFTH_MASK 0xe000 313#define RTW8180_RCR_RXFTH_64 LSHIFT(2, RTW8180_RCR_RXFTH_MASK) 314#define RTW8180_RCR_RXFTH_128 LSHIFT(3, RTW8180_RCR_RXFTH_MASK) 315#define RTW8180_RCR_RXFTH_256 LSHIFT(4, RTW8180_RCR_RXFTH_MASK) 316#define RTW8180_RCR_RXFTH_512 LSHIFT(5, RTW8180_RCR_RXFTH_MASK) 317#define RTW8180_RCR_RXFTH_1024 LSHIFT(6, RTW8180_RCR_RXFTH_MASK) 318#define RTW8180_RCR_RXFTH_WHOLE LSHIFT(7, RTW8180_RCR_RXFTH_MASK) 319 320#define RTW_RCR_AICV (1<<12) /* accept frames w/ ICV errors */ 321 322/* Max DMA Burst Size per Rx DMA Burst */ 323#define RTW_RCR_MXDMA_MASK 0x700 324#define RTW_RCR_MXDMA_16 LSHIFT(0, RTW_RCR_MXDMA_MASK) 325#define RTW_RCR_MXDMA_32 LSHIFT(1, RTW_RCR_MXDMA_MASK) 326#define RTW_RCR_MXDMA_64 LSHIFT(2, RTW_RCR_MXDMA_MASK) 327#define RTW_RCR_MXDMA_128 LSHIFT(3, RTW_RCR_MXDMA_MASK) 328#define RTW_RCR_MXDMA_256 LSHIFT(4, RTW_RCR_MXDMA_MASK) 329#define RTW_RCR_MXDMA_512 LSHIFT(5, RTW_RCR_MXDMA_MASK) 330#define RTW_RCR_MXDMA_1024 LSHIFT(6, RTW_RCR_MXDMA_MASK) 331#define RTW_RCR_MXDMA_UNLIMITED LSHIFT(7, RTW_RCR_MXDMA_MASK) 332 333/* EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 */ 334#define RTW_RCR_9356SEL (1<<6) 335 336#define RTW_RCR_ACRC32 (1<<5) /* accept frames w/ CRC32 errors */ 337#define RTW_RCR_AB (1<<3) /* accept broadcast frames */ 338#define RTW_RCR_AM (1<<2) /* accept multicast frames */ 339/* accept physical match frames. XXX means PLCP header ok? */ 340#define RTW_RCR_APM (1<<1) 341#define RTW_RCR_AAP (1<<0) /* accept frames w/ destination */ 342 343/* Additional bits to set in monitor mode. */ 344#define RTW_RCR_MONITOR ( \ 345 RTW_RCR_AAP | \ 346 RTW_RCR_ACF | \ 347 RTW_RCR_ACRC32 | \ 348 RTW_RCR_AICV | \ 349 0) 350 351/* The packet filter bits. */ 352#define RTW_RCR_PKTFILTER_MASK (\ 353 RTW_RCR_AAP | \ 354 RTW_RCR_AB | \ 355 RTW_RCR_ACF | \ 356 RTW_RCR_ACRC32 | \ 357 RTW_RCR_ADD3 | \ 358 RTW_RCR_ADF | \ 359 RTW_RCR_AICV | \ 360 RTW_RCR_AM | \ 361 RTW_RCR_AMF | \ 362 RTW_RCR_APM | \ 363 RTW_RCR_APWRMGT | \ 364 0) 365 366/* Receive power-management frames and mgmt/ctrl/data frames. */ 367#define RTW_RCR_PKTFILTER_DEFAULT ( \ 368 RTW_RCR_ADF | \ 369 RTW_RCR_AMF | \ 370 RTW_RCR_APM | \ 371 RTW_RCR_APWRMGT | \ 372 0) 373 374#define RTW_TINT 0x48 /* Timer Interrupt Register, 32b */ 375#define RTW_TBDA 0x4c /* Transmit Beacon Descriptor Start Address, 376 * 32b, 256-byte alignment 377 */ 378#define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */ 379#define RTW_9346CR_EEM_MASK 0xc0 /* Operating Mode */ 380#define RTW_9346CR_EEM_NORMAL LSHIFT(0, RTW_9346CR_EEM_MASK) 381/* Load the EEPROM. Reset registers to defaults. 382 * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL. 383 * XXX RTL8180 only? 384 */ 385#define RTW_9346CR_EEM_AUTOLOAD LSHIFT(1, RTW_9346CR_EEM_MASK) 386/* Disable network & bus-master operations and enable 387 * _EECS, _EESK, _EEDI, _EEDO. 388 * XXX RTL8180 only? 389 */ 390#define RTW_9346CR_EEM_PROGRAM LSHIFT(2, RTW_9346CR_EEM_MASK) 391/* Enable RTW_CONFIG[0123] registers. */ 392#define RTW_9346CR_EEM_CONFIG LSHIFT(3, RTW_9346CR_EEM_MASK) 393/* EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes. 394 * XXX RTL8180 only? 395 */ 396#define RTW_9346CR_EECS (1<<3) 397#define RTW_9346CR_EESK (1<<2) 398#define RTW_9346CR_EEDI (1<<1) 399#define RTW_9346CR_EEDO (1<<0) /* read-only */ 400 401#define RTW_CONFIG0 0x51 /* Configuration Register 0, 8b */ 402#define RTW8180_CONFIG0_WEP40 (1<<7) /* implements 40-bit WEP, 403 */ 404#define RTW8180_CONFIG0_WEP104 (1<<6) /* implements 104-bit WEP, 405 * from EEPROM, read-only 406 */ 407#define RTW8180_CONFIG0_LEDGPOEN (1<<4) /* 1: RTW_PSR_LEDGPO[01] control 408 * LED[01] pins. 409 * 0: LED behavior defined by 410 * RTW_CONFIG1_LEDS10_MASK 411 */ 412/* auxiliary power is present, read-only */ 413#define RTW_CONFIG0_AUXPWR (1<<3) 414/* Geographic Location, read-only */ 415#define RTW8180_CONFIG0_GL_MASK 0x3 416#define RTW8180_CONFIG0_GL_USA LSHIFT(3, RTW8180_CONFIG0_GL_MASK) 417#define RTW8180_CONFIG0_GL_EUROPE LSHIFT(2, RTW8180_CONFIG0_GL_MASK) 418#define RTW8180_CONFIG0_GL_JAPAN LSHIFT(1, RTW8180_CONFIG0_GL_MASK) 419#define RTW8180_CONFIG0_GL_JAPAN2 LSHIFT(0, RTW8180_CONFIG0_GL_MASK) 420/* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. */ 421 422#define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */ 423 424/* LED configuration. From EEPROM. Read/write. 425 * 426 * Setting LED0 LED1 427 * ------- ---- ---- 428 * RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure 429 * RTW_CONFIG1_LEDS_ACT_LINK Activity Link 430 * RTW_CONFIG1_LEDS_TX_RX Tx Rx 431 * RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure 432 */ 433#define RTW_CONFIG1_LEDS_MASK 0xc0 434#define RTW_CONFIG1_LEDS_ACT_INFRA LSHIFT(0, RTW_CONFIG1_LEDS_MASK) 435#define RTW_CONFIG1_LEDS_ACT_LINK LSHIFT(1, RTW_CONFIG1_LEDS_MASK) 436#define RTW_CONFIG1_LEDS_TX_RX LSHIFT(2, RTW_CONFIG1_LEDS_MASK) 437#define RTW_CONFIG1_LEDS_LINKACT_INFRA LSHIFT(3, RTW_CONFIG1_LEDS_MASK) 438 439/* LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms. 440 * 441 * RTW_CONFIG1_LWACT 442 * 0 1 443 * RTW_CONFIG4_LWPTN 0 active high active low 444 * 1 positive pulse negative pulse 445 */ 446#define RTW_CONFIG1_LWACT (1<<4) 447 448#define RTW_CONFIG1_MEMMAP (1<<3) /* using PCI memory space, read-only */ 449#define RTW_CONFIG1_IOMAP (1<<2) /* using PCI I/O space, read-only */ 450#define RTW_CONFIG1_VPD (1<<1) /* if set, VPD from offsets 451 * 0x40-0x7f in EEPROM are at 452 * registers 0x60-0x67 of PCI 453 * Configuration Space (XXX huh?) 454 */ 455#define RTW_CONFIG1_PMEN (1<<0) /* Power Management Enable: TBD */ 456 457#define RTW_CONFIG2 0x53 /* Configuration Register 2, 8b */ 458#define RTW_CONFIG2_LCK (1<<7) /* clocks are locked, read-only: 459 * Tx frequency & symbol clocks 460 * are derived from the same OSC 461 */ 462#define RTW8180_CONFIG2_ANT (1<<6) /* diversity enabled, read-only */ 463#define RTW_CONFIG2_DPS (1<<3) /* Descriptor Polling State: enable 464 * test mode. 465 */ 466#define RTW_CONFIG2_PAPESIGN (1<<2) /* TBD, from EEPROM */ 467#define RTW_CONFIG2_PAPETIME_MASK 0x3 /* TBD, from EEPROM */ 468 469#define RTW_ANAPARM_0 0x54 /* Analog parameter, 32b */ 470#define RTW8185_ANAPARM_1 0x60 471 472#define RTW_ANAPARM_RFPOW0_MASK 0x70000000 /* undocumented bits 473 * which appear to 474 * control the power 475 * state of the RF 476 * components 477 */ 478#define RTW_ANAPARM_RFPOW_MASK \ 479 (RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK) 480 481#define RTW_ANAPARM_TXDACOFF (1<<27) /* 1: disable Tx DAC, 482 * 0: enable 483 */ 484#define RTW_ANAPARM_RFPOW1_MASK 0x7f00000 /* undocumented bits 485 * which appear to 486 * control the power 487 * state of the RF 488 * components 489 */ 490 491/* 492 * Maxim On/Sleep/Off control 493 */ 494#define RTW_ANAPARM_RFPOW_MAXIM_ON LSHIFT(0x8, RTW_ANAPARM_RFPOW1_MASK) 495 496/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 497#define RTW_ANAPARM_RFPOW_MAXIM_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 498 499/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 500#define RTW_ANAPARM_RFPOW_MAXIM_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 501 502/* 503 * RFMD On/Sleep/Off control 504 */ 505#define RTW_ANAPARM_RFPOW_RFMD_ON LSHIFT(0x408, RTW_ANAPARM_RFPOW1_MASK) 506 507/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 508#define RTW_ANAPARM_RFPOW_RFMD_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 509 510/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 511#define RTW_ANAPARM_RFPOW_RFMD_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 512 513/* 514 * Philips On/Sleep/Off control 515 */ 516#define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON \ 517 LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK) 518#define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON \ 519 LSHIFT(0x008, RTW_ANAPARM_RFPOW1_MASK) 520 521/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 522#define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\ 523 LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK) 524 525/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */ 526#define RTW_ANAPARM_RFPOW_PHILIPS_OFF\ 527 LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK) 528 529#define RTW_ANAPARM_RFPOW_PHILIPS_ON LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK) 530 531#define RTW_ANAPARM_CARDSP_MASK 0xfffff /* undocumented 532 * card-specific 533 * bits from the 534 * EEPROM. 535 */ 536 537#define RTW_MSR 0x58 /* Media Status Register, 8b */ 538/* Network Type and Link Status */ 539#define RTW_MSR_NETYPE_MASK 0xc 540/* AP, XXX RTL8181 only? */ 541#define RTW_MSR_NETYPE_AP_OK LSHIFT(3, RTW_MSR_NETYPE_MASK) 542/* infrastructure link ok */ 543#define RTW_MSR_NETYPE_INFRA_OK LSHIFT(2, RTW_MSR_NETYPE_MASK) 544/* ad-hoc link ok */ 545#define RTW_MSR_NETYPE_ADHOC_OK LSHIFT(1, RTW_MSR_NETYPE_MASK) 546/* no link */ 547#define RTW_MSR_NETYPE_NOLINK LSHIFT(0, RTW_MSR_NETYPE_MASK) 548 549#define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */ 550#define RTW_CONFIG3_GNTSEL (1<<7) /* Grant Select, read-only */ 551#define RTW_CONFIG3_PARMEN (1<<6) /* Set RTW_CONFIG3_PARMEN and 552 * RTW_9346CR_EEM_CONFIG to 553 * allow RTW_ANAPARM writes. 554 */ 555#define RTW_CONFIG3_MAGIC (1<<5) /* Valid when RTW_CONFIG1_PMEN is 556 * set. If set, RTL8180 wakes up 557 * OS when Magic Packet is Rx'd. 558 */ 559#define RTW_CONFIG3_CARDBEN (1<<3) /* Cardbus-related registers 560 * and functions are enabled, 561 * read-only. XXX RTL8180 only. 562 */ 563#define RTW_CONFIG3_CLKRUNEN (1<<2) /* CLKRUN enabled, read-only. 564 * XXX RTL8180 only. 565 */ 566#define RTW_CONFIG3_FUNCREGEN (1<<1) /* Function Registers Enabled, 567 * read-only. XXX RTL8180 only. 568 */ 569#define RTW_CONFIG3_FBTBEN (1<<0) /* Fast back-to-back enabled, 570 * read-only. 571 */ 572#define RTW_CONFIG4 0x5A /* Configuration Register 4, 8b */ 573#define RTW_CONFIG4_VCOPDN (1<<7) /* VCO Power Down 574 * 0: normal operation 575 * (power-on default) 576 * 1: power-down VCO, RF front-end, 577 * and most RTL8180 components. 578 */ 579#define RTW_CONFIG4_PWROFF (1<<6) /* Power Off 580 * 0: normal operation 581 * (power-on default) 582 * 1: power-down RF front-end, 583 * and most RTL8180 components, 584 * but leave VCO on. 585 * 586 * XXX RFMD front-end only? 587 */ 588#define RTW_CONFIG4_PWRMGT (1<<5) /* Power Management 589 * 0: normal operation 590 * (power-on default) 591 * 1: set Tx packet's PWRMGMT bit. 592 */ 593#define RTW_CONFIG4_LWPME (1<<4) /* LANWAKE vs. PMEB: Cardbus-only 594 * 0: LWAKE & PMEB asserted 595 * simultaneously 596 * 1: LWAKE asserted only if 597 * both PMEB is asserted and 598 * ISOLATEB is low. 599 * XXX RTL8180 only. 600 */ 601#define RTW_CONFIG4_LWPTN (1<<2) /* see RTW_CONFIG1_LWACT 602 * XXX RTL8180 only. 603 */ 604/* Radio Front-End Programming Method */ 605#define RTW_CONFIG4_RFTYPE_MASK 0x3 606#define RTW_CONFIG4_RFTYPE_INTERSIL LSHIFT(1, RTW_CONFIG4_RFTYPE_MASK) 607#define RTW_CONFIG4_RFTYPE_RFMD LSHIFT(2, RTW_CONFIG4_RFTYPE_MASK) 608#define RTW_CONFIG4_RFTYPE_PHILIPS LSHIFT(3, RTW_CONFIG4_RFTYPE_MASK) 609 610#define RTW_TESTR 0x5B /* TEST mode register, 8b */ 611 612#define RTW_PSR 0x5e /* Page Select Register, 8b */ 613#define RTW_PSR_GPO (1<<7) /* Control/status of pin 52. */ 614#define RTW_PSR_GPI (1<<6) /* Status of pin 64. */ 615#define RTW_PSR_LEDGPO1 (1<<5) /* Status/control of LED1 pin if 616 * RTW_CONFIG0_LEDGPOEN is set. 617 */ 618#define RTW_PSR_LEDGPO0 (1<<4) /* Status/control of LED0 pin if 619 * RTW_CONFIG0_LEDGPOEN is set. 620 */ 621#define RTW_PSR_UWF (1<<1) /* Enable Unicast Wakeup Frame */ 622#define RTW_PSR_PSEN (1<<0) /* 1: page 1, 0: page 0 */ 623 624#define RTW8180_SCR 0x5f /* Security Configuration Register, 8b */ 625#define RTW8180_SCR_KM_MASK 0x30 /* Key Mode */ 626#define RTW8180_SCR_KM_WEP104 LSHIFT(1, RTW8180_SCR_KM_MASK) 627#define RTW8180_SCR_KM_WEP40 LSHIFT(0, RTW8180_SCR_KM_MASK) 628#define RTW8180_SCR_TXSECON (1<<1) /* Enable Tx WEP. Invalid if 629 * neither RTW_CONFIG0_WEP40 nor 630 * RTW_CONFIG0_WEP104 is set. 631 */ 632#define RTW8180_SCR_RXSECON (1<<0) /* Enable Rx WEP. Invalid if 633 * neither RTW_CONFIG0_WEP40 nor 634 * RTW_CONFIG0_WEP104 is set. 635 */ 636 637#define RTW8185_RFPARM 0x60 /* RF Parameter Register, 32b */ 638 639#define RTW_BCNITV 0x70 /* Beacon Interval Register, 16b */ 640#define RTW_BCNITV_BCNITV_MASK 0x3ff /* TU between TBTT, written 641 * by host. 642 */ 643#define RTW_ATIMWND 0x72 /* ATIM Window Register, 16b */ 644#define RTW_ATIMWND_ATIMWND 0x3ff /* ATIM Window length in TU, 645 * written by host. 646 */ 647 648#define RTW_BINTRITV 0x74 /* Beacon Interrupt Interval Register, 16b */ 649#define RTW_BINTRITV_BINTRITV 0x3ff /* RTL8180 wakes host with 650 * RTW_INTR_BCNINT at BINTRITV 651 * microseconds before TBTT 652 */ 653#define RTW_ATIMTRITV 0x76 /* ATIM Interrupt Interval Register, 16b */ 654#define RTW_ATIMTRITV_ATIMTRITV 0x3ff /* RTL8180 wakes host with 655 * RTW_INTR_ATIMINT at ATIMTRITV 656 * microseconds before end of 657 * ATIM Window 658 */ 659 660#define RTW_PHYDELAY 0x78 /* PHY Delay Register, 8b */ 661#define RTW_PHYDELAY_REVC_MAGIC (1<<3) /* Rev. C magic from reference 662 * driver 663 */ 664#define RTW_PHYDELAY_PHYDELAY 0x7 /* microsecond Tx delay between 665 * MAC and RF front-end 666 */ 667#define RTW_CRCOUNT 0x79 /* Carrier Sense Counter, 8b */ 668#define RTW_CRCOUNT_MAGIC 0x4c 669 670#define RTW_CRC16ERR 0x7a /* CRC16 error count, 16b, XXX RTL8181 only? */ 671 672#define RTW_BB 0x7c /* Baseband interface, 32b */ 673/* used for writing RTL8180's integrated baseband processor */ 674#define RTW_BB_RD_MASK 0xff0000 /* data to read */ 675#define RTW_BB_WR_MASK 0xff00 /* data to write */ 676#define RTW_BB_WREN (1<<7) /* write enable */ 677#define RTW_BB_ADDR_MASK 0x7f /* address */ 678 679#define RTW_PHYADDR 0x7c /* Address register for PHY interface, 8b */ 680#define RTW_PHYDATAW 0x7d /* Write data to PHY, 8b, write-only */ 681#define RTW_PHYDATAR 0x7e /* Read data from PHY, 8b (?), read-only */ 682 683#define RTW8180_PHYCFG 0x80 /* PHY Configuration Register, 32b */ 684#define RTW8180_PHYCFG_MAC_POLL (1<<31) /* if !RTW8180_PHYCFG_HST, 685 * host sets. MAC clears 686 * after banging bits. 687 */ 688#define RTW8180_PHYCFG_HST (1<<30) /* 1: host bangs bits 689 * 0: MAC bangs bits 690 */ 691#define RTW8180_PHYCFG_MAC_RFTYPE_MASK 0x30000000 692#define RTW8180_PHYCFG_MAC_RFTYPE_INTERSIL \ 693 LSHIFT(0, RTW8180_PHYCFG_MAC_RFTYPE_MASK) 694#define RTW8180_PHYCFG_MAC_RFTYPE_RFMD \ 695 LSHIFT(1, RTW8180_PHYCFG_MAC_RFTYPE_MASK) 696#define RTW8180_PHYCFG_MAC_RFTYPE_GCT \ 697 RTW8180_PHYCFG_MAC_RFTYPE_RFMD 698#define RTW8180_PHYCFG_MAC_RFTYPE_PHILIPS \ 699 LSHIFT(3, RTW8180_PHYCFG_MAC_RFTYPE_MASK) 700#define RTW8180_PHYCFG_MAC_PHILIPS_ADDR_MASK 0xf000000 701#define RTW8180_PHYCFG_MAC_PHILIPS_DATA_MASK 0xffffff 702#define RTW8180_PHYCFG_MAC_MAXIM_LODATA_MASK 0xf000000 703#define RTW8180_PHYCFG_MAC_MAXIM_ADDR_MASK 0xf00 704#define RTW8180_PHYCFG_MAC_MAXIM_HIDATA_MASK 0xff 705#define RTW8180_PHYCFG_HST_EN (1<<2) 706#define RTW8180_PHYCFG_HST_CLK (1<<1) 707#define RTW8180_PHYCFG_HST_DATA (1<<0) 708 709#define RTW8185_RFPINSOUTPUT 0x80 710#define RTW8185_RFPINSOUTPUT_MASK 0xfff3 711 712#define RTW8185_RFPINSENABLE 0x82 713#define RTW8185_RFPINSENABLE_ENABLE 0x0007 714 715#define RTW8185_INSSELECT 0x84 716#define RTW8185_SW_GPIO 0x400 717 718#define RTW_MAXIM_HIDATA_MASK 0xff0 719#define RTW_MAXIM_LODATA_MASK 0xf 720 721/** 722 ** 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1. 723 **/ 724 725#define RTW_WAKEUP0L 0x84 /* Power Management Wakeup Frame */ 726#define RTW_WAKEUP0H 0x88 /* 32b */ 727 728#define RTW_WAKEUP1L 0x8c 729#define RTW_WAKEUP1H 0x90 730 731#define RTW_WAKEUP2LL 0x94 732#define RTW_WAKEUP2LH 0x98 733 734#define RTW_WAKEUP2HL 0x9c 735#define RTW_WAKEUP2HH 0xa0 736 737#define RTW_WAKEUP3LL 0xa4 738#define RTW_WAKEUP3LH 0xa8 739 740#define RTW_WAKEUP3HL 0xac 741#define RTW_WAKEUP3HH 0xb0 742 743#define RTW_WAKEUP4LL 0xb4 744#define RTW_WAKEUP4LH 0xb8 745 746#define RTW_WAKEUP4HL 0xbc 747#define RTW_WAKEUP4HH 0xc0 748 749#define RTW_CRC0 0xc4 /* CRC of wakeup frame 0, 16b */ 750#define RTW_CRC1 0xc6 /* CRC of wakeup frame 1, 16b */ 751#define RTW_CRC2 0xc8 /* CRC of wakeup frame 2, 16b */ 752#define RTW_CRC3 0xca /* CRC of wakeup frame 3, 16b */ 753#define RTW_CRC4 0xcc /* CRC of wakeup frame 4, 16b */ 754 755/** 756 ** 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0. 757 **/ 758 759/* Default Key Registers, each 128b 760 * 761 * If RTW8180_SCR_KM_WEP104, 104 lsb are the key. 762 * If RTW8180_SCR_KM_WEP40, 40 lsb are the key. 763 */ 764#define RTW8180_DK0 0x90 /* Default Key 0 Register, 128b */ 765#define RTW8180_DK1 0xa0 /* Default Key 1 Register, 128b */ 766#define RTW8180_DK2 0xb0 /* Default Key 2 Register, 128b */ 767#define RTW8180_DK3 0xc0 /* Default Key 3 Register, 128b */ 768 769#define RTW8185_RFPINSSELECT 0x84 770#define RTW8185_RFPINSSELECT_ENABLE 0x0007 771 772#define RTW8185_RFPINSINPUT 0x86 773#define RTW8185_RFPARA 0x88 774#define RTW8185_RFTIMING 0x8c 775#define RTW8185_GPO 0x90 776#define RTW8185_GPE 0x91 777#define RTW8185_GPI 0x92 778#define RTW8185_TXAGCCTL 0x9c 779#define RTW8185_CCKTXAGC 0x9d 780#define RTW8185_OFDMTXAGC 0x9e 781#define RTW8185_ANTSEL 0x9f 782 783#define RTW8185_CAMRW 0xa0 /* CAM R/W Register, 32b */ 784#define RTW8185_CAMRW_POOLING (1<<31) /* Pooling bit */ 785#define RTW8185_CAMRW_WRITE (1<<16) /* Write enable */ 786#define RTW8185_CAMRW_ADDRESS 0x7f /* CAM address */ 787 788#define RTW8185_CAMOUTPUT 0xa4 789#define RTW8185_CAMINPUT 0xa8 790 791#define RTW8185_CAMDEBUG 0xac /* CAM Debug Interface, 32b */ 792#define RTW8185_CAMDEBUG_SELTXRXINFO (1<<31) 793#define RTW8185_CAMDEBUG_KEYFOUND (1<<30) 794#define RTW8185_CAMDEBUG_WPACONFIG 0x3f000000 795#define RTW8185_CAMDEBUG_CAMKEY 0xffffff 796 797#define RTW8185_WPACONFIG 0xb0 /* WPA Config Register, 16b */ 798#define RTW8185_WPACONFIG_RXWPADUMMY (1<<8) 799#define RTW8185_WPACONFIG_DISRX_AESMIC (1<<3) 800#define RTW8185_WPACONFIG_RXDECRYPT (1<<2) 801#define RTW8185_WPACONFIG_TXENCRYPT (1<<1) 802#define RTW8185_WPACONFIG_USEDEFAULTKEY (1<<0) 803 804#define RTW8185_AESMASK 0xb2 805#define RTW8185_SIFS 0xb4 806#define RTW8185_DIFS 0xb5 807#define RTW8185_SLOTTIME 0xb6 808#define RTW8185_UTUNE 0xb7 809 810#define RTW8185_CWCONFIG 0xbc /* CW Config Register, 8b */ 811#define RTW8185_CWCONFIG_PPRETRYLIMIT (1<<1) /* Per-Packet Retry Limit */ 812#define RTW8185_CWCONFIG_PPCW (1<<1) /* Per-Packet Cont. Window */ 813 814#define RTW8185_CWVALUES 0xbd /* CW Values, 8b */ 815#define RTW8185_CWVALUES_CWMAX 0xf0 /* Max Contention Window */ 816#define RTW8185_CWVALUES_CWMIN 0xf /* Min Contention Window */ 817 818#define RTW8185_RATEFALLBACKCTL 0xbe /* Auto Rate Fallback, 8b */ 819#define RTW8185_RATEFALLBACKCTL_ENABLE (1<<7) 820#define RTW8185_RATEFALLBACKCTL_STEP 0x3 821 822#define RTW_CONFIG5 0xd8 /* Configuration Register 5, 8b */ 823#define RTW_CONFIG5_TXFIFOOK (1<<7) /* Tx FIFO self-test pass, read-only */ 824#define RTW_CONFIG5_RXFIFOOK (1<<6) /* Rx FIFO self-test pass, read-only */ 825#define RTW_CONFIG5_CALON (1<<5) /* 1: start calibration cycle 826 * and raise AGCRESET pin. 827 * 0: lower AGCRESET pin 828 */ 829#define RTW_CONFIG5_EACPI (1<<2) /* Enable ACPI Wake up, default 0 */ 830#define RTW_CONFIG5_LANWAKE (1<<1) /* Enable LAN Wake signal, 831 * from EEPROM 832 */ 833#define RTW_CONFIG5_PMESTS (1<<0) /* 1: both software & PCI Reset 834 * reset PME_Status 835 * 0: only software resets PME_Status 836 * 837 * From EEPROM. 838 */ 839 840#define RTW_TPPOLL 0xd9 /* Transmit Priority Polling Register, 8b, 841 * write-only. 842 */ 843#define RTW_TPPOLL_BQ (1<<7) /* RTL8180 clears to notify host of a beacon 844 * Tx. Host writes have no effect. 845 */ 846#define RTW_TPPOLL_HPQ (1<<6) /* Host writes 1 to notify RTL8180 of 847 * high-priority Tx packets, RTL8180 clears 848 * to after high-priority Tx is complete. 849 */ 850#define RTW_TPPOLL_NPQ (1<<5) /* If RTW_CONFIG2_DPS is set, 851 * host writes 1 to notify RTL8180 of 852 * normal-priority Tx packets, RTL8180 clears 853 * after normal-priority Tx is complete. 854 * 855 * If RTW_CONFIG2_DPS is clear, host writes 856 * have no effect. RTL8180 clears after 857 * normal-priority Tx is complete. 858 */ 859#define RTW_TPPOLL_LPQ (1<<4) /* Host writes 1 to notify RTL8180 of 860 * low-priority Tx packets, RTL8180 clears 861 * after low-priority Tx is complete. 862 */ 863#define RTW_TPPOLL_SBQ (1<<3) /* Host writes 1 to tell RTL8180 to 864 * stop beacon DMA. This bit is invalid 865 * when RTW_CONFIG2_DPS is set. 866 */ 867#define RTW_TPPOLL_SHPQ (1<<2) /* Host writes 1 to tell RTL8180 to 868 * stop high-priority DMA. 869 */ 870#define RTW_TPPOLL_SNPQ (1<<1) /* Host writes 1 to tell RTL8180 to 871 * stop normal-priority DMA. This bit is invalid 872 * when RTW_CONFIG2_DPS is set. 873 */ 874#define RTW_TPPOLL_SLPQ (1<<0) /* Host writes 1 to tell RTL8180 to 875 * stop low-priority DMA. 876 */ 877 878/* Start all queues. */ 879#define RTW_TPPOLL_ALL (RTW_TPPOLL_BQ | RTW_TPPOLL_HPQ | \ 880 RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ) 881/* Check all queues' activity. */ 882#define RTW_TPPOLL_ACTIVE RTW_TPPOLL_ALL 883/* Stop all queues. */ 884#define RTW_TPPOLL_SALL (RTW_TPPOLL_SBQ | RTW_TPPOLL_SHPQ | \ 885 RTW_TPPOLL_SNPQ | RTW_TPPOLL_SLPQ) 886 887#define RTW_CWR 0xdc /* Contention Window Register, 16b, read-only */ 888/* Contention Window: indicates number of contention windows before Tx 889 */ 890#define RTW_CWR_CW 0x3ff 891 892/* Retry Count Register, 16b, read-only */ 893#define RTW_RETRYCTR 0xde 894/* Retry Count: indicates number of retries after Tx */ 895#define RTW_RETRYCTR_RETRYCT 0xff 896 897#define RTW_RDSAR 0xe4 /* Receive descriptor Start Address Register, 898 * 32b, 256-byte alignment. 899 */ 900/* Function Event Register, 32b, Cardbus only. Only valid when 901 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 902 */ 903#define RTW_FER 0xf0 904#define RTW_FER_INTR (1<<15) /* set when RTW_FFER_INTR is set */ 905#define RTW_FER_GWAKE (1<<4) /* General Wakeup */ 906/* Function Event Mask Register, 32b, Cardbus only. Only valid when 907 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set. 908 */ 909#define RTW_FEMR 0xf4 910#define RTW_FEMR_INTR (1<<15) /* set when RTW_FFER_INTR is set */ 911#define RTW_FEMR_WKUP (1<<14) /* Wakeup Mask */ 912#define RTW_FEMR_GWAKE (1<<4) /* General Wakeup */ 913/* Function Present State Register, 32b, read-only, Cardbus only. 914 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 915 * are set. 916 */ 917#define RTW_FPSR 0xf8 918#define RTW_FPSR_INTR (1<<15) /* TBD */ 919#define RTW_FPSR_GWAKE (1<<4) /* General Wakeup: TBD */ 920/* Function Force Event Register, 32b, write-only, Cardbus only. 921 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN 922 * are set. 923 */ 924#define RTW_FFER 0xfc 925#define RTW_FFER_INTR (1<<15) /* TBD */ 926#define RTW_FFER_GWAKE (1<<4) /* General Wakeup: TBD */ 927 928/* Serial EEPROM offsets */ 929#define RTW_SR_ID 0x00 /* 16b */ 930#define RTW_SR_VID 0x02 /* 16b */ 931#define RTW_SR_DID 0x04 /* 16b */ 932#define RTW_SR_SVID 0x06 /* 16b */ 933#define RTW_SR_SMID 0x08 /* 16b */ 934#define RTW_SR_MNGNT 0x0a 935#define RTW_SR_MXLAT 0x0b 936#define RTW_SR_RFCHIPID 0x0c 937#define RTW_SR_CONFIG3 0x0d 938#define RTW_SR_MAC 0x0e /* 6 bytes */ 939#define RTW_SR_CONFIG0 0x14 940#define RTW_SR_CONFIG1 0x15 941#define RTW_SR_PMC 0x16 /* Power Management Capabilities, 16b */ 942#define RTW_SR_CONFIG2 0x18 943#define RTW_SR_CONFIG4 0x19 944#define RTW_SR_ANAPARM 0x1a /* Analog Parameters, 32b */ 945#define RTW_SR_TESTR 0x1e 946#define RTW_SR_CONFIG5 0x1f 947#define RTW_SR_TXPOWER1 0x20 948#define RTW_SR_TXPOWER2 0x21 949#define RTW_SR_TXPOWER3 0x22 950#define RTW_SR_TXPOWER4 0x23 951#define RTW_SR_TXPOWER5 0x24 952#define RTW_SR_TXPOWER6 0x25 953#define RTW_SR_TXPOWER7 0x26 954#define RTW_SR_TXPOWER8 0x27 955#define RTW_SR_TXPOWER9 0x28 956#define RTW_SR_TXPOWER10 0x29 957#define RTW_SR_TXPOWER11 0x2a 958#define RTW_SR_TXPOWER12 0x2b 959#define RTW_SR_TXPOWER13 0x2c 960#define RTW_SR_TXPOWER14 0x2d 961#define RTW_SR_CHANNELPLAN 0x2e /* bitmap of channels to scan */ 962#define RTW_SR_ENERGYDETTHR 0x2f /* energy-detect threshold */ 963#define RTW_SR_ENERGYDETTHR_DEFAULT 0x0c /* use this if old SROM */ 964#define RTW_SR_CISPOINTER 0x30 /* 16b */ 965#define RTW_SR_RFPARM 0x32 /* RF-specific parameter */ 966#define RTW_SR_RFPARM_DIGPHY (1<<0) /* 1: digital PHY */ 967#define RTW_SR_RFPARM_DFLANTB (1<<1) /* 1: antenna B is default */ 968#define RTW_SR_RFPARM_CS_MASK 0xc /* carrier-sense type */ 969#define RTW_SR_VERSION 0x3c /* EEPROM content version, 16b */ 970#define RTW_SR_CRC 0x3e /* EEPROM content CRC, 16b */ 971#define RTW_SR_VPD 0x40 /* Vital Product Data, 64 bytes */ 972#define RTW_SR_CIS 0x80 /* CIS Data, 93c56 only, 128 bytes*/ 973 974/* 975 * RTL8180 Transmit/Receive Descriptors 976 */ 977 978/* the first descriptor in each ring must be on a 256-byte boundary */ 979#define RTW_DESC_ALIGNMENT 256 980 981/* Tx descriptor */ 982struct rtw_txdesc { 983 u_int32_t td_ctl0; 984 u_int32_t td_ctl1; 985 u_int32_t td_buf; 986 u_int32_t td_len; 987 u_int32_t td_next; 988 u_int32_t td_rsvd[3]; 989}; 990 991#define td_stat td_ctl0 992 993#define RTW_TXCTL0_OWN (1<<31) /* 1: ready to Tx */ 994#define RTW_TXCTL0_RSVD0 (1<<30) /* reserved */ 995#define RTW_TXCTL0_FS (1<<29) /* first segment */ 996#define RTW_TXCTL0_LS (1<<28) /* last segment */ 997 998#define RTW_TXCTL0_RATE_MASK 0xf000000 /* Tx rate */ 999#define RTW_TXCTL0_RATE_1MBPS LSHIFT(0, RTW_TXCTL0_RATE_MASK) 1000#define RTW_TXCTL0_RATE_2MBPS LSHIFT(1, RTW_TXCTL0_RATE_MASK) 1001#define RTW_TXCTL0_RATE_5MBPS LSHIFT(2, RTW_TXCTL0_RATE_MASK) 1002#define RTW_TXCTL0_RATE_11MBPS LSHIFT(3, RTW_TXCTL0_RATE_MASK) 1003 1004#define RTW_TXCTL0_RTSEN (1<<23) /* RTS Enable */ 1005 1006#define RTW_TXCTL0_RTSRATE_MASK 0x780000 /* Tx rate */ 1007#define RTW_TXCTL0_RTSRATE_1MBPS LSHIFT(0, RTW_TXCTL0_RTSRATE_MASK) 1008#define RTW_TXCTL0_RTSRATE_2MBPS LSHIFT(1, RTW_TXCTL0_RTSRATE_MASK) 1009#define RTW_TXCTL0_RTSRATE_5MBPS LSHIFT(2, RTW_TXCTL0_RTSRATE_MASK) 1010#define RTW_TXCTL0_RTSRATE_11MBPS LSHIFT(3, RTW_TXCTL0_RTSRATE_MASK) 1011 1012#define RTW_TXCTL0_BEACON (1<<18) /* packet is a beacon */ 1013#define RTW_TXCTL0_MOREFRAG (1<<17) /* another fragment follows */ 1014#define RTW_TXCTL0_SPLCP (1<<16) /* add short PLCP preamble 1015 * and header 1016 */ 1017#define RTW_TXCTL0_KEYID_MASK 0xc000 /* default key id */ 1018#define RTW_TXCTL0_RSVD1_MASK 0x3000 /* reserved */ 1019#define RTW_TXCTL0_TPKTSIZE_MASK 0xfff /* Tx packet size 1020 * in bytes 1021 */ 1022 1023#define RTW_TXSTAT_OWN RTW_TXCTL0_OWN 1024#define RTW_TXSTAT_RSVD0 RTW_TXCTL0_RSVD0 1025#define RTW_TXSTAT_FS RTW_TXCTL0_FS 1026#define RTW_TXSTAT_LS RTW_TXCTL0_LS 1027#define RTW_TXSTAT_RSVD1_MASK 0xfff0000 1028#define RTW_TXSTAT_TOK (1<<15) 1029#define RTW_TXSTAT_RTSRETRY_MASK 0x7f00 /* RTS retry count */ 1030#define RTW_TXSTAT_DRC_MASK 0xff /* Data retry count */ 1031 1032#define RTW_TXCTL1_LENGEXT (1<<31) /* supplements _LENGTH 1033 * in packets sent 5.5Mb/s or 1034 * faster 1035 */ 1036#define RTW_TXCTL1_LENGTH_MASK 0x7fff0000 /* PLCP length (microseconds) */ 1037#define RTW_TXCTL1_RTSDUR_MASK 0xffff /* RTS Duration 1038 * (microseconds) 1039 */ 1040 1041#define RTW_TXLEN_LENGTH_MASK 0xfff /* Tx buffer length in bytes */ 1042 1043/* Rx descriptor */ 1044struct rtw_rxdesc { 1045 u_int32_t rd_ctl; 1046 u_int32_t rd_rsvd0; 1047 u_int32_t rd_buf; 1048 u_int32_t rd_rsvd1; 1049}; 1050 1051#define rd_stat rd_ctl 1052#define rd_rssi rd_rsvd0 1053#define rd_tsftl rd_buf /* valid only when RTW_RXSTAT_LS is set */ 1054#define rd_tsfth rd_rsvd1 /* valid only when RTW_RXSTAT_LS is set */ 1055 1056#define RTW_RXCTL_OWN (1<<31) /* 1: owned by NIC */ 1057#define RTW_RXCTL_EOR (1<<30) /* end of ring */ 1058#define RTW_RXCTL_FS (1<<29) /* first segment */ 1059#define RTW_RXCTL_LS (1<<28) /* last segment */ 1060#define RTW_RXCTL_RSVD0_MASK 0x3ffff000 /* reserved */ 1061#define RTW_RXCTL_LENGTH_MASK 0xfff /* Rx buffer length */ 1062 1063#define RTW_RXSTAT_OWN RTW_RXCTL_OWN 1064#define RTW_RXSTAT_EOR RTW_RXCTL_EOR 1065#define RTW_RXSTAT_FS RTW_RXCTL_FS /* first segment */ 1066#define RTW_RXSTAT_LS RTW_RXCTL_LS /* last segment */ 1067#define RTW_RXSTAT_DMAFAIL (1<<27) /* DMA failure on this pkt */ 1068#define RTW_RXSTAT_BOVF (1<<26) /* buffer overflow XXX means 1069 * FIFO exhausted? 1070 */ 1071#define RTW_RXSTAT_SPLCP (1<<25) /* Rx'd with short preamble 1072 * and PLCP header 1073 */ 1074#define RTW_RXSTAT_RSVD1 (1<<24) /* reserved */ 1075#define RTW_RXSTAT_RATE_MASK 0xf00000 /* Rx rate */ 1076#define RTW_RXSTAT_RATE_1MBPS LSHIFT(0, RTW_RXSTAT_RATE_MASK) 1077#define RTW_RXSTAT_RATE_2MBPS LSHIFT(1, RTW_RXSTAT_RATE_MASK) 1078#define RTW_RXSTAT_RATE_5MBPS LSHIFT(2, RTW_RXSTAT_RATE_MASK) 1079#define RTW_RXSTAT_RATE_11MBPS LSHIFT(3, RTW_RXSTAT_RATE_MASK) 1080#define RTW_RXSTAT_MIC (1<<19) /* XXX from reference driver */ 1081#define RTW_RXSTAT_MAR (1<<18) /* is multicast */ 1082#define RTW_RXSTAT_PAR (1<<17) /* matches RTL8180's MAC */ 1083#define RTW_RXSTAT_BAR (1<<16) /* is broadcast */ 1084#define RTW_RXSTAT_RES (1<<15) /* error summary. valid when 1085 * RTW_RXSTAT_LS set. indicates 1086 * that either RTW_RXSTAT_CRC32 1087 * or RTW_RXSTAT_ICV is set. 1088 */ 1089#define RTW_RXSTAT_PWRMGT (1<<14) /* 802.11 PWRMGMT bit is set */ 1090#define RTW_RXSTAT_CRC16 (1<<14) /* XXX CRC16 error, from 1091 * reference driver 1092 */ 1093#define RTW_RXSTAT_CRC32 (1<<13) /* CRC32 error */ 1094#define RTW_RXSTAT_ICV (1<<12) /* ICV error */ 1095#define RTW_RXSTAT_LENGTH_MASK 0xfff /* frame length, including 1096 * CRC32 1097 */ 1098 1099/* Convenient status conjunction. */ 1100#define RTW_RXSTAT_ONESEG (RTW_RXSTAT_FS|RTW_RXSTAT_LS) 1101/* Convenient status disjunctions. */ 1102#define RTW_RXSTAT_IOERROR (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF) 1103#define RTW_RXSTAT_DEBUG (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\ 1104 RTW_RXSTAT_PAR|RTW_RXSTAT_BAR|\ 1105 RTW_RXSTAT_PWRMGT|RTW_RXSTAT_CRC32|\ 1106 RTW_RXSTAT_ICV) 1107 1108 1109#define RTW_RXRSSI_VLAN 0xfffe /* XXX from reference driver */ 1110/* for Philips RF front-ends */ 1111#define RTW_RXRSSI_RSSI 0xff00 /* RF energy at the PHY */ 1112/* for RF front-ends by Intersil, Maxim, RFMD */ 1113#define RTW_RXRSSI_IMR_RSSI 0xfe00 /* RF energy at the PHY */ 1114#define RTW_RXRSSI_IMR_LNA (1<<8) /* 1: LNA activated */ 1115#define RTW_RXRSSI_SQ 0xff /* Barker code-lock quality */ 1116 1117#define RTW_READ8(regs, ofs) \ 1118 ((*(regs)->r_read8)(regs, ofs)) 1119 1120#define RTW_READ16(regs, ofs) \ 1121 ((*(regs)->r_read16)(regs, ofs)) 1122 1123#define RTW_READ(regs, ofs) \ 1124 ((*(regs)->r_read32)(regs, ofs)) 1125 1126#define RTW_WRITE8(regs, ofs, val) \ 1127 ((*(regs)->r_write8)(regs, ofs, val)) 1128 1129#define RTW_WRITE16(regs, ofs, val) \ 1130 ((*(regs)->r_write16)(regs, ofs, val)) 1131 1132#define RTW_WRITE(regs, ofs, val) \ 1133 ((*(regs)->r_write32)(regs, ofs, val)) 1134 1135#define RTW_ISSET(regs, reg, mask) \ 1136 (RTW_READ((regs), (reg)) & (mask)) 1137 1138#define RTW_CLR(regs, reg, mask) \ 1139 RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask)) 1140 1141/* bus_space(9) lied? */ 1142#ifndef BUS_SPACE_BARRIER_SYNC 1143#define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 1144#endif 1145 1146#ifndef BUS_SPACE_BARRIER_READ_BEFORE_READ 1147#define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ 1148#endif 1149 1150#ifndef BUS_SPACE_BARRIER_READ_BEFORE_WRITE 1151#define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ 1152#endif 1153 1154#ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_READ 1155#define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE 1156#endif 1157 1158#ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE 1159#define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE 1160#endif 1161 1162/* 1163 * Bus barrier 1164 * 1165 * Complete outstanding read and/or write ops on [reg0, reg1] 1166 * ([reg1, reg0]) before starting new ops on the same region. See 1167 * acceptable bus_space_barrier(9) for the flag definitions. 1168 */ 1169#define RTW_BARRIER(regs, reg0, reg1, flags) \ 1170 ((*(regs)->r_barrier)(regs, reg0, reg1, flags)) 1171 1172/* 1173 * Barrier convenience macros. 1174 */ 1175/* sync */ 1176#define RTW_SYNC(regs, reg0, reg1) \ 1177 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC) 1178 1179/* write-before-write */ 1180#define RTW_WBW(regs, reg0, reg1) \ 1181 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1182 1183/* write-before-read */ 1184#define RTW_WBR(regs, reg0, reg1) \ 1185 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ) 1186 1187/* read-before-read */ 1188#define RTW_RBR(regs, reg0, reg1) \ 1189 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ) 1190 1191/* read-before-read */ 1192#define RTW_RBW(regs, reg0, reg1) \ 1193 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE) 1194 1195#define RTW_WBRW(regs, reg0, reg1) \ 1196 RTW_BARRIER(regs, reg0, reg1, \ 1197 BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \ 1198 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 1199 1200/* 1201 * Registers for RTL8180L's built-in baseband modem. 1202 */ 1203#define RTW_BBP_SYS1 0x00 1204#define RTW_BBP_TXAGC 0x03 /* guess: transmit auto gain control */ 1205#define RTW_BBP_LNADET 0x04 /* guess: low-noise amplifier activation 1206 * threshold 1207 */ 1208#define RTW_BBP_IFAGCINI 0x05 /* guess: intermediate frequency (IF) 1209 * auto-gain control (AGC) initial value 1210 */ 1211#define RTW_BBP_IFAGCLIMIT 0x06 /* guess: IF AGC maximum value */ 1212#define RTW_BBP_IFAGCDET 0x07 /* guess: activation threshold for 1213 * IF AGC loop 1214 */ 1215 1216#define RTW_BBP_ANTATTEN 0x10 /* guess: antenna & attenuation */ 1217#define RTW_BBP_ANTATTEN_PHILIPS_MAGIC 0x91 1218#define RTW_BBP_ANTATTEN_INTERSIL_MAGIC 0x92 1219#define RTW_BBP_ANTATTEN_RFMD_MAGIC 0x93 1220#define RTW_BBP_ANTATTEN_GCT_MAGIC 0xa3 1221#define RTW_BBP_ANTATTEN_MAXIM_MAGIC 0xb3 1222#define RTW_BBP_ANTATTEN_DFLANTB 0x40 1223#define RTW_BBP_ANTATTEN_CHAN14 0x0c 1224 1225#define RTW_BBP_TRL 0x11 /* guess: transmit/receive 1226 * switch latency 1227 */ 1228#define RTW_BBP_SYS2 0x12 1229#define RTW_BBP_SYS2_ANTDIV 0x80 /* enable antenna diversity */ 1230#define RTW_BBP_SYS2_RATE_MASK 0x30 /* loopback rate? 1231 * 0: 1Mbps 1232 * 1: 2Mbps 1233 * 2: 5.5Mbps 1234 * 3: 11Mbps 1235 */ 1236#define RTW_BBP_SYS3 0x13 1237/* carrier-sense threshold */ 1238#define RTW_BBP_SYS3_CSTHRESH_MASK 0xf 1239#define RTW_BBP_CHESTLIM 0x19 /* guess: channel energy-detect 1240 * threshold 1241 */ 1242#define RTW_BBP_CHSQLIM 0x1a /* guess: channel signal-quality 1243 * threshold 1244 */ 1245