rtl81x9reg.h revision 1.72
1/* $OpenBSD: rtl81x9reg.h,v 1.72 2010/11/28 22:08:59 kettenis Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.14 1999/10/21 19:42:03 wpaul Exp $ 35 */ 36 37/* 38 * RealTek 8129/8139 register offsets 39 */ 40#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 41#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 42#define RL_IDR2 0x0002 43#define RL_IDR3 0x0003 44#define RL_IDR4 0x0004 45#define RL_IDR5 0x0005 46 /* 0006-0007 reserved */ 47#define RL_MAR0 0x0008 /* Multicast hash table */ 48#define RL_MAR1 0x0009 49#define RL_MAR2 0x000A 50#define RL_MAR3 0x000B 51#define RL_MAR4 0x000C 52#define RL_MAR5 0x000D 53#define RL_MAR6 0x000E 54#define RL_MAR7 0x000F 55 56#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 57#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 58#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 59#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 60 61#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 62#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 63#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 64#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 65 66#define RL_RXADDR 0x0030 /* RX ring start address */ 67#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 68#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 69#define RL_COMMAND 0x0037 /* command register */ 70#define RL_CURRXADDR 0x0038 /* current address of packet read */ 71#define RL_CURRXBUF 0x003A /* current RX buffer address */ 72#define RL_IMR 0x003C /* interrupt mask register */ 73#define RL_ISR 0x003E /* interrupt status register */ 74#define RL_TXCFG 0x0040 /* transmit config */ 75#define RL_RXCFG 0x0044 /* receive config */ 76#define RL_TIMERCNT 0x0048 /* timer count register */ 77#define RL_MISSEDPKT 0x004C /* missed packet counter */ 78#define RL_EECMD 0x0050 /* EEPROM command register */ 79#define RL_CFG0 0x0051 /* config register #0 */ 80#define RL_CFG1 0x0052 /* config register #1 */ 81#define RL_CFG2 0x0053 /* config register #2 */ 82#define RL_CFG3 0x0054 /* config register #3 */ 83#define RL_CFG4 0x0055 /* config register #4 */ 84#define RL_CFG5 0x0056 /* config register #5 */ 85 /* 0057 reserved */ 86#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 87 /* 0059-005A reserved */ 88#define RL_MII 0x005A /* 8129 chip only */ 89#define RL_HALTCLK 0x005B 90#define RL_MULTIINTR 0x005C /* multiple interrupt */ 91#define RL_PCIREV 0x005E /* PCI revision value */ 92 /* 005F reserved */ 93#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 94 95#define RL_CSIDR 0x0064 96#define RL_CSIAR 0x0068 97 98/* Direct PHY access registers only available on 8139 */ 99#define RL_BMCR 0x0062 /* PHY basic mode control */ 100#define RL_BMSR 0x0064 /* PHY basic mode status */ 101#define RL_ANAR 0x0066 /* PHY autoneg advert */ 102#define RL_LPAR 0x0068 /* PHY link partner ability */ 103#define RL_ANER 0x006A /* PHY autoneg expansion */ 104 105#define RL_DISCCNT 0x006C /* disconnect counter */ 106#define RL_FALSECAR 0x006E /* false carrier counter */ 107#define RL_NWAYTST 0x0070 /* NWAY test register */ 108#define RL_RX_ER 0x0072 /* RX_ER counter */ 109#define RL_CSCFG 0x0074 /* CS configuration register */ 110 111/* 112 * When operating in special C+ mode, some of the registers in an 113 * 8139C+ chip have different definitions. These are also used for 114 * the 8169 gigE chip. 115 */ 116#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 117#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 118#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 119#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 120#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte aligned */ 121#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte aligned */ 122#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 123#define RL_TXSTART 0x00D9 /* 8 bits */ 124#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 125#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 126#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 127#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 128 129/* 130 * Registers specific to the 8169 gigE chip 131 */ 132#define RL_GTXSTART 0x0038 /* 8 bits */ 133#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 134#define RL_PHYAR 0x0060 135#define RL_TBICSR 0x0064 136#define RL_TBI_ANAR 0x0068 137#define RL_TBI_LPAR 0x006A 138#define RL_GMEDIASTAT 0x006C /* 8 bits */ 139#define RL_MACDBG 0x006D /* 8 bits */ 140#define RL_GPIO 0x006E /* 8 bits */ 141#define RL_PMCH 0x006F /* 8 bits */ 142#define RL_LDPS 0x0082 /* Link Down Power Saving */ 143#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 144#define RL_IM 0x00E2 145 146/* 147 * TX config register bits 148 */ 149#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 150#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 151#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 152#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 153#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 154#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 155#define RL_TXCFG_HWREV 0x7C800000 156 157#define RL_LOOPTEST_OFF 0x00000000 158#define RL_LOOPTEST_ON 0x00020000 159#define RL_LOOPTEST_ON_CPLUS 0x00060000 160 161/* Known revision codes. */ 162 163#define RL_HWREV_8169 0x00000000 164#define RL_HWREV_8169S 0x00800000 165#define RL_HWREV_8110S 0x04000000 166#define RL_HWREV_8169_8110SB 0x10000000 167#define RL_HWREV_8169_8110SCd 0x18000000 168#define RL_HWREV_8102EL 0x24800000 169#define RL_HWREV_8103E 0x24C00000 170#define RL_HWREV_8168D 0x28000000 171#define RL_HWREV_8168DP 0x28800000 172#define RL_HWREV_8168E 0x2C000000 173#define RL_HWREV_8168_SPIN1 0x30000000 174#define RL_HWREV_8100E_SPIN1 0x30800000 175#define RL_HWREV_8101E 0x34000000 176#define RL_HWREV_8102E 0x34800000 177#define RL_HWREV_8168_SPIN2 0x38000000 178#define RL_HWREV_8168_SPIN3 0x38400000 179#define RL_HWREV_8100E_SPIN2 0x38800000 180#define RL_HWREV_8168C 0x3c000000 181#define RL_HWREV_8168C_SPIN2 0x3c400000 182#define RL_HWREV_8168CP 0x3c800000 183#define RL_HWREV_8139 0x60000000 184#define RL_HWREV_8139A 0x70000000 185#define RL_HWREV_8139AG 0x70800000 186#define RL_HWREV_8139B 0x78000000 187#define RL_HWREV_8130 0x7C000000 188#define RL_HWREV_8139C 0x74000000 189#define RL_HWREV_8139D 0x74400000 190#define RL_HWREV_8139CPLUS 0x74800000 191#define RL_HWREV_8101 0x74c00000 192#define RL_HWREV_8100 0x78800000 193#define RL_HWREV_8169_8110SBL 0x7cc00000 194#define RL_HWREV_8169_8110SCe 0x98000000 195 196#define RL_TXDMA_16BYTES 0x00000000 197#define RL_TXDMA_32BYTES 0x00000100 198#define RL_TXDMA_64BYTES 0x00000200 199#define RL_TXDMA_128BYTES 0x00000300 200#define RL_TXDMA_256BYTES 0x00000400 201#define RL_TXDMA_512BYTES 0x00000500 202#define RL_TXDMA_1024BYTES 0x00000600 203#define RL_TXDMA_2048BYTES 0x00000700 204 205/* 206 * Transmit descriptor status register bits. 207 */ 208#define RL_TXSTAT_LENMASK 0x00001FFF 209#define RL_TXSTAT_OWN 0x00002000 210#define RL_TXSTAT_TX_UNDERRUN 0x00004000 211#define RL_TXSTAT_TX_OK 0x00008000 212#define RL_TXSTAT_EARLY_THRESH 0x003F0000 213#define RL_TXSTAT_COLLCNT 0x0F000000 214#define RL_TXSTAT_CARR_HBEAT 0x10000000 215#define RL_TXSTAT_OUTOFWIN 0x20000000 216#define RL_TXSTAT_TXABRT 0x40000000 217#define RL_TXSTAT_CARRLOSS 0x80000000 218 219/* 220 * Interrupt status register bits. 221 */ 222#define RL_ISR_RX_OK 0x0001 223#define RL_ISR_RX_ERR 0x0002 224#define RL_ISR_TX_OK 0x0004 225#define RL_ISR_TX_ERR 0x0008 226#define RL_ISR_RX_OVERRUN 0x0010 227#define RL_ISR_PKT_UNDERRUN 0x0020 228#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 229#define RL_ISR_FIFO_OFLOW 0x0040 230#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 231#define RL_ISR_SWI 0x0100 /* C+ only */ 232#define RL_ISR_CABLE_LEN_CHGD 0x2000 233#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 234#define RL_ISR_TIMEOUT_EXPIRED 0x4000 235#define RL_ISR_SYSTEM_ERR 0x8000 236 237#define RL_INTRS \ 238 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 239 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 240 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 241 242#define RL_INTRS_CPLUS \ 243 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 244 RL_ISR_RX_OVERRUN|RL_ISR_FIFO_OFLOW|RL_ISR_LINKCHG| \ 245 RL_ISR_SYSTEM_ERR|RL_ISR_TX_OK) 246 247#define RL_INTRS_TIMER \ 248 (RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 249 RL_ISR_LINKCHG|RL_ISR_SYSTEM_ERR| \ 250 RL_ISR_TIMEOUT_EXPIRED) 251 252/* 253 * Media status register. (8139 only) 254 */ 255#define RL_MEDIASTAT_RXPAUSE 0x01 256#define RL_MEDIASTAT_TXPAUSE 0x02 257#define RL_MEDIASTAT_LINK 0x04 258#define RL_MEDIASTAT_SPEED10 0x08 259#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 260#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 261 262/* 263 * Receive config register. 264 */ 265#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 266#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 267#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 268#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 269#define RL_RXCFG_RX_RUNT 0x00000010 270#define RL_RXCFG_RX_ERRPKT 0x00000020 271#define RL_RXCFG_WRAP 0x00000080 272#define RL_RXCFG_MAXDMA 0x00000700 273#define RL_RXCFG_BURSZ 0x00001800 274#define RL_RXCFG_FIFOTHRESH 0x0000E000 275#define RL_RXCFG_EARLYTHRESH 0x07000000 276 277#define RL_RXDMA_16BYTES 0x00000000 278#define RL_RXDMA_32BYTES 0x00000100 279#define RL_RXDMA_64BYTES 0x00000200 280#define RL_RXDMA_128BYTES 0x00000300 281#define RL_RXDMA_256BYTES 0x00000400 282#define RL_RXDMA_512BYTES 0x00000500 283#define RL_RXDMA_1024BYTES 0x00000600 284#define RL_RXDMA_UNLIMITED 0x00000700 285 286#define RL_RXBUF_8 0x00000000 287#define RL_RXBUF_16 0x00000800 288#define RL_RXBUF_32 0x00001000 289#define RL_RXBUF_64 0x00001800 290 291#define RL_RXFIFO_16BYTES 0x00000000 292#define RL_RXFIFO_32BYTES 0x00002000 293#define RL_RXFIFO_64BYTES 0x00004000 294#define RL_RXFIFO_128BYTES 0x00006000 295#define RL_RXFIFO_256BYTES 0x00008000 296#define RL_RXFIFO_512BYTES 0x0000A000 297#define RL_RXFIFO_1024BYTES 0x0000C000 298#define RL_RXFIFO_NOTHRESH 0x0000E000 299 300/* 301 * Bits in RX status header (included with RX'ed packet 302 * in ring buffer). 303 */ 304#define RL_RXSTAT_RXOK 0x00000001 305#define RL_RXSTAT_ALIGNERR 0x00000002 306#define RL_RXSTAT_CRCERR 0x00000004 307#define RL_RXSTAT_GIANT 0x00000008 308#define RL_RXSTAT_RUNT 0x00000010 309#define RL_RXSTAT_BADSYM 0x00000020 310#define RL_RXSTAT_BROAD 0x00002000 311#define RL_RXSTAT_INDIV 0x00004000 312#define RL_RXSTAT_MULTI 0x00008000 313#define RL_RXSTAT_LENMASK 0xFFFF0000 314 315#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 316/* 317 * Command register. 318 */ 319#define RL_CMD_EMPTY_RXBUF 0x0001 320#define RL_CMD_TX_ENB 0x0004 321#define RL_CMD_RX_ENB 0x0008 322#define RL_CMD_RESET 0x0010 323#define RL_CMD_STOPREQ 0x0080 324 325/* 326 * EEPROM control register 327 */ 328#define RL_EE_DATAOUT 0x01 /* Data out */ 329#define RL_EE_DATAIN 0x02 /* Data in */ 330#define RL_EE_CLK 0x04 /* clock */ 331#define RL_EE_SEL 0x08 /* chip select */ 332#define RL_EE_MODE (0x40|0x80) 333 334#define RL_EEMODE_OFF 0x00 335#define RL_EEMODE_AUTOLOAD 0x40 336#define RL_EEMODE_PROGRAM 0x80 337#define RL_EEMODE_WRITECFG (0x80|0x40) 338 339/* 9346/9356 EEPROM commands */ 340 341#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 342#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 343 344#define RL_9346_WRITE 0x5 345#define RL_9346_READ 0x6 346#define RL_9346_ERASE 0x7 347#define RL_9346_EWEN 0x4 348#define RL_9346_EWEN_ADDR 0x30 349#define RL_9456_EWDS 0x4 350#define RL_9346_EWDS_ADDR 0x00 351 352#define RL_EECMD_WRITE 0x5 /* 0101b */ 353#define RL_EECMD_READ 0x6 /* 0110b */ 354#define RL_EECMD_ERASE 0x7 /* 0111b */ 355#define RL_EECMD_LEN 4 356 357#define RL_EEADDR_LEN0 6 /* 9346 */ 358#define RL_EEADDR_LEN1 8 /* 9356 */ 359 360#define RL_EECMD_READ_6BIT 0x180 /* XXX */ 361#define RL_EECMD_READ_8BIT 0x600 /* EECMD_READ above maybe wrong? */ 362 363#define RL_EE_ID 0x00 364#define RL_EE_PCI_VID 0x01 365#define RL_EE_PCI_DID 0x02 366/* Location of station address inside EEPROM */ 367#define RL_EE_EADDR 0x07 368 369/* 370 * MII register (8129 only) 371 */ 372#define RL_MII_CLK 0x01 373#define RL_MII_DATAIN 0x02 374#define RL_MII_DATAOUT 0x04 375#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 376 377/* 378 * Config 0 register 379 */ 380#define RL_CFG0_ROM0 0x01 381#define RL_CFG0_ROM1 0x02 382#define RL_CFG0_ROM2 0x04 383#define RL_CFG0_PL0 0x08 384#define RL_CFG0_PL1 0x10 385#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 386#define RL_CFG0_PCS 0x40 387#define RL_CFG0_SCR 0x80 388 389/* 390 * Config 1 register 391 */ 392#define RL_CFG1_PWRDWN 0x01 393#define RL_CFG1_PME 0x01 394#define RL_CFG1_SLEEP 0x02 395#define RL_CFG1_VPDEN 0x02 396#define RL_CFG1_IOMAP 0x04 397#define RL_CFG1_MEMMAP 0x08 398#define RL_CFG1_RSVD 0x10 399#define RL_CFG1_LWACT 0x10 400#define RL_CFG1_DRVLOAD 0x20 401#define RL_CFG1_LED0 0x40 402#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 403#define RL_CFG1_LED1 0x80 404 405/* 406 * Config 2 register 407 */ 408#define RL_CFG2_PCI_MASK 0x07 409#define RL_CFG2_PCI_33MHZ 0x00 410#define RL_CFG2_PCI_66MHZ 0x01 411#define RL_CFG2_PCI_64BIT 0x08 412#define RL_CFG2_AUXPWR 0x10 413 414/* 415 * Config 3 register 416 */ 417#define RL_CFG3_GRANTSEL 0x80 418#define RL_CFG3_WOL_MAGIC 0x20 419#define RL_CFG3_WOL_LINK 0x10 420#define RL_CFG3_FAST_B2B 0x01 421 422/* 423 * Config 4 register 424 */ 425#define RL_CFG4_LWPTN 0x04 426#define RL_CFG4_LWPME 0x10 427 428/* 429 * Config 5 register 430 */ 431#define RL_CFG5_WOL_BCAST 0x40 432#define RL_CFG5_WOL_MCAST 0x20 433#define RL_CFG5_WOL_UCAST 0x10 434#define RL_CFG5_WOL_LANWAKE 0x02 435#define RL_CFG5_PME_STS 0x01 436 437/* 438 * 8139C+ register definitions 439 */ 440 441/* RL_DUMPSTATS_LO register */ 442 443#define RL_DUMPSTATS_START 0x00000008 444 445/* Transmit start register */ 446 447#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 448#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 449#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 450 451/* 452 * Config 2 register, 8139C+/8169/8169S/8110S only 453 */ 454#define RL_CFG2_BUSFREQ 0x07 455#define RL_CFG2_BUSWIDTH 0x08 456#define RL_CFG2_AUXPWRSTS 0x10 457 458#define RL_BUSFREQ_33MHZ 0x00 459#define RL_BUSFREQ_66MHZ 0x01 460 461#define RL_BUSWIDTH_32BITS 0x00 462#define RL_BUSWIDTH_64BITS 0x08 463 464/* C+ mode command register */ 465 466#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 467#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 468#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 469#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 470#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 471#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 472#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 473#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 474#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 475#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 476#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 477#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 478#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 479#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 480#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 481 482/* C+ early transmit threshold */ 483 484#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 485 486/* 487 * Gigabit PHY access register (8169 only) 488 */ 489 490#define RL_PHYAR_PHYDATA 0x0000FFFF 491#define RL_PHYAR_PHYREG 0x001F0000 492#define RL_PHYAR_BUSY 0x80000000 493 494/* 495 * Gigabit media status (8169 only) 496 */ 497#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 498#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 499#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 500#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 501#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 502#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 503#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 504#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 505 506/* 507 * The RealTek doesn't use a fragment-based descriptor mechanism. 508 * Instead, there are only four register sets, each of which represents 509 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 510 * packet buffer (32-bit aligned!) and we place the buffer addresses in 511 * the registers so the chip knows where they are. 512 * 513 * We can sort of kludge together the same kind of buffer management 514 * used in previous drivers, but we have to do buffer copies almost all 515 * the time, so it doesn't really buy us much. 516 * 517 * For reception, there's just one large buffer where the chip stores 518 * all received packets. 519 */ 520 521#define RL_RX_BUF_SZ RL_RXBUF_64 522#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 523#define RL_TX_LIST_CNT 4 524#define RL_MIN_FRAMELEN 60 525#define RL_TXTHRESH(x) ((x) << 11) 526#define RL_TX_THRESH_INIT 96 527#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 528#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 529#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 530 531#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 532#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 533 534#define RL_IM_MAGIC 0x5050 535#define RL_IM_RXTIME(t) ((t) & 0xf) 536#define RL_IM_TXTIME(t) (((t) & 0xf) << 8) 537 538struct rl_chain_data { 539 u_int16_t cur_rx; 540 caddr_t rl_rx_buf; 541 caddr_t rl_rx_buf_ptr; 542 bus_addr_t rl_rx_buf_pa; 543 544 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 545 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 546 u_int8_t last_tx; 547 u_int8_t cur_tx; 548}; 549 550 551/* 552 * The 8139C+ and 8160 gigE chips support descriptor-based TX 553 * and RX. In fact, they even support TCP large send. Descriptors 554 * must be allocated in contiguous blocks that are aligned on a 555 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 556 */ 557 558/* 559 * RX/TX descriptor definition. When large send mode is enabled, the 560 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 561 * the checksum offload bits are disabled. The structure layout is 562 * the same for RX and TX descriptors 563 */ 564 565struct rl_desc { 566 volatile u_int32_t rl_cmdstat; 567 volatile u_int32_t rl_vlanctl; 568 volatile u_int32_t rl_bufaddr_lo; 569 volatile u_int32_t rl_bufaddr_hi; 570}; 571 572#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 573#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 574#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 575#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 576#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 577#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 578#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 579#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 580#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 581#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 582 583#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 584#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 585/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 586#define RL_TDESC_CMD_IPCSUMV2 0x20000000 587#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 588#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 589 590/* 591 * Error bits are valid only on the last descriptor of a frame 592 * (i.e. RL_TDESC_CMD_EOF == 1) 593 */ 594 595#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 596#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 597#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 598#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 599#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 600#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 601#define RL_TDESC_STAT_OWN 0x80000000 602 603/* 604 * RX descriptor cmd/vlan definitions 605 */ 606 607#define RL_RDESC_CMD_EOR 0x40000000 608#define RL_RDESC_CMD_OWN 0x80000000 609#define RL_RDESC_CMD_BUFLEN 0x00001FFF 610 611#define RL_RDESC_STAT_OWN 0x80000000 612#define RL_RDESC_STAT_EOR 0x40000000 613#define RL_RDESC_STAT_SOF 0x20000000 614#define RL_RDESC_STAT_EOF 0x10000000 615#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 616#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 617#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 618#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 619#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 620#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 621#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 622#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 623#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 624#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 625#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 626#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 627#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 628#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 629#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 630#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 631#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 632#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 633#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 634 RL_RDESC_STAT_CRCERR) 635 636#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 637 (rl_vlandata valid)*/ 638#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 639/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 640#define RL_RDESC_IPV6 0x80000000 641#define RL_RDESC_IPV4 0x40000000 642 643#define RL_PROTOID_NONIP 0x00000000 644#define RL_PROTOID_TCPIP 0x00010000 645#define RL_PROTOID_UDPIP 0x00020000 646#define RL_PROTOID_IP 0x00030000 647#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 648 RL_PROTOID_TCPIP) 649#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 650 RL_PROTOID_UDPIP) 651 652/* 653 * Statistics counter structure (8139C+ and 8169 only) 654 */ 655struct rl_stats { 656 u_int32_t rl_tx_pkts_lo; 657 u_int32_t rl_tx_pkts_hi; 658 u_int32_t rl_tx_errs_lo; 659 u_int32_t rl_tx_errs_hi; 660 u_int32_t rl_tx_errs; 661 u_int16_t rl_missed_pkts; 662 u_int16_t rl_rx_framealign_errs; 663 u_int32_t rl_tx_onecoll; 664 u_int32_t rl_tx_multicolls; 665 u_int32_t rl_rx_ucasts_hi; 666 u_int32_t rl_rx_ucasts_lo; 667 u_int32_t rl_rx_bcasts_lo; 668 u_int32_t rl_rx_bcasts_hi; 669 u_int32_t rl_rx_mcasts; 670 u_int16_t rl_tx_aborts; 671 u_int16_t rl_rx_underruns; 672}; 673 674#define RL_RX_DESC_CNT 64 675#define RL_TX_DESC_CNT_8139 64 676#define RL_TX_DESC_CNT_8169 512 677 678#define RL_TX_QLEN 64 679 680#define RL_NTXDESC_RSVD 4 681 682#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 683#define RL_RING_ALIGN 256 684#define RL_PKTSZ(x) ((x)/* >> 3*/) 685#ifdef __STRICT_ALIGNMENT 686#define RE_ETHER_ALIGN 2 687#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 688#else 689#define RE_ETHER_ALIGN 0 690#define RE_RX_DESC_BUFLEN MCLBYTES 691#endif 692 693#define RL_TX_DESC_CNT(sc) \ 694 ((sc)->rl_ldata.rl_tx_desc_cnt) 695#define RL_TX_LIST_SZ(sc) \ 696 (RL_TX_DESC_CNT(sc) * sizeof(struct rl_desc)) 697#define RL_NEXT_TX_DESC(sc, x) \ 698 (((x) + 1) % RL_TX_DESC_CNT(sc)) 699#define RL_NEXT_RX_DESC(sc, x) \ 700 (((x) + 1) % RL_RX_DESC_CNT) 701#define RL_NEXT_TXQ(sc, x) \ 702 (((x) + 1) % RL_TX_QLEN) 703 704#define RL_TXDESCSYNC(sc, idx, ops) \ 705 bus_dmamap_sync((sc)->sc_dmat, \ 706 (sc)->rl_ldata.rl_tx_list_map, \ 707 sizeof(struct rl_desc) * (idx), \ 708 sizeof(struct rl_desc), \ 709 (ops)) 710#define RL_RXDESCSYNC(sc, idx, ops) \ 711 bus_dmamap_sync((sc)->sc_dmat, \ 712 (sc)->rl_ldata.rl_rx_list_map, \ 713 sizeof(struct rl_desc) * (idx), \ 714 sizeof(struct rl_desc), \ 715 (ops)) 716 717#define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) 718#define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32) 719 720/* see comment in dev/ic/re.c */ 721#define RL_JUMBO_FRAMELEN 7440 722#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 723 724#define MAX_NUM_MULTICAST_ADDRESSES 128 725 726#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 727#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 728#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 729#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 730#define RL_CUR_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 731#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 732#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 733#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 734#define RL_LAST_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 735 736struct rl_type { 737 u_int16_t rl_vid; 738 u_int16_t rl_did; 739}; 740 741struct rl_mii_frame { 742 u_int8_t mii_stdelim; 743 u_int8_t mii_opcode; 744 u_int8_t mii_phyaddr; 745 u_int8_t mii_regaddr; 746 u_int8_t mii_turnaround; 747 u_int16_t mii_data; 748}; 749 750/* 751 * MII constants 752 */ 753#define RL_MII_STARTDELIM 0x01 754#define RL_MII_READOP 0x02 755#define RL_MII_WRITEOP 0x01 756#define RL_MII_TURNAROUND 0x02 757 758#define RL_UNKNOWN 0 759#define RL_8129 1 760#define RL_8139 2 761 762struct rl_rxsoft { 763 struct mbuf *rxs_mbuf; 764 bus_dmamap_t rxs_dmamap; 765}; 766 767struct rl_txq { 768 struct mbuf *txq_mbuf; 769 bus_dmamap_t txq_dmamap; 770 int txq_descidx; 771 int txq_nsegs; 772}; 773 774struct rl_list_data { 775 struct rl_txq rl_txq[RL_TX_QLEN]; 776 int rl_txq_considx; 777 int rl_txq_prodidx; 778 779 bus_dmamap_t rl_tx_list_map; 780 struct rl_desc *rl_tx_list; 781 int rl_tx_free; /* # of free descriptors */ 782 int rl_tx_nextfree; /* next descriptor to use */ 783 int rl_tx_desc_cnt; /* # of descriptors */ 784 bus_dma_segment_t rl_tx_listseg; 785 int rl_tx_listnseg; 786 787 struct rl_rxsoft rl_rxsoft[RL_RX_DESC_CNT]; 788 bus_dmamap_t rl_rx_list_map; 789 struct rl_desc *rl_rx_list; 790 int rl_rx_considx; 791 int rl_rx_prodidx; 792 int rl_rx_cnt; 793 bus_dma_segment_t rl_rx_listseg; 794 int rl_rx_listnseg; 795}; 796 797struct rl_softc { 798 struct device sc_dev; /* us, as a device */ 799 void * sc_ih; /* interrupt vectoring */ 800 bus_space_handle_t rl_bhandle; /* bus space handle */ 801 bus_space_tag_t rl_btag; /* bus space tag */ 802 bus_dma_tag_t sc_dmat; 803 bus_dma_segment_t sc_rx_seg; 804 bus_dmamap_t sc_rx_dmamap; 805 struct arpcom sc_arpcom; /* interface info */ 806 struct mii_data sc_mii; /* MII information */ 807 u_int8_t rl_type; 808 u_int32_t sc_hwrev; 809 int rl_eecmd_read; 810 int rl_eewidth; 811 int rl_bus_speed; 812 int rl_txthresh; 813 struct rl_chain_data rl_cdata; 814 struct timeout sc_tick_tmo; 815 816 struct rl_list_data rl_ldata; 817 struct mbuf *rl_head; 818 struct mbuf *rl_tail; 819 u_int32_t rl_rxlenmask; 820 int rl_testmode; 821 struct timeout timer_handle; 822 823 int rl_txstart; 824 u_int32_t rl_flags; 825#define RL_FLAG_MSI 0x00000001 826#define RL_FLAG_PCI64 0x00000002 827#define RL_FLAG_PCIE 0x00000004 828#define RL_FLAG_INVMAR 0x00000008 829#define RL_FLAG_PHYWAKE 0x00000010 830#define RL_FLAG_NOJUMBO 0x00000020 831#define RL_FLAG_PAR 0x00000040 832#define RL_FLAG_DESCV2 0x00000080 833#define RL_FLAG_MACSTAT 0x00000100 834#define RL_FLAG_HWIM 0x00000200 835#define RL_FLAG_TIMERINTR 0x00000400 836#define RL_FLAG_MACLDPS 0x00000800 837#define RL_FLAG_CMDSTOP 0x00001000 838#define RL_FLAG_MACSLEEP 0x00002000 839#define RL_FLAG_AUTOPAD 0x00004000 840#define RL_FLAG_LINK 0x00008000 841#define RL_FLAG_PHYWAKE_PM 0x00010000 842 843 u_int16_t rl_intrs; 844 u_int16_t rl_tx_ack; 845 u_int16_t rl_rx_ack; 846 int rl_tx_time; 847 int rl_rx_time; 848 int rl_sim_time; 849 int rl_imtype; 850#define RL_IMTYPE_NONE 0 851#define RL_IMTYPE_SIM 1 /* simulated */ 852#define RL_IMTYPE_HW 2 /* hardware based */ 853}; 854 855/* 856 * re(4) hardware ip4csum-tx could be mangled with 28 byte or less IP packets 857 */ 858#define RL_IP4CSUMTX_MINLEN 28 859#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 860/* 861 * XXX 862 * We are allocating pad DMA buffer after RX DMA descs for now 863 * because RL_TX_LIST_SZ(sc) always occupies whole page but 864 * RL_RX_LIST_SZ is less than PAGE_SIZE so there is some unused region. 865 */ 866#define RL_RX_DMAMEM_SZ (RL_RX_LIST_SZ + RL_IP4CSUMTX_PADLEN) 867#define RL_TXPADOFF RL_RX_LIST_SZ 868#define RL_TXPADDADDR(sc) \ 869 ((sc)->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr + RL_TXPADOFF) 870 871/* 872 * register space access macros 873 */ 874#define CSR_WRITE_RAW_4(sc, csr, val) \ 875 bus_space_write_raw_region_4(sc->rl_btag, sc->rl_bhandle, csr, val, 4) 876#define CSR_WRITE_4(sc, csr, val) \ 877 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val) 878#define CSR_WRITE_2(sc, csr, val) \ 879 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val) 880#define CSR_WRITE_1(sc, csr, val) \ 881 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val) 882 883#define CSR_READ_4(sc, csr) \ 884 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, csr) 885#define CSR_READ_2(sc, csr) \ 886 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, csr) 887#define CSR_READ_1(sc, csr) \ 888 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, csr) 889 890#define CSR_SETBIT_1(sc, offset, val) \ 891 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 892 893#define CSR_CLRBIT_1(sc, offset, val) \ 894 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 895 896#define CSR_SETBIT_2(sc, offset, val) \ 897 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 898 899#define CSR_CLRBIT_2(sc, offset, val) \ 900 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 901 902#define CSR_SETBIT_4(sc, offset, val) \ 903 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 904 905#define CSR_CLRBIT_4(sc, offset, val) \ 906 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 907 908#define RL_TIMEOUT 1000 909#define RL_PHY_TIMEOUT 20 910 911/* 912 * General constants that are fun to know. 913 * 914 * RealTek PCI vendor ID 915 */ 916#define RT_VENDORID 0x10EC 917 918/* 919 * RealTek chip device IDs. 920 */ 921#define RT_DEVICEID_8129 0x8129 922#define RT_DEVICEID_8101E 0x8136 923#define RT_DEVICEID_8138 0x8138 924#define RT_DEVICEID_8139 0x8139 925#define RT_DEVICEID_8169SC 0x8167 926#define RT_DEVICEID_8168 0x8168 927#define RT_DEVICEID_8169 0x8169 928#define RT_DEVICEID_8100 0x8100 929 930/* 931 * Accton PCI vendor ID 932 */ 933#define ACCTON_VENDORID 0x1113 934 935/* 936 * Accton MPX 5030/5038 device ID. 937 */ 938#define ACCTON_DEVICEID_5030 0x1211 939 940/* 941 * Delta Electronics Vendor ID. 942 */ 943#define DELTA_VENDORID 0x1500 944 945/* 946 * Delta device IDs. 947 */ 948#define DELTA_DEVICEID_8139 0x1360 949 950/* 951 * Addtron vendor ID. 952 */ 953#define ADDTRON_VENDORID 0x4033 954 955/* 956 * Addtron device IDs. 957 */ 958#define ADDTRON_DEVICEID_8139 0x1360 959 960/* D-Link Vendor ID */ 961#define DLINK_VENDORID 0x1186 962 963/* D-Link device IDs */ 964#define DLINK_DEVICEID_8139 0x1300 965#define DLINK_DEVICEID_8139_2 0x1340 966 967/* Abocom device IDs */ 968#define ABOCOM_DEVICEID_8139 0xab06 969 970/* 971 * PCI low memory base and low I/O base register, and 972 * other PCI registers. Note: some are only available on 973 * the 3c905B, in particular those that related to power management. 974 */ 975 976#define RL_PCI_VENDOR_ID 0x00 977#define RL_PCI_DEVICE_ID 0x02 978#define RL_PCI_COMMAND 0x04 979#define RL_PCI_STATUS 0x06 980#define RL_PCI_CLASSCODE 0x09 981#define RL_PCI_LATENCY_TIMER 0x0D 982#define RL_PCI_HEADER_TYPE 0x0E 983#define RL_PCI_LOIO 0x10 984#define RL_PCI_LOMEM 0x14 985#define RL_PCI_BIOSROM 0x30 986#define RL_PCI_INTLINE 0x3C 987#define RL_PCI_INTPIN 0x3D 988#define RL_PCI_MINGNT 0x3E 989#define RL_PCI_MINLAT 0x0F 990#define RL_PCI_RESETOPT 0x48 991#define RL_PCI_EEPROM_DATA 0x4C 992 993#define RL_PCI_CAPID 0x50 /* 8 bits */ 994#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 995#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 996#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 997 998#define RL_PSTATE_MASK 0x0003 999#define RL_PSTATE_D0 0x0000 1000#define RL_PSTATE_D1 0x0001 1001#define RL_PSTATE_D2 0x0002 1002#define RL_PSTATE_D3 0x0003 1003#define RL_PME_EN 0x0010 1004#define RL_PME_STATUS 0x8000 1005 1006extern int rl_attach(struct rl_softc *); 1007extern int rl_intr(void *); 1008extern void rl_setmulti(struct rl_softc *); 1009int rl_detach(struct rl_softc *); 1010int rl_activate(struct device *, int); 1011