rtl81x9reg.h revision 1.4
1/* $OpenBSD: rtl81x9reg.h,v 1.4 2002/03/14 01:26:55 millert Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.14 1999/10/21 19:42:03 wpaul Exp $ 35 */ 36 37/* 38 * RealTek 8129/8139 register offsets 39 */ 40#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 41#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 42#define RL_IDR2 0x0002 43#define RL_IDR3 0x0003 44#define RL_IDR4 0x0004 45#define RL_IDR5 0x0005 46 /* 0006-0007 reserved */ 47#define RL_MAR0 0x0008 /* Multicast hash table */ 48#define RL_MAR1 0x0009 49#define RL_MAR2 0x000A 50#define RL_MAR3 0x000B 51#define RL_MAR4 0x000C 52#define RL_MAR5 0x000D 53#define RL_MAR6 0x000E 54#define RL_MAR7 0x000F 55 56#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 57#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 58#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 59#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 60 61#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 62#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 63#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 64#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 65 66#define RL_RXADDR 0x0030 /* RX ring start address */ 67#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 68#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 69#define RL_COMMAND 0x0037 /* command register */ 70#define RL_CURRXADDR 0x0038 /* current address of packet read */ 71#define RL_CURRXBUF 0x003A /* current RX buffer address */ 72#define RL_IMR 0x003C /* interrupt mask register */ 73#define RL_ISR 0x003E /* interrupt status register */ 74#define RL_TXCFG 0x0040 /* transmit config */ 75#define RL_RXCFG 0x0044 /* receive config */ 76#define RL_TIMERCNT 0x0048 /* timer count register */ 77#define RL_MISSEDPKT 0x004C /* missed packet counter */ 78#define RL_EECMD 0x0050 /* EEPROM command register */ 79#define RL_CFG0 0x0051 /* config register #0 */ 80#define RL_CFG1 0x0052 /* config register #1 */ 81 /* 0053-0057 reserved */ 82#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 83 /* 0059-005A reserved */ 84#define RL_MII 0x005A /* 8129 chip only */ 85#define RL_HALTCLK 0x005B 86#define RL_MULTIINTR 0x005C /* multiple interrupt */ 87#define RL_PCIREV 0x005E /* PCI revision value */ 88 /* 005F reserved */ 89#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 90 91/* Direct PHY access registers only available on 8139 */ 92#define RL_BMCR 0x0062 /* PHY basic mode control */ 93#define RL_BMSR 0x0064 /* PHY basic mode status */ 94#define RL_ANAR 0x0066 /* PHY autoneg advert */ 95#define RL_LPAR 0x0068 /* PHY link partner ability */ 96#define RL_ANER 0x006A /* PHY autoneg expansion */ 97 98#define RL_DISCCNT 0x006C /* disconnect counter */ 99#define RL_FALSECAR 0x006E /* false carrier counter */ 100#define RL_NWAYTST 0x0070 /* NWAY test register */ 101#define RL_RX_ER 0x0072 /* RX_ER counter */ 102#define RL_CSCFG 0x0074 /* CS configuration register */ 103 104 105/* 106 * TX config register bits 107 */ 108#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 109#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 110#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 111#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 112#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 113 114#define RL_TXDMA_16BYTES 0x00000000 115#define RL_TXDMA_32BYTES 0x00000100 116#define RL_TXDMA_64BYTES 0x00000200 117#define RL_TXDMA_128BYTES 0x00000300 118#define RL_TXDMA_256BYTES 0x00000400 119#define RL_TXDMA_512BYTES 0x00000500 120#define RL_TXDMA_1024BYTES 0x00000600 121#define RL_TXDMA_2048BYTES 0x00000700 122 123/* 124 * Transmit descriptor status register bits. 125 */ 126#define RL_TXSTAT_LENMASK 0x00001FFF 127#define RL_TXSTAT_OWN 0x00002000 128#define RL_TXSTAT_TX_UNDERRUN 0x00004000 129#define RL_TXSTAT_TX_OK 0x00008000 130#define RL_TXSTAT_EARLY_THRESH 0x003F0000 131#define RL_TXSTAT_COLLCNT 0x0F000000 132#define RL_TXSTAT_CARR_HBEAT 0x10000000 133#define RL_TXSTAT_OUTOFWIN 0x20000000 134#define RL_TXSTAT_TXABRT 0x40000000 135#define RL_TXSTAT_CARRLOSS 0x80000000 136 137/* 138 * Interrupt status register bits. 139 */ 140#define RL_ISR_RX_OK 0x0001 141#define RL_ISR_RX_ERR 0x0002 142#define RL_ISR_TX_OK 0x0004 143#define RL_ISR_TX_ERR 0x0008 144#define RL_ISR_RX_OVERRUN 0x0010 145#define RL_ISR_PKT_UNDERRUN 0x0020 146#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 147#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 148#define RL_ISR_SYSTEM_ERR 0x8000 149 150#define RL_INTRS \ 151 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 152 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 153 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 154 155/* 156 * Media status register. (8139 only) 157 */ 158#define RL_MEDIASTAT_RXPAUSE 0x01 159#define RL_MEDIASTAT_TXPAUSE 0x02 160#define RL_MEDIASTAT_LINK 0x04 161#define RL_MEDIASTAT_SPEED10 0x08 162#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 163#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 164 165/* 166 * Receive config register. 167 */ 168#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 169#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 170#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 171#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 172#define RL_RXCFG_RX_RUNT 0x00000010 173#define RL_RXCFG_RX_ERRPKT 0x00000020 174#define RL_RXCFG_WRAP 0x00000080 175#define RL_RXCFG_MAXDMA 0x00000700 176#define RL_RXCFG_BURSZ 0x00001800 177#define RL_RXCFG_FIFOTHRESH 0x0000E000 178#define RL_RXCFG_EARLYTHRESH 0x07000000 179 180#define RL_RXDMA_16BYTES 0x00000000 181#define RL_RXDMA_32BYTES 0x00000100 182#define RL_RXDMA_64BYTES 0x00000200 183#define RL_RXDMA_128BYTES 0x00000300 184#define RL_RXDMA_256BYTES 0x00000400 185#define RL_RXDMA_512BYTES 0x00000500 186#define RL_RXDMA_1024BYTES 0x00000600 187#define RL_RXDMA_UNLIMITED 0x00000700 188 189#define RL_RXBUF_8 0x00000000 190#define RL_RXBUF_16 0x00000800 191#define RL_RXBUF_32 0x00001000 192#define RL_RXBUF_64 0x00001800 193 194#define RL_RXFIFO_16BYTES 0x00000000 195#define RL_RXFIFO_32BYTES 0x00002000 196#define RL_RXFIFO_64BYTES 0x00004000 197#define RL_RXFIFO_128BYTES 0x00006000 198#define RL_RXFIFO_256BYTES 0x00008000 199#define RL_RXFIFO_512BYTES 0x0000A000 200#define RL_RXFIFO_1024BYTES 0x0000C000 201#define RL_RXFIFO_NOTHRESH 0x0000E000 202 203/* 204 * Bits in RX status header (included with RX'ed packet 205 * in ring buffer). 206 */ 207#define RL_RXSTAT_RXOK 0x00000001 208#define RL_RXSTAT_ALIGNERR 0x00000002 209#define RL_RXSTAT_CRCERR 0x00000004 210#define RL_RXSTAT_GIANT 0x00000008 211#define RL_RXSTAT_RUNT 0x00000010 212#define RL_RXSTAT_BADSYM 0x00000020 213#define RL_RXSTAT_BROAD 0x00002000 214#define RL_RXSTAT_INDIV 0x00004000 215#define RL_RXSTAT_MULTI 0x00008000 216#define RL_RXSTAT_LENMASK 0xFFFF0000 217 218#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 219/* 220 * Command register. 221 */ 222#define RL_CMD_EMPTY_RXBUF 0x0001 223#define RL_CMD_TX_ENB 0x0004 224#define RL_CMD_RX_ENB 0x0008 225#define RL_CMD_RESET 0x0010 226 227/* 228 * EEPROM control register 229 */ 230#define RL_EE_DATAOUT 0x01 /* Data out */ 231#define RL_EE_DATAIN 0x02 /* Data in */ 232#define RL_EE_CLK 0x04 /* clock */ 233#define RL_EE_SEL 0x08 /* chip select */ 234#define RL_EE_MODE (0x40|0x80) 235 236#define RL_EEMODE_OFF 0x00 237#define RL_EEMODE_AUTOLOAD 0x40 238#define RL_EEMODE_PROGRAM 0x80 239#define RL_EEMODE_WRITECFG (0x80|0x40) 240 241/* 9346 EEPROM commands */ 242#define RL_EECMD_WRITE 0x140 243#define RL_EECMD_READ 0x180 244#define RL_EECMD_ERASE 0x1c0 245 246#define RL_EE_ID 0x00 247#define RL_EE_PCI_VID 0x01 248#define RL_EE_PCI_DID 0x02 249/* Location of station address inside EEPROM */ 250#define RL_EE_EADDR 0x07 251 252/* 253 * MII register (8129 only) 254 */ 255#define RL_MII_CLK 0x01 256#define RL_MII_DATAIN 0x02 257#define RL_MII_DATAOUT 0x04 258#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 259 260/* 261 * Config 0 register 262 */ 263#define RL_CFG0_ROM0 0x01 264#define RL_CFG0_ROM1 0x02 265#define RL_CFG0_ROM2 0x04 266#define RL_CFG0_PL0 0x08 267#define RL_CFG0_PL1 0x10 268#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 269#define RL_CFG0_PCS 0x40 270#define RL_CFG0_SCR 0x80 271 272/* 273 * Config 1 register 274 */ 275#define RL_CFG1_PWRDWN 0x01 276#define RL_CFG1_SLEEP 0x02 277#define RL_CFG1_IOMAP 0x04 278#define RL_CFG1_MEMMAP 0x08 279#define RL_CFG1_RSVD 0x10 280#define RL_CFG1_DRVLOAD 0x20 281#define RL_CFG1_LED0 0x40 282#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 283#define RL_CFG1_LED1 0x80 284 285/* 286 * The RealTek doesn't use a fragment-based descriptor mechanism. 287 * Instead, there are only four register sets, each or which represents 288 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 289 * packet buffer (32-bit aligned!) and we place the buffer addresses in 290 * the registers so the chip knows where they are. 291 * 292 * We can sort of kludge together the same kind of buffer management 293 * used in previous drivers, but we have to do buffer copies almost all 294 * the time, so it doesn't really buy us much. 295 * 296 * For reception, there's just one large buffer where the chip stores 297 * all received packets. 298 */ 299 300#define RL_RX_BUF_SZ RL_RXBUF_64 301#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 302#define RL_TX_LIST_CNT 4 303#define RL_MIN_FRAMELEN 60 304#define RL_TXTHRESH(x) ((x) << 11) 305#define RL_TX_THRESH_INIT 96 306#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 307#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 308#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 309 310#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 311#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 312 313#define RL_ETHER_ALIGN 2 314 315struct rl_chain_data { 316 u_int16_t cur_rx; 317 caddr_t rl_rx_buf; 318 caddr_t rl_rx_buf_ptr; 319 320 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 321 u_int8_t last_tx; 322 u_int8_t cur_tx; 323}; 324 325#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 326#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 327#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 328#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 329#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 330#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 331#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 332 333struct rl_type { 334 u_int16_t rl_vid; 335 u_int16_t rl_did; 336}; 337 338struct rl_mii_frame { 339 u_int8_t mii_stdelim; 340 u_int8_t mii_opcode; 341 u_int8_t mii_phyaddr; 342 u_int8_t mii_regaddr; 343 u_int8_t mii_turnaround; 344 u_int16_t mii_data; 345}; 346 347/* 348 * MII constants 349 */ 350#define RL_MII_STARTDELIM 0x01 351#define RL_MII_READOP 0x02 352#define RL_MII_WRITEOP 0x01 353#define RL_MII_TURNAROUND 0x02 354 355#define RL_8129 1 356#define RL_8139 2 357 358struct rl_softc { 359 struct device sc_dev; /* us, as a device */ 360 void * sc_ih; /* interrupt vectoring */ 361 bus_space_handle_t rl_bhandle; /* bus space handle */ 362 bus_space_tag_t rl_btag; /* bus space tag */ 363 bus_dma_tag_t sc_dmat; 364 struct arpcom arpcom; /* interface info */ 365 struct mii_data sc_mii; /* MII information */ 366 u_int8_t rl_type; 367 int rl_txthresh; 368 struct rl_chain_data rl_cdata; 369 struct timeout sc_tick_tmo; 370}; 371 372/* 373 * register space access macros 374 */ 375#define CSR_WRITE_4(sc, csr, val) \ 376 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val) 377#define CSR_WRITE_2(sc, csr, val) \ 378 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val) 379#define CSR_WRITE_1(sc, csr, val) \ 380 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val) 381 382#define CSR_READ_4(sc, csr) \ 383 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, csr) 384#define CSR_READ_2(sc, csr) \ 385 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, csr) 386#define CSR_READ_1(sc, csr) \ 387 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, csr) 388 389#define RL_TIMEOUT 1000 390 391/* 392 * General constants that are fun to know. 393 * 394 * RealTek PCI vendor ID 395 */ 396#define RT_VENDORID 0x10EC 397 398/* 399 * RealTek chip device IDs. 400 */ 401#define RT_DEVICEID_8129 0x8129 402#define RT_DEVICEID_8139 0x8139 403 404/* 405 * Accton PCI vendor ID 406 */ 407#define ACCTON_VENDORID 0x1113 408 409/* 410 * Accton MPX 5030/5038 device ID. 411 */ 412#define ACCTON_DEVICEID_5030 0x1211 413 414/* 415 * Delta Electronics Vendor ID. 416 */ 417#define DELTA_VENDORID 0x1500 418 419/* 420 * Delta device IDs. 421 */ 422#define DELTA_DEVICEID_8139 0x1360 423 424/* 425 * Addtron vendor ID. 426 */ 427#define ADDTRON_VENDORID 0x4033 428 429/* 430 * Addtron device IDs. 431 */ 432#define ADDTRON_DEVICEID_8139 0x1360 433 434/* D-Link Vendor ID */ 435#define DLINK_VENDORID 0x1186 436 437/* D-Link device IDs */ 438#define DLINK_DEVICEID_8139 0x1300 439 440/* 441 * PCI low memory base and low I/O base register, and 442 * other PCI registers. Note: some are only available on 443 * the 3c905B, in particular those that related to power management. 444 */ 445 446#define RL_PCI_VENDOR_ID 0x00 447#define RL_PCI_DEVICE_ID 0x02 448#define RL_PCI_COMMAND 0x04 449#define RL_PCI_STATUS 0x06 450#define RL_PCI_CLASSCODE 0x09 451#define RL_PCI_LATENCY_TIMER 0x0D 452#define RL_PCI_HEADER_TYPE 0x0E 453#define RL_PCI_LOIO 0x10 454#define RL_PCI_LOMEM 0x14 455#define RL_PCI_BIOSROM 0x30 456#define RL_PCI_INTLINE 0x3C 457#define RL_PCI_INTPIN 0x3D 458#define RL_PCI_MINGNT 0x3E 459#define RL_PCI_MINLAT 0x0F 460#define RL_PCI_RESETOPT 0x48 461#define RL_PCI_EEPROM_DATA 0x4C 462 463#define RL_PCI_CAPID 0x50 /* 8 bits */ 464#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 465#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 466#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 467 468#define RL_PSTATE_MASK 0x0003 469#define RL_PSTATE_D0 0x0000 470#define RL_PSTATE_D1 0x0002 471#define RL_PSTATE_D2 0x0002 472#define RL_PSTATE_D3 0x0003 473#define RL_PME_EN 0x0010 474#define RL_PME_STATUS 0x8000 475 476#ifdef __alpha__ 477#undef vtophys 478#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 479#endif 480 481extern int rl_attach(struct rl_softc *); 482extern int rl_intr(void *); 483