rtl81x9reg.h revision 1.101
1/* $OpenBSD: rtl81x9reg.h,v 1.101 2018/04/11 08:02:18 patrick Exp $ */ 2 3/* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.14 1999/10/21 19:42:03 wpaul Exp $ 35 */ 36 37/* 38 * Realtek 8129/8139 register offsets 39 */ 40#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 41#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 42#define RL_IDR2 0x0002 43#define RL_IDR3 0x0003 44#define RL_IDR4 0x0004 45#define RL_IDR5 0x0005 46 /* 0006-0007 reserved */ 47#define RL_MAR0 0x0008 /* Multicast hash table */ 48#define RL_MAR1 0x0009 49#define RL_MAR2 0x000A 50#define RL_MAR3 0x000B 51#define RL_MAR4 0x000C 52#define RL_MAR5 0x000D 53#define RL_MAR6 0x000E 54#define RL_MAR7 0x000F 55 56#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 57#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 58#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 59#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 60 61#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 62#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 63#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 64#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 65 66#define RL_RXADDR 0x0030 /* RX ring start address */ 67#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 68#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 69#define RL_COMMAND 0x0037 /* command register */ 70#define RL_CURRXADDR 0x0038 /* current address of packet read */ 71#define RL_CURRXBUF 0x003A /* current RX buffer address */ 72#define RL_IMR 0x003C /* interrupt mask register */ 73#define RL_ISR 0x003E /* interrupt status register */ 74#define RL_TXCFG 0x0040 /* transmit config */ 75#define RL_RXCFG 0x0044 /* receive config */ 76#define RL_TIMERCNT 0x0048 /* timer count register */ 77#define RL_MISSEDPKT 0x004C /* missed packet counter */ 78#define RL_EECMD 0x0050 /* EEPROM command register */ 79 80/* RTL8139/RTL8139C+ only */ 81#define RL_8139_CFG0 0x0051 /* config register #0 */ 82#define RL_8139_CFG1 0x0052 /* config register #1 */ 83#define RL_8139_CFG3 0x0059 /* config register #3 */ 84#define RL_8139_CFG4 0x005A /* config register #4 */ 85#define RL_8139_CFG5 0x00D8 /* config register #5 */ 86 87#define RL_CFG0 0x0051 /* config register #0 */ 88#define RL_CFG1 0x0052 /* config register #1 */ 89#define RL_CFG2 0x0053 /* config register #2 */ 90#define RL_CFG3 0x0054 /* config register #3 */ 91#define RL_CFG4 0x0055 /* config register #4 */ 92#define RL_CFG5 0x0056 /* config register #5 */ 93 /* 0057 reserved */ 94#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 95 /* 0059-005A reserved */ 96#define RL_MII 0x005A /* 8129 chip only */ 97#define RL_HALTCLK 0x005B 98#define RL_MULTIINTR 0x005C /* multiple interrupt */ 99#define RL_PCIREV 0x005E /* PCI revision value */ 100 /* 005F reserved */ 101#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 102 103#define RL_CSIDR 0x0064 104#define RL_CSIAR 0x0068 105 106/* Direct PHY access registers only available on 8139 */ 107#define RL_BMCR 0x0062 /* PHY basic mode control */ 108#define RL_BMSR 0x0064 /* PHY basic mode status */ 109#define RL_ANAR 0x0066 /* PHY autoneg advert */ 110#define RL_LPAR 0x0068 /* PHY link partner ability */ 111#define RL_ANER 0x006A /* PHY autoneg expansion */ 112 113#define RL_DISCCNT 0x006C /* disconnect counter */ 114#define RL_FALSECAR 0x006E /* false carrier counter */ 115#define RL_NWAYTST 0x0070 /* NWAY test register */ 116#define RL_RX_ER 0x0072 /* RX_ER counter */ 117#define RL_CSCFG 0x0074 /* CS configuration register */ 118 119/* 120 * When operating in special C+ mode, some of the registers in an 121 * 8139C+ chip have different definitions. These are also used for 122 * the 8169 gigE chip. 123 */ 124#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 125#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 126#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 127#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 128#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte aligned */ 129#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte aligned */ 130#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 131#define RL_TXSTART 0x00D9 /* 8 bits */ 132#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 133#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 134#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 135#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 136 137/* 138 * Registers specific to the 8169 gigE chip 139 */ 140#define RL_GTXSTART 0x0038 /* 8 bits */ 141#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 142#define RL_PHYAR 0x0060 143#define RL_TBICSR 0x0064 144#define RL_TBI_ANAR 0x0068 145#define RL_TBI_LPAR 0x006A 146#define RL_GMEDIASTAT 0x006C /* 8 bits */ 147#define RL_MACDBG 0x006D /* 8 bits */ 148#define RL_GPIO 0x006E /* 8 bits */ 149#define RL_PMCH 0x006F /* 8 bits */ 150#define RL_LDPS 0x0082 /* Link Down Power Saving */ 151#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 152#define RL_IM 0x00E2 153#define RL_MISC 0x00F0 154 155/* 156 * Register used on RTL8111E 157 */ 158#define RL_LEDSEL 0x0018 159#define RL_LED_LINK 0x7 /* link at any speed */ 160#define RL_LED_ACT 0x8 161 162/* 163 * TX config register bits 164 */ 165#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 166#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 167#define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */ 168#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 169#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 170#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 171#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 172#define RL_TXCFG_HWREV 0x7C800000 173 174#define RL_LOOPTEST_OFF 0x00000000 175#define RL_LOOPTEST_ON 0x00020000 176#define RL_LOOPTEST_ON_CPLUS 0x00060000 177 178/* Known revision codes. */ 179 180#define RL_HWREV_8169 0x00000000 181#define RL_HWREV_8169S 0x00800000 182#define RL_HWREV_8110S 0x04000000 183#define RL_HWREV_8169_8110SB 0x10000000 184#define RL_HWREV_8169_8110SCd 0x18000000 185#define RL_HWREV_8401E 0x24000000 186#define RL_HWREV_8102EL 0x24800000 187#define RL_HWREV_8102EL_SPIN1 0x24C00000 188#define RL_HWREV_8168D 0x28000000 189#define RL_HWREV_8168DP 0x28800000 190#define RL_HWREV_8168E 0x2C000000 191#define RL_HWREV_8168E_VL 0x2C800000 192#define RL_HWREV_8168B_SPIN1 0x30000000 193#define RL_HWREV_8100E 0x30800000 194#define RL_HWREV_8101E 0x34000000 195#define RL_HWREV_8102E 0x34800000 196#define RL_HWREV_8103E 0x34C00000 197#define RL_HWREV_8168B_SPIN2 0x38000000 198#define RL_HWREV_8168B_SPIN3 0x38400000 199#define RL_HWREV_8100E_SPIN2 0x38800000 200#define RL_HWREV_8168C 0x3c000000 201#define RL_HWREV_8168C_SPIN2 0x3c400000 202#define RL_HWREV_8168CP 0x3c800000 203#define RL_HWREV_8105E 0x40800000 204#define RL_HWREV_8105E_SPIN1 0x40C00000 205#define RL_HWREV_8402 0x44000000 206#define RL_HWREV_8106E 0x44800000 207#define RL_HWREV_8168F 0x48000000 208#define RL_HWREV_8411 0x48800000 209#define RL_HWREV_8168G 0x4c000000 210#define RL_HWREV_8168EP 0x50000000 211#define RL_HWREV_8168GU 0x50800000 212#define RL_HWREV_8168H 0x54000000 213#define RL_HWREV_8411B 0x5c800000 214#define RL_HWREV_8139 0x60000000 215#define RL_HWREV_8139A 0x70000000 216#define RL_HWREV_8139AG 0x70800000 217#define RL_HWREV_8139B 0x78000000 218#define RL_HWREV_8130 0x7C000000 219#define RL_HWREV_8139C 0x74000000 220#define RL_HWREV_8139D 0x74400000 221#define RL_HWREV_8139CPLUS 0x74800000 222#define RL_HWREV_8101 0x74c00000 223#define RL_HWREV_8100 0x78800000 224#define RL_HWREV_8169_8110SBL 0x7cc00000 225#define RL_HWREV_8169_8110SCe 0x98000000 226 227#define RL_TXDMA_16BYTES 0x00000000 228#define RL_TXDMA_32BYTES 0x00000100 229#define RL_TXDMA_64BYTES 0x00000200 230#define RL_TXDMA_128BYTES 0x00000300 231#define RL_TXDMA_256BYTES 0x00000400 232#define RL_TXDMA_512BYTES 0x00000500 233#define RL_TXDMA_1024BYTES 0x00000600 234#define RL_TXDMA_2048BYTES 0x00000700 235 236/* 237 * Transmit descriptor status register bits. 238 */ 239#define RL_TXSTAT_LENMASK 0x00001FFF 240#define RL_TXSTAT_OWN 0x00002000 241#define RL_TXSTAT_TX_UNDERRUN 0x00004000 242#define RL_TXSTAT_TX_OK 0x00008000 243#define RL_TXSTAT_EARLY_THRESH 0x003F0000 244#define RL_TXSTAT_COLLCNT 0x0F000000 245#define RL_TXSTAT_CARR_HBEAT 0x10000000 246#define RL_TXSTAT_OUTOFWIN 0x20000000 247#define RL_TXSTAT_TXABRT 0x40000000 248#define RL_TXSTAT_CARRLOSS 0x80000000 249 250/* 251 * Interrupt status register bits. 252 */ 253#define RL_ISR_RX_OK 0x0001 254#define RL_ISR_RX_ERR 0x0002 255#define RL_ISR_TX_OK 0x0004 256#define RL_ISR_TX_ERR 0x0008 257#define RL_ISR_RX_OVERRUN 0x0010 258#define RL_ISR_PKT_UNDERRUN 0x0020 259#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 260#define RL_ISR_FIFO_OFLOW 0x0040 261#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 262#define RL_ISR_SWI 0x0100 /* C+ only */ 263#define RL_ISR_CABLE_LEN_CHGD 0x2000 264#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 265#define RL_ISR_TIMEOUT_EXPIRED 0x4000 266#define RL_ISR_SYSTEM_ERR 0x8000 267 268#define RL_INTRS \ 269 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 270 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 271 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 272 273#define RL_INTRS_CPLUS \ 274 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 275 RL_ISR_RX_OVERRUN|RL_ISR_FIFO_OFLOW| \ 276 RL_ISR_SYSTEM_ERR|RL_ISR_TX_OK) 277 278#define RL_INTRS_TIMER \ 279 (RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_SYSTEM_ERR| \ 280 RL_ISR_TIMEOUT_EXPIRED) 281 282/* 283 * Media status register. (8139 only) 284 */ 285#define RL_MEDIASTAT_RXPAUSE 0x01 286#define RL_MEDIASTAT_TXPAUSE 0x02 287#define RL_MEDIASTAT_LINK 0x04 288#define RL_MEDIASTAT_SPEED10 0x08 289#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 290#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 291 292/* 293 * Receive config register. 294 */ 295#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 296#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 297#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 298#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 299#define RL_RXCFG_RX_RUNT 0x00000010 300#define RL_RXCFG_RX_ERRPKT 0x00000020 301#define RL_RXCFG_WRAP 0x00000080 302#define RL_RXCFG_EARLYOFFV2 0x00000800 303#define RL_RXCFG_MAXDMA 0x00000700 304#define RL_RXCFG_BURSZ 0x00001800 305#define RL_RXCFG_EARLYOFF 0x00003800 306#define RL_RXCFG_FIFOTHRESH 0x0000E000 307#define RL_RXCFG_EARLYTHRESH 0x07000000 308 309#define RL_RXDMA_16BYTES 0x00000000 310#define RL_RXDMA_32BYTES 0x00000100 311#define RL_RXDMA_64BYTES 0x00000200 312#define RL_RXDMA_128BYTES 0x00000300 313#define RL_RXDMA_256BYTES 0x00000400 314#define RL_RXDMA_512BYTES 0x00000500 315#define RL_RXDMA_1024BYTES 0x00000600 316#define RL_RXDMA_UNLIMITED 0x00000700 317 318#define RL_RXBUF_8 0x00000000 319#define RL_RXBUF_16 0x00000800 320#define RL_RXBUF_32 0x00001000 321#define RL_RXBUF_64 0x00001800 322 323#define RL_RXFIFO_16BYTES 0x00000000 324#define RL_RXFIFO_32BYTES 0x00002000 325#define RL_RXFIFO_64BYTES 0x00004000 326#define RL_RXFIFO_128BYTES 0x00006000 327#define RL_RXFIFO_256BYTES 0x00008000 328#define RL_RXFIFO_512BYTES 0x0000A000 329#define RL_RXFIFO_1024BYTES 0x0000C000 330#define RL_RXFIFO_NOTHRESH 0x0000E000 331 332/* 333 * Bits in RX status header (included with RX'ed packet 334 * in ring buffer). 335 */ 336#define RL_RXSTAT_RXOK 0x00000001 337#define RL_RXSTAT_ALIGNERR 0x00000002 338#define RL_RXSTAT_CRCERR 0x00000004 339#define RL_RXSTAT_GIANT 0x00000008 340#define RL_RXSTAT_RUNT 0x00000010 341#define RL_RXSTAT_BADSYM 0x00000020 342#define RL_RXSTAT_BROAD 0x00002000 343#define RL_RXSTAT_INDIV 0x00004000 344#define RL_RXSTAT_MULTI 0x00008000 345#define RL_RXSTAT_LENMASK 0xFFFF0000 346 347#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 348/* 349 * Command register. 350 */ 351#define RL_CMD_EMPTY_RXBUF 0x0001 352#define RL_CMD_TX_ENB 0x0004 353#define RL_CMD_RX_ENB 0x0008 354#define RL_CMD_RESET 0x0010 355#define RL_CMD_STOPREQ 0x0080 356 357/* 358 * EEPROM control register 359 */ 360#define RL_EE_DATAOUT 0x01 /* Data out */ 361#define RL_EE_DATAIN 0x02 /* Data in */ 362#define RL_EE_CLK 0x04 /* clock */ 363#define RL_EE_SEL 0x08 /* chip select */ 364#define RL_EE_MODE (0x40|0x80) 365 366#define RL_EEMODE_OFF 0x00 367#define RL_EEMODE_AUTOLOAD 0x40 368#define RL_EEMODE_PROGRAM 0x80 369#define RL_EEMODE_WRITECFG (0x80|0x40) 370 371/* 9346/9356 EEPROM commands */ 372 373#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 374#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 375 376#define RL_9346_WRITE 0x5 377#define RL_9346_READ 0x6 378#define RL_9346_ERASE 0x7 379#define RL_9346_EWEN 0x4 380#define RL_9346_EWEN_ADDR 0x30 381#define RL_9456_EWDS 0x4 382#define RL_9346_EWDS_ADDR 0x00 383 384#define RL_EECMD_WRITE 0x5 /* 0101b */ 385#define RL_EECMD_READ 0x6 /* 0110b */ 386#define RL_EECMD_ERASE 0x7 /* 0111b */ 387#define RL_EECMD_LEN 4 388 389#define RL_EEADDR_LEN0 6 /* 9346 */ 390#define RL_EEADDR_LEN1 8 /* 9356 */ 391 392#define RL_EECMD_READ_6BIT 0x180 /* XXX */ 393#define RL_EECMD_READ_8BIT 0x600 /* EECMD_READ above maybe wrong? */ 394 395#define RL_EE_ID 0x00 396#define RL_EE_PCI_VID 0x01 397#define RL_EE_PCI_DID 0x02 398/* Location of station address inside EEPROM */ 399#define RL_EE_EADDR 0x07 400 401/* 402 * MII register (8129 only) 403 */ 404#define RL_MII_CLK 0x01 405#define RL_MII_DATAIN 0x02 406#define RL_MII_DATAOUT 0x04 407#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 408 409/* 410 * Config 0 register 411 */ 412#define RL_CFG0_ROM0 0x01 413#define RL_CFG0_ROM1 0x02 414#define RL_CFG0_ROM2 0x04 415#define RL_CFG0_PL0 0x08 416#define RL_CFG0_PL1 0x10 417#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 418#define RL_CFG0_PCS 0x40 419#define RL_CFG0_SCR 0x80 420 421/* 422 * Config 1 register 423 */ 424#define RL_CFG1_PWRDWN 0x01 425#define RL_CFG1_PME 0x01 426#define RL_CFG1_SLEEP 0x02 427#define RL_CFG1_VPDEN 0x02 428#define RL_CFG1_IOMAP 0x04 429#define RL_CFG1_MEMMAP 0x08 430#define RL_CFG1_RSVD 0x10 431#define RL_CFG1_LWACT 0x10 432#define RL_CFG1_DRVLOAD 0x20 433#define RL_CFG1_LED0 0x40 434#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 435#define RL_CFG1_LED1 0x80 436 437/* 438 * Config 2 register 439 */ 440#define RL_CFG2_PCI_MASK 0x07 441#define RL_CFG2_PCI_33MHZ 0x00 442#define RL_CFG2_PCI_66MHZ 0x01 443#define RL_CFG2_PCI_64BIT 0x08 444#define RL_CFG2_AUXPWR 0x10 445#define RL_CFG2_MSI 0x20 446 447/* 448 * Config 3 register 449 */ 450#define RL_CFG3_GRANTSEL 0x80 451#define RL_CFG3_WOL_MAGIC 0x20 452#define RL_CFG3_WOL_LINK 0x10 453#define RL_CFG3_JUMBO_EN0 0x04 454#define RL_CFG3_FAST_B2B 0x01 455 456/* 457 * Config 4 register 458 */ 459#define RL_CFG4_CUSTOM_LED 0x40 460#define RL_CFG4_LWPTN 0x04 461#define RL_CFG4_LWPME 0x10 462#define RL_CFG4_JUMBO_EN1 0x02 463#define RL_CFG4_8168E_JUMBO_EN1 0x01 464 465/* 466 * Config 5 register 467 */ 468#define RL_CFG5_WOL_BCAST 0x40 469#define RL_CFG5_WOL_MCAST 0x20 470#define RL_CFG5_WOL_UCAST 0x10 471#define RL_CFG5_WOL_LANWAKE 0x02 472#define RL_CFG5_PME_STS 0x01 473 474/* 475 * 8139C+ register definitions 476 */ 477 478/* RL_DUMPSTATS_LO register */ 479 480#define RL_DUMPSTATS_START 0x00000008 481 482/* Transmit start register */ 483 484#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 485#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 486#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 487 488/* 489 * Config 2 register, 8139C+/8169/8169S/8110S only 490 */ 491#define RL_CFG2_BUSFREQ 0x07 492#define RL_CFG2_BUSWIDTH 0x08 493#define RL_CFG2_AUXPWRSTS 0x10 494 495#define RL_BUSFREQ_33MHZ 0x00 496#define RL_BUSFREQ_66MHZ 0x01 497 498#define RL_BUSWIDTH_32BITS 0x00 499#define RL_BUSWIDTH_64BITS 0x08 500 501/* C+ mode command register */ 502 503#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 504#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 505#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 506#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 507#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 508#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 509#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 510#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 511#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 512#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 513#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 514#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 515#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 516#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 517#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 518 519/* C+ early transmit threshold */ 520 521#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 522 523/* 524 * Gigabit PHY access register (8169 only) 525 */ 526 527#define RL_PHYAR_PHYDATA 0x0000FFFF 528#define RL_PHYAR_PHYREG 0x001F0000 529#define RL_PHYAR_BUSY 0x80000000 530 531/* 532 * Gigabit media status (8169 only) 533 */ 534#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 535#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 536#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 537#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 538#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 539#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 540#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 541#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 542 543/* 544 * The Realtek doesn't use a fragment-based descriptor mechanism. 545 * Instead, there are only four register sets, each of which represents 546 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 547 * packet buffer (32-bit aligned!) and we place the buffer addresses in 548 * the registers so the chip knows where they are. 549 * 550 * We can sort of kludge together the same kind of buffer management 551 * used in previous drivers, but we have to do buffer copies almost all 552 * the time, so it doesn't really buy us much. 553 * 554 * For reception, there's just one large buffer where the chip stores 555 * all received packets. 556 */ 557 558#define RL_RX_BUF_SZ RL_RXBUF_64 559#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 560#define RL_TX_LIST_CNT 4 561#define RL_MIN_FRAMELEN 60 562#define RL_TXTHRESH(x) ((x) << 11) 563#define RL_TX_THRESH_INIT 96 564#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 565#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 566#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 567 568#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 569#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 570 571#define RL_IM_MAGIC 0x5050 572#define RL_IM_RXTIME(t) ((t) & 0xf) 573#define RL_IM_TXTIME(t) (((t) & 0xf) << 8) 574 575struct rl_chain_data { 576 u_int16_t cur_rx; 577 caddr_t rl_rx_buf; 578 caddr_t rl_rx_buf_ptr; 579 bus_addr_t rl_rx_buf_pa; 580 581 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 582 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 583 u_int8_t last_tx; 584 u_int8_t cur_tx; 585}; 586 587 588/* 589 * The 8139C+ and 8160 gigE chips support descriptor-based TX 590 * and RX. In fact, they even support TCP large send. Descriptors 591 * must be allocated in contiguous blocks that are aligned on a 592 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 593 */ 594 595/* 596 * RX/TX descriptor definition. When large send mode is enabled, the 597 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 598 * the checksum offload bits are disabled. The structure layout is 599 * the same for RX and TX descriptors 600 */ 601 602struct rl_desc { 603 volatile u_int32_t rl_cmdstat; 604 volatile u_int32_t rl_vlanctl; 605 volatile u_int32_t rl_bufaddr_lo; 606 volatile u_int32_t rl_bufaddr_hi; 607}; 608 609#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 610#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 611#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 612#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 613#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 614#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 615#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 616#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 617#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 618#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 619 620#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 621#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 622/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 623#define RL_TDESC_CMD_IPCSUMV2 0x20000000 624#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 625#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 626 627/* 628 * Error bits are valid only on the last descriptor of a frame 629 * (i.e. RL_TDESC_CMD_EOF == 1) 630 */ 631 632#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 633#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 634#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 635#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 636#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 637#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 638#define RL_TDESC_STAT_OWN 0x80000000 639 640/* 641 * RX descriptor cmd/vlan definitions 642 */ 643 644#define RL_RDESC_CMD_EOR 0x40000000 645#define RL_RDESC_CMD_OWN 0x80000000 646#define RL_RDESC_CMD_BUFLEN 0x00001FFF 647 648#define RL_RDESC_STAT_OWN 0x80000000 649#define RL_RDESC_STAT_EOR 0x40000000 650#define RL_RDESC_STAT_SOF 0x20000000 651#define RL_RDESC_STAT_EOF 0x10000000 652#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 653#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 654#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 655#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 656#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 657#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 658#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 659#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 660#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 661#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 662#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 663#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 664#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 665#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 666#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 667#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 668#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 669#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 670#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 671 RL_RDESC_STAT_CRCERR) 672 673#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 674 (rl_vlandata valid)*/ 675#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 676/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 677#define RL_RDESC_IPV6 0x80000000 678#define RL_RDESC_IPV4 0x40000000 679 680#define RL_PROTOID_NONIP 0x00000000 681#define RL_PROTOID_TCPIP 0x00010000 682#define RL_PROTOID_UDPIP 0x00020000 683#define RL_PROTOID_IP 0x00030000 684#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 685 RL_PROTOID_TCPIP) 686#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 687 RL_PROTOID_UDPIP) 688 689/* 690 * Statistics counter structure (8139C+ and 8169 only) 691 */ 692struct rl_stats { 693 u_int32_t rl_tx_pkts_lo; 694 u_int32_t rl_tx_pkts_hi; 695 u_int32_t rl_tx_errs_lo; 696 u_int32_t rl_tx_errs_hi; 697 u_int32_t rl_tx_errs; 698 u_int16_t rl_missed_pkts; 699 u_int16_t rl_rx_framealign_errs; 700 u_int32_t rl_tx_onecoll; 701 u_int32_t rl_tx_multicolls; 702 u_int32_t rl_rx_ucasts_hi; 703 u_int32_t rl_rx_ucasts_lo; 704 u_int32_t rl_rx_bcasts_lo; 705 u_int32_t rl_rx_bcasts_hi; 706 u_int32_t rl_rx_mcasts; 707 u_int16_t rl_tx_aborts; 708 u_int16_t rl_rx_underruns; 709}; 710 711/* 712 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 713 * 714 * 8139C+ 715 * Number of descriptors supported : up to 64 716 * Descriptor alignment : 256 bytes 717 * Tx buffer : At least 4 bytes in length. 718 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 719 * 720 * 8169 721 * Number of descriptors supported : up to 1024 722 * Descriptor alignment : 256 bytes 723 * Tx buffer : At least 4 bytes in length. 724 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 725 */ 726#define RL_8169_TX_DESC_CNT 1024 727#define RL_8169_RX_DESC_CNT 1024 728#define RL_8139_TX_DESC_CNT 64 729#define RL_8139_RX_DESC_CNT 64 730#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 731#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 732#define RL_8169_NTXSEGS 32 733#define RL_8139_NTXSEGS 8 734 735#define RL_TX_QLEN 64 736 737#define RL_RING_ALIGN 256 738#define RL_PKTSZ(x) ((x)/* >> 3*/) 739#ifdef __STRICT_ALIGNMENT 740#define RE_ETHER_ALIGN 2 741#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 742#else 743#define RE_ETHER_ALIGN 0 744#define RE_RX_DESC_BUFLEN MCLBYTES 745#endif 746 747#define RL_TX_LIST_SZ(sc) \ 748 ((sc)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)) 749#define RL_RX_LIST_SZ(sc) \ 750 ((sc)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)) 751#define RL_NEXT_TX_DESC(sc, x) \ 752 (((x) + 1) % (sc)->rl_ldata.rl_tx_desc_cnt) 753#define RL_NEXT_RX_DESC(sc, x) \ 754 (((x) + 1) % (sc)->rl_ldata.rl_rx_desc_cnt) 755#define RL_NEXT_TXQ(sc, x) \ 756 (((x) + 1) % RL_TX_QLEN) 757 758#define RL_TXDESCSYNC(sc, idx, ops) \ 759 bus_dmamap_sync((sc)->sc_dmat, \ 760 (sc)->rl_ldata.rl_tx_list_map, \ 761 sizeof(struct rl_desc) * (idx), \ 762 sizeof(struct rl_desc), \ 763 (ops)) 764#define RL_RXDESCSYNC(sc, idx, ops) \ 765 bus_dmamap_sync((sc)->sc_dmat, \ 766 (sc)->rl_ldata.rl_rx_list_map, \ 767 sizeof(struct rl_desc) * (idx), \ 768 sizeof(struct rl_desc), \ 769 (ops)) 770 771#define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) 772#define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32) 773 774#define RL_JUMBO_FRAMELEN (9 * 1024) 775#define RL_JUMBO_MTU_4K \ 776 ((4 * 1024) - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 777#define RL_JUMBO_MTU_6K \ 778 ((6 * 1024) - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 779#define RL_JUMBO_MTU_7K \ 780 ((7 * 1024) - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 781#define RL_JUMBO_MTU_9K \ 782 ((9 * 1024) - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 783#define RL_MTU ETHERMTU 784 785#define MAX_NUM_MULTICAST_ADDRESSES 128 786 787#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 788#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 789#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 790#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 791#define RL_CUR_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 792#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 793#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 794#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 795#define RL_LAST_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 796 797struct rl_type { 798 u_int16_t rl_vid; 799 u_int16_t rl_did; 800}; 801 802struct rl_mii_frame { 803 u_int8_t mii_stdelim; 804 u_int8_t mii_opcode; 805 u_int8_t mii_phyaddr; 806 u_int8_t mii_regaddr; 807 u_int8_t mii_turnaround; 808 u_int16_t mii_data; 809}; 810 811/* 812 * MII constants 813 */ 814#define RL_MII_STARTDELIM 0x01 815#define RL_MII_READOP 0x02 816#define RL_MII_WRITEOP 0x01 817#define RL_MII_TURNAROUND 0x02 818 819#define RL_UNKNOWN 0 820#define RL_8129 1 821#define RL_8139 2 822 823struct rl_rxsoft { 824 struct mbuf *rxs_mbuf; 825 bus_dmamap_t rxs_dmamap; 826}; 827 828struct rl_txq { 829 struct mbuf *txq_mbuf; 830 bus_dmamap_t txq_dmamap; 831 int txq_descidx; 832 int txq_nsegs; 833}; 834 835struct rl_list_data { 836 struct rl_txq rl_txq[RL_TX_DESC_CNT]; 837 int rl_txq_considx; 838 int rl_txq_prodidx; 839 840 bus_dmamap_t rl_tx_list_map; 841 struct rl_desc *rl_tx_list; 842 int rl_tx_free; /* # of free descriptors */ 843 int rl_tx_nextfree; /* next descriptor to use */ 844 int rl_tx_desc_cnt; /* # of descriptors */ 845 int rl_tx_ndescs; /* descs per tx packet */ 846 bus_dma_segment_t rl_tx_listseg; 847 int rl_tx_listnseg; 848 849 struct rl_rxsoft rl_rxsoft[RL_RX_DESC_CNT]; 850 bus_dmamap_t rl_rx_list_map; 851 struct rl_desc *rl_rx_list; 852 int rl_rx_considx; 853 int rl_rx_prodidx; 854 int rl_rx_desc_cnt; /* # of descriptors */ 855 struct if_rxring rl_rx_ring; 856 bus_dma_segment_t rl_rx_listseg; 857 int rl_rx_listnseg; 858}; 859 860struct rl_softc { 861 struct device sc_dev; /* us, as a device */ 862 void * sc_ih; /* interrupt vectoring */ 863 bus_space_handle_t rl_bhandle; /* bus space handle */ 864 bus_space_tag_t rl_btag; /* bus space tag */ 865 bus_dma_tag_t sc_dmat; 866 bus_dma_segment_t sc_rx_seg; 867 bus_dmamap_t sc_rx_dmamap; 868 struct arpcom sc_arpcom; /* interface info */ 869 struct mii_data sc_mii; /* MII information */ 870 u_int8_t rl_type; 871 u_int32_t sc_hwrev; 872 u_int16_t sc_product; 873 int rl_max_mtu; 874 int rl_eecmd_read; 875 int rl_eewidth; 876 int rl_bus_speed; 877 int rl_txthresh; 878 bus_size_t rl_cfg0; 879 bus_size_t rl_cfg1; 880 bus_size_t rl_cfg2; 881 bus_size_t rl_cfg3; 882 bus_size_t rl_cfg4; 883 bus_size_t rl_cfg5; 884 struct rl_chain_data rl_cdata; 885 struct timeout sc_tick_tmo; 886 887 struct rl_list_data rl_ldata; 888 struct mbuf *rl_head; 889 struct mbuf *rl_tail; 890 u_int32_t rl_rxlenmask; 891 struct timeout timer_handle; 892 struct task rl_start; 893 894 int rl_txstart; 895 u_int32_t rl_flags; 896#define RL_FLAG_MSI 0x00000001 897#define RL_FLAG_PCI64 0x00000002 898#define RL_FLAG_PCIE 0x00000004 899#define RL_FLAG_PHYWAKE 0x00000008 900#define RL_FLAG_PAR 0x00000010 901#define RL_FLAG_DESCV2 0x00000020 902#define RL_FLAG_MACSTAT 0x00000040 903#define RL_FLAG_HWIM 0x00000080 904#define RL_FLAG_TIMERINTR 0x00000100 905#define RL_FLAG_MACRESET 0x00000200 906#define RL_FLAG_CMDSTOP 0x00000400 907#define RL_FLAG_MACSLEEP 0x00000800 908#define RL_FLAG_AUTOPAD 0x00001000 909#define RL_FLAG_LINK 0x00002000 910#define RL_FLAG_PHYWAKE_PM 0x00004000 911#define RL_FLAG_EARLYOFF 0x00008000 912#define RL_FLAG_EARLYOFFV2 0x00010000 913#define RL_FLAG_RXDV_GATED 0x00020000 914#define RL_FLAG_FASTETHER 0x00040000 915#define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00080000 916#define RL_FLAG_JUMBOV2 0x00100000 917#define RL_FLAG_WOL_MANLINK 0x00200000 918#define RL_FLAG_WAIT_TXPOLL 0x00400000 919#define RL_FLAG_WOLRXENB 0x00800000 920 921 u_int16_t rl_intrs; 922 u_int16_t rl_tx_ack; 923 u_int16_t rl_rx_ack; 924 int rl_tx_time; 925 int rl_rx_time; 926 int rl_sim_time; 927 int rl_imtype; 928#define RL_IMTYPE_NONE 0 929#define RL_IMTYPE_SIM 1 /* simulated */ 930#define RL_IMTYPE_HW 2 /* hardware based */ 931 int rl_timerintr; 932}; 933 934/* 935 * re(4) hardware ip4csum-tx could be mangled with 28 byte or less IP packets 936 */ 937#define RL_IP4CSUMTX_MINLEN 28 938#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 939/* 940 * XXX 941 * We are allocating pad DMA buffer after RX DMA descs for now 942 * because RL_TX_LIST_SZ(sc) always occupies whole page but 943 * RL_RX_LIST_SZ is less than PAGE_SIZE so there is some unused region. 944 */ 945#define RL_RX_DMAMEM_SZ(sc) (RL_RX_LIST_SZ(sc) + RL_IP4CSUMTX_PADLEN) 946#define RL_TXPADOFF(sc) RL_RX_LIST_SZ(sc) 947#define RL_TXPADDADDR(sc) \ 948 ((sc)->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr + RL_TXPADOFF(sc)) 949 950/* 951 * register space access macros 952 */ 953#define CSR_WRITE_RAW_4(sc, csr, val) \ 954 bus_space_write_raw_region_4(sc->rl_btag, sc->rl_bhandle, csr, val, 4) 955#define CSR_WRITE_4(sc, csr, val) \ 956 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val) 957#define CSR_WRITE_2(sc, csr, val) \ 958 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val) 959#define CSR_WRITE_1(sc, csr, val) \ 960 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val) 961 962#define CSR_READ_4(sc, csr) \ 963 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, csr) 964#define CSR_READ_2(sc, csr) \ 965 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, csr) 966#define CSR_READ_1(sc, csr) \ 967 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, csr) 968 969#define CSR_SETBIT_1(sc, offset, val) \ 970 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 971 972#define CSR_CLRBIT_1(sc, offset, val) \ 973 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 974 975#define CSR_SETBIT_2(sc, offset, val) \ 976 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 977 978#define CSR_CLRBIT_2(sc, offset, val) \ 979 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 980 981#define CSR_SETBIT_4(sc, offset, val) \ 982 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 983 984#define CSR_CLRBIT_4(sc, offset, val) \ 985 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 986 987#define RL_TIMEOUT 1000 988#define RL_PHY_TIMEOUT 20 989 990/* 991 * General constants that are fun to know. 992 * 993 * Realtek PCI vendor ID 994 */ 995#define RT_VENDORID 0x10EC 996 997/* 998 * Realtek chip device IDs. 999 */ 1000#define RT_DEVICEID_8129 0x8129 1001#define RT_DEVICEID_8101E 0x8136 1002#define RT_DEVICEID_8138 0x8138 1003#define RT_DEVICEID_8139 0x8139 1004#define RT_DEVICEID_8169SC 0x8167 1005#define RT_DEVICEID_8168 0x8168 1006#define RT_DEVICEID_8169 0x8169 1007#define RT_DEVICEID_8100 0x8100 1008 1009/* 1010 * Accton PCI vendor ID 1011 */ 1012#define ACCTON_VENDORID 0x1113 1013 1014/* 1015 * Accton MPX 5030/5038 device ID. 1016 */ 1017#define ACCTON_DEVICEID_5030 0x1211 1018 1019/* 1020 * Delta Electronics Vendor ID. 1021 */ 1022#define DELTA_VENDORID 0x1500 1023 1024/* 1025 * Delta device IDs. 1026 */ 1027#define DELTA_DEVICEID_8139 0x1360 1028 1029/* 1030 * Addtron vendor ID. 1031 */ 1032#define ADDTRON_VENDORID 0x4033 1033 1034/* 1035 * Addtron device IDs. 1036 */ 1037#define ADDTRON_DEVICEID_8139 0x1360 1038 1039/* D-Link Vendor ID */ 1040#define DLINK_VENDORID 0x1186 1041 1042/* D-Link device IDs */ 1043#define DLINK_DEVICEID_8139 0x1300 1044#define DLINK_DEVICEID_8139_2 0x1340 1045 1046/* Abocom device IDs */ 1047#define ABOCOM_DEVICEID_8139 0xab06 1048 1049/* 1050 * PCI low memory base and low I/O base register, and 1051 * other PCI registers. Note: some are only available on 1052 * the 3c905B, in particular those that related to power management. 1053 */ 1054 1055#define RL_PCI_VENDOR_ID 0x00 1056#define RL_PCI_DEVICE_ID 0x02 1057#define RL_PCI_COMMAND 0x04 1058#define RL_PCI_STATUS 0x06 1059#define RL_PCI_CLASSCODE 0x09 1060#define RL_PCI_LATENCY_TIMER 0x0D 1061#define RL_PCI_HEADER_TYPE 0x0E 1062#define RL_PCI_LOIO 0x10 1063#define RL_PCI_LOMEM 0x14 1064#define RL_PCI_LOMEM64 0x18 1065#define RL_PCI_BIOSROM 0x30 1066#define RL_PCI_INTLINE 0x3C 1067#define RL_PCI_INTPIN 0x3D 1068#define RL_PCI_MINGNT 0x3E 1069#define RL_PCI_MINLAT 0x0F 1070#define RL_PCI_PMCSR 0x44 1071#define RL_PCI_RESETOPT 0x48 1072#define RL_PCI_EEPROM_DATA 0x4C 1073 1074#define RL_PCI_CAPID 0x50 /* 8 bits */ 1075#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 1076#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 1077#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 1078 1079#define RL_PSTATE_MASK 0x0003 1080#define RL_PSTATE_D0 0x0000 1081#define RL_PSTATE_D1 0x0001 1082#define RL_PSTATE_D2 0x0002 1083#define RL_PSTATE_D3 0x0003 1084#define RL_PME_EN 0x0100 1085#define RL_PME_STATUS 0x8000 1086 1087extern int rl_attach(struct rl_softc *); 1088extern int rl_intr(void *); 1089extern void rl_setmulti(struct rl_softc *); 1090int rl_detach(struct rl_softc *); 1091int rl_activate(struct device *, int); 1092