rt2560.c revision 1.5
1/* $OpenBSD: rt2560.c,v 1.5 2006/01/10 21:20:46 damien Exp $ */ 2 3/*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20/*- 21 * Ralink Technology RT2560 chipset driver 22 * http://www.ralinktech.com/ 23 */ 24 25#include "bpfilter.h" 26 27#include <sys/param.h> 28#include <sys/sockio.h> 29#include <sys/sysctl.h> 30#include <sys/mbuf.h> 31#include <sys/kernel.h> 32#include <sys/socket.h> 33#include <sys/systm.h> 34#include <sys/malloc.h> 35#include <sys/timeout.h> 36#include <sys/conf.h> 37#include <sys/device.h> 38 39#include <machine/bus.h> 40#include <machine/endian.h> 41#include <machine/intr.h> 42 43#if NBPFILTER > 0 44#include <net/bpf.h> 45#endif 46#include <net/if.h> 47#include <net/if_arp.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50#include <net/if_types.h> 51 52#include <netinet/in.h> 53#include <netinet/in_systm.h> 54#include <netinet/in_var.h> 55#include <netinet/if_ether.h> 56#include <netinet/ip.h> 57 58#include <net80211/ieee80211_var.h> 59#include <net80211/ieee80211_rssadapt.h> 60#include <net80211/ieee80211_radiotap.h> 61 62#include <dev/ic/rt2560reg.h> 63#include <dev/ic/rt2560var.h> 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67#include <dev/pci/pcidevs.h> 68 69#ifdef RAL_DEBUG 70#define DPRINTF(x) do { if (rt2560_debug > 0) printf x; } while (0) 71#define DPRINTFN(n, x) do { if (rt2560_debug >= (n)) printf x; } while (0) 72int rt2560_debug = 0; 73#else 74#define DPRINTF(x) 75#define DPRINTFN(n, x) 76#endif 77 78int rt2560_alloc_tx_ring(struct rt2560_softc *, 79 struct rt2560_tx_ring *, int); 80void rt2560_reset_tx_ring(struct rt2560_softc *, 81 struct rt2560_tx_ring *); 82void rt2560_free_tx_ring(struct rt2560_softc *, 83 struct rt2560_tx_ring *); 84int rt2560_alloc_rx_ring(struct rt2560_softc *, 85 struct rt2560_rx_ring *, int); 86void rt2560_reset_rx_ring(struct rt2560_softc *, 87 struct rt2560_rx_ring *); 88void rt2560_free_rx_ring(struct rt2560_softc *, 89 struct rt2560_rx_ring *); 90struct ieee80211_node *rt2560_node_alloc(struct ieee80211com *); 91void rt2560_node_copy(struct ieee80211com *ic, 92 struct ieee80211_node *, const struct ieee80211_node *); 93int rt2560_media_change(struct ifnet *); 94void rt2560_next_scan(void *); 95void rt2560_iter_func(void *, struct ieee80211_node *); 96void rt2560_rssadapt_updatestats(void *); 97int rt2560_newstate(struct ieee80211com *, enum ieee80211_state, 98 int); 99uint16_t rt2560_eeprom_read(struct rt2560_softc *, uint8_t); 100void rt2560_encryption_intr(struct rt2560_softc *); 101void rt2560_tx_intr(struct rt2560_softc *); 102void rt2560_prio_intr(struct rt2560_softc *); 103void rt2560_decryption_intr(struct rt2560_softc *); 104void rt2560_rx_intr(struct rt2560_softc *); 105void rt2560_beacon_expire(struct rt2560_softc *); 106void rt2560_wakeup_expire(struct rt2560_softc *); 107int rt2560_ack_rate(struct ieee80211com *, int); 108uint16_t rt2560_txtime(int, int, uint32_t); 109uint8_t rt2560_plcp_signal(int); 110void rt2560_setup_tx_desc(struct rt2560_softc *, 111 struct rt2560_tx_desc *, uint32_t, int, int, int, 112 bus_addr_t); 113int rt2560_tx_bcn(struct rt2560_softc *, struct mbuf *, 114 struct ieee80211_node *); 115int rt2560_tx_mgt(struct rt2560_softc *, struct mbuf *, 116 struct ieee80211_node *); 117struct mbuf *rt2560_get_rts(struct rt2560_softc *, 118 struct ieee80211_frame *, uint16_t); 119int rt2560_tx_data(struct rt2560_softc *, struct mbuf *, 120 struct ieee80211_node *); 121void rt2560_start(struct ifnet *); 122void rt2560_watchdog(struct ifnet *); 123int rt2560_ioctl(struct ifnet *, u_long, caddr_t); 124void rt2560_bbp_write(struct rt2560_softc *, uint8_t, uint8_t); 125uint8_t rt2560_bbp_read(struct rt2560_softc *, uint8_t); 126void rt2560_rf_write(struct rt2560_softc *, uint8_t, uint32_t); 127void rt2560_set_chan(struct rt2560_softc *, 128 struct ieee80211_channel *); 129void rt2560_disable_rf_tune(struct rt2560_softc *); 130void rt2560_enable_tsf_sync(struct rt2560_softc *); 131void rt2560_update_plcp(struct rt2560_softc *); 132void rt2560_update_slot(struct rt2560_softc *); 133void rt2560_update_led(struct rt2560_softc *, int, int); 134void rt2560_set_bssid(struct rt2560_softc *, uint8_t *); 135void rt2560_set_macaddr(struct rt2560_softc *, uint8_t *); 136void rt2560_get_macaddr(struct rt2560_softc *, uint8_t *); 137void rt2560_update_promisc(struct rt2560_softc *); 138void rt2560_set_txantenna(struct rt2560_softc *, int); 139void rt2560_set_rxantenna(struct rt2560_softc *, int); 140const char *rt2560_get_rf(int); 141void rt2560_read_eeprom(struct rt2560_softc *); 142int rt2560_bbp_init(struct rt2560_softc *); 143int rt2560_init(struct ifnet *); 144void rt2560_stop(struct ifnet *, int); 145 146/* 147 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 148 */ 149static const struct ieee80211_rateset rt2560_rateset_11a = 150 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 151 152static const struct ieee80211_rateset rt2560_rateset_11b = 153 { 4, { 2, 4, 11, 22 } }; 154 155static const struct ieee80211_rateset rt2560_rateset_11g = 156 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 157 158/* 159 * Default values for MAC registers; values taken from the reference driver. 160 */ 161static const struct { 162 uint32_t reg; 163 uint32_t val; 164} rt2560_def_mac[] = { 165 { RT2560_PSCSR0, 0x00020002 }, 166 { RT2560_PSCSR1, 0x00000002 }, 167 { RT2560_PSCSR2, 0x00020002 }, 168 { RT2560_PSCSR3, 0x00000002 }, 169 { RT2560_TIMECSR, 0x00003f21 }, 170 { RT2560_CSR9, 0x00000780 }, 171 { RT2560_CSR11, 0x07041483 }, 172 { RT2560_CNT3, 0x00000000 }, 173 { RT2560_TXCSR1, 0x07614562 }, 174 { RT2560_ARSP_PLCP_0, 0x8c8d8b8a }, 175 { RT2560_ACKPCTCSR, 0x7038140a }, 176 { RT2560_ARTCSR1, 0x1d21252d }, 177 { RT2560_ARTCSR2, 0x1919191d }, 178 { RT2560_RXCSR0, 0xffffffff }, 179 { RT2560_RXCSR3, 0xb3aab3af }, 180 { RT2560_PCICSR, 0x000003b8 }, 181 { RT2560_PWRCSR0, 0x3f3b3100 }, 182 { RT2560_GPIOCSR, 0x0000ff00 }, 183 { RT2560_TESTCSR, 0x000000f0 }, 184 { RT2560_PWRCSR1, 0x000001ff }, 185 { RT2560_MACCSR0, 0x00213223 }, 186 { RT2560_MACCSR1, 0x00235518 }, 187 { RT2560_RLPWCSR, 0x00000040 }, 188 { RT2560_RALINKCSR, 0x9a009a11 }, 189 { RT2560_CSR7, 0xffffffff }, 190 { RT2560_BBPCSR1, 0x82188200 }, 191 { RT2560_TXACKCSR0, 0x00000020 }, 192 { RT2560_SECCSR3, 0x0000e78f } 193}; 194 195/* 196 * Default values for BBP registers; values taken from the reference driver. 197 */ 198static const struct { 199 uint8_t reg; 200 uint8_t val; 201} rt2560_def_bbp[] = { 202 { 3, 0x02 }, 203 { 4, 0x19 }, 204 { 14, 0x1c }, 205 { 15, 0x30 }, 206 { 16, 0xac }, 207 { 17, 0x48 }, 208 { 18, 0x18 }, 209 { 19, 0xff }, 210 { 20, 0x1e }, 211 { 21, 0x08 }, 212 { 22, 0x08 }, 213 { 23, 0x08 }, 214 { 24, 0x80 }, 215 { 25, 0x50 }, 216 { 26, 0x08 }, 217 { 27, 0x23 }, 218 { 30, 0x10 }, 219 { 31, 0x2b }, 220 { 32, 0xb9 }, 221 { 34, 0x12 }, 222 { 35, 0x50 }, 223 { 39, 0xc4 }, 224 { 40, 0x02 }, 225 { 41, 0x60 }, 226 { 53, 0x10 }, 227 { 54, 0x18 }, 228 { 56, 0x08 }, 229 { 57, 0x10 }, 230 { 58, 0x08 }, 231 { 61, 0x60 }, 232 { 62, 0x10 }, 233 { 75, 0xff } 234}; 235 236/* 237 * Default values for RF register R2 indexed by channel numbers; values taken 238 * from the reference driver. 239 */ 240static const uint32_t rt2560_rf2522_r2[] = { 241 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 242 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 243}; 244 245static const uint32_t rt2560_rf2523_r2[] = { 246 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 247 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 248}; 249 250static const uint32_t rt2560_rf2524_r2[] = { 251 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 252 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 253}; 254 255static const uint32_t rt2560_rf2525_r2[] = { 256 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 257 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 258}; 259 260static const uint32_t rt2560_rf2525_hi_r2[] = { 261 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 262 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 263}; 264 265static const uint32_t rt2560_rf2525e_r2[] = { 266 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 267 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 268}; 269 270static const uint32_t rt2560_rf2526_hi_r2[] = { 271 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 272 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 273}; 274 275static const uint32_t rt2560_rf2526_r2[] = { 276 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 277 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 278}; 279 280/* 281 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 282 * values taken from the reference driver. 283 */ 284static const struct { 285 uint8_t chan; 286 uint32_t r1; 287 uint32_t r2; 288 uint32_t r4; 289} rt2560_rf5222[] = { 290 /* channels in the 2.4GHz band */ 291 { 1, 0x08808, 0x0044d, 0x00282 }, 292 { 2, 0x08808, 0x0044e, 0x00282 }, 293 { 3, 0x08808, 0x0044f, 0x00282 }, 294 { 4, 0x08808, 0x00460, 0x00282 }, 295 { 5, 0x08808, 0x00461, 0x00282 }, 296 { 6, 0x08808, 0x00462, 0x00282 }, 297 { 7, 0x08808, 0x00463, 0x00282 }, 298 { 8, 0x08808, 0x00464, 0x00282 }, 299 { 9, 0x08808, 0x00465, 0x00282 }, 300 { 10, 0x08808, 0x00466, 0x00282 }, 301 { 11, 0x08808, 0x00467, 0x00282 }, 302 { 12, 0x08808, 0x00468, 0x00282 }, 303 { 13, 0x08808, 0x00469, 0x00282 }, 304 { 14, 0x08808, 0x0046b, 0x00286 }, 305 306 /* channels in the 5.2GHz band */ 307 { 36, 0x08804, 0x06225, 0x00287 }, 308 { 40, 0x08804, 0x06226, 0x00287 }, 309 { 44, 0x08804, 0x06227, 0x00287 }, 310 { 48, 0x08804, 0x06228, 0x00287 }, 311 { 52, 0x08804, 0x06229, 0x00287 }, 312 { 56, 0x08804, 0x0622a, 0x00287 }, 313 { 60, 0x08804, 0x0622b, 0x00287 }, 314 { 64, 0x08804, 0x0622c, 0x00287 }, 315 316 { 100, 0x08804, 0x02200, 0x00283 }, 317 { 104, 0x08804, 0x02201, 0x00283 }, 318 { 108, 0x08804, 0x02202, 0x00283 }, 319 { 112, 0x08804, 0x02203, 0x00283 }, 320 { 116, 0x08804, 0x02204, 0x00283 }, 321 { 120, 0x08804, 0x02205, 0x00283 }, 322 { 124, 0x08804, 0x02206, 0x00283 }, 323 { 128, 0x08804, 0x02207, 0x00283 }, 324 { 132, 0x08804, 0x02208, 0x00283 }, 325 { 136, 0x08804, 0x02209, 0x00283 }, 326 { 140, 0x08804, 0x0220a, 0x00283 }, 327 328 { 149, 0x08808, 0x02429, 0x00281 }, 329 { 153, 0x08808, 0x0242b, 0x00281 }, 330 { 157, 0x08808, 0x0242d, 0x00281 }, 331 { 161, 0x08808, 0x0242f, 0x00281 } 332}; 333 334int 335rt2560_attach(void *xsc, int id) 336{ 337 struct rt2560_softc *sc = xsc; 338 struct ieee80211com *ic = &sc->sc_ic; 339 struct ifnet *ifp = &ic->ic_if; 340 int error, i; 341 342 timeout_set(&sc->scan_ch, rt2560_next_scan, sc); 343 timeout_set(&sc->rssadapt_ch, rt2560_rssadapt_updatestats, sc); 344 345 /* retrieve RT2560 rev. no */ 346 sc->asic_rev = RAL_READ(sc, RT2560_CSR0); 347 348 /* retrieve MAC address */ 349 rt2560_get_macaddr(sc, ic->ic_myaddr); 350 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 351 352 /* retrieve RF rev. no and various other things from EEPROM */ 353 rt2560_read_eeprom(sc); 354 355 printf("%s: MAC/BBP RT2560 (rev 0x%02x), RF %s\n", sc->sc_dev.dv_xname, 356 sc->asic_rev, rt2560_get_rf(sc->rf_rev)); 357 358 /* 359 * Allocate Tx and Rx rings. 360 */ 361 error = rt2560_alloc_tx_ring(sc, &sc->txq, RT2560_TX_RING_COUNT); 362 if (error != 0) { 363 printf("%s: could not allocate Tx ring\n", 364 sc->sc_dev.dv_xname); 365 goto fail1; 366 } 367 368 error = rt2560_alloc_tx_ring(sc, &sc->atimq, RT2560_ATIM_RING_COUNT); 369 if (error != 0) { 370 printf("%s: could not allocate ATIM ring\n", 371 sc->sc_dev.dv_xname); 372 goto fail2; 373 } 374 375 error = rt2560_alloc_tx_ring(sc, &sc->prioq, RT2560_PRIO_RING_COUNT); 376 if (error != 0) { 377 printf("%s: could not allocate Prio ring\n", 378 sc->sc_dev.dv_xname); 379 goto fail3; 380 } 381 382 error = rt2560_alloc_tx_ring(sc, &sc->bcnq, RT2560_BEACON_RING_COUNT); 383 if (error != 0) { 384 printf("%s: could not allocate Beacon ring\n", 385 sc->sc_dev.dv_xname); 386 goto fail4; 387 } 388 389 error = rt2560_alloc_rx_ring(sc, &sc->rxq, RT2560_RX_RING_COUNT); 390 if (error != 0) { 391 printf("%s: could not allocate Rx ring\n", 392 sc->sc_dev.dv_xname); 393 goto fail5; 394 } 395 396 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 397 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 398 ic->ic_state = IEEE80211_S_INIT; 399 400 /* set device capabilities */ 401 ic->ic_caps = IEEE80211_C_MONITOR | IEEE80211_C_IBSS | 402 IEEE80211_C_HOSTAP | IEEE80211_C_SHPREAMBLE | IEEE80211_C_PMGT | 403 IEEE80211_C_TXPMGT | IEEE80211_C_WEP; 404 405 if (sc->rf_rev == RT2560_RF_5222) { 406 /* set supported .11a rates */ 407 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2560_rateset_11a; 408 409 /* set supported .11a channels */ 410 for (i = 36; i <= 64; i += 4) { 411 ic->ic_channels[i].ic_freq = 412 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 413 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 414 } 415 for (i = 100; i <= 140; i += 4) { 416 ic->ic_channels[i].ic_freq = 417 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 418 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 419 } 420 for (i = 149; i <= 161; i += 4) { 421 ic->ic_channels[i].ic_freq = 422 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 423 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 424 } 425 } 426 427 /* set supported .11b and .11g rates */ 428 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2560_rateset_11b; 429 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2560_rateset_11g; 430 431 /* set supported .11b and .11g channels (1 through 14) */ 432 for (i = 1; i <= 14; i++) { 433 ic->ic_channels[i].ic_freq = 434 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 435 ic->ic_channels[i].ic_flags = 436 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 437 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 438 } 439 440 ifp->if_softc = sc; 441 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 442 ifp->if_init = rt2560_init; 443 ifp->if_ioctl = rt2560_ioctl; 444 ifp->if_start = rt2560_start; 445 ifp->if_watchdog = rt2560_watchdog; 446 IFQ_SET_READY(&ifp->if_snd); 447 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 448 449 if_attach(ifp); 450 ieee80211_ifattach(ifp); 451 ic->ic_node_alloc = rt2560_node_alloc; 452 ic->ic_node_copy = rt2560_node_copy; 453 454 /* override state transition machine */ 455 sc->sc_newstate = ic->ic_newstate; 456 ic->ic_newstate = rt2560_newstate; 457 ieee80211_media_init(ifp, rt2560_media_change, ieee80211_media_status); 458 459#if NBPFILTER > 0 460 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 461 sizeof (struct ieee80211_frame) + 64); 462 463 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 464 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 465 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2560_RX_RADIOTAP_PRESENT); 466 467 sc->sc_txtap_len = sizeof sc->sc_txtapu; 468 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 469 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2560_TX_RADIOTAP_PRESENT); 470#endif 471 472 return 0; 473 474fail5: rt2560_free_tx_ring(sc, &sc->bcnq); 475fail4: rt2560_free_tx_ring(sc, &sc->prioq); 476fail3: rt2560_free_tx_ring(sc, &sc->atimq); 477fail2: rt2560_free_tx_ring(sc, &sc->txq); 478fail1: return ENXIO; 479} 480 481int 482rt2560_detach(void *xsc) 483{ 484 struct rt2560_softc *sc = xsc; 485 struct ifnet *ifp = &sc->sc_ic.ic_if; 486 487 timeout_del(&sc->scan_ch); 488 timeout_del(&sc->rssadapt_ch); 489 490 ieee80211_ifdetach(ifp); 491 if_detach(ifp); 492 493 rt2560_free_tx_ring(sc, &sc->txq); 494 rt2560_free_tx_ring(sc, &sc->atimq); 495 rt2560_free_tx_ring(sc, &sc->prioq); 496 rt2560_free_tx_ring(sc, &sc->bcnq); 497 rt2560_free_rx_ring(sc, &sc->rxq); 498 499 return 0; 500} 501 502int 503rt2560_alloc_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring, 504 int count) 505{ 506 int i, nsegs, error; 507 508 ring->count = count; 509 ring->queued = 0; 510 ring->cur = ring->next = 0; 511 ring->cur_encrypt = ring->next_encrypt = 0; 512 513 error = bus_dmamap_create(sc->sc_dmat, count * RT2560_TX_DESC_SIZE, 1, 514 count * RT2560_TX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 515 if (error != 0) { 516 printf("%s: could not create desc DMA map\n", 517 sc->sc_dev.dv_xname); 518 goto fail; 519 } 520 521 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2560_TX_DESC_SIZE, 522 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 523 if (error != 0) { 524 printf("%s: could not allocate DMA memory\n", 525 sc->sc_dev.dv_xname); 526 goto fail; 527 } 528 529 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 530 count * RT2560_TX_DESC_SIZE, (caddr_t *)&ring->desc, 531 BUS_DMA_NOWAIT); 532 if (error != 0) { 533 printf("%s: could not map desc DMA memory\n", 534 sc->sc_dev.dv_xname); 535 goto fail; 536 } 537 538 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 539 count * RT2560_TX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 540 if (error != 0) { 541 printf("%s: could not load desc DMA map\n", 542 sc->sc_dev.dv_xname); 543 goto fail; 544 } 545 546 memset(ring->desc, 0, count * RT2560_TX_DESC_SIZE); 547 ring->physaddr = ring->map->dm_segs->ds_addr; 548 549 ring->data = malloc(count * sizeof (struct rt2560_tx_data), M_DEVBUF, 550 M_NOWAIT); 551 if (ring->data == NULL) { 552 printf("%s: could not allocate soft data\n", 553 sc->sc_dev.dv_xname); 554 error = ENOMEM; 555 goto fail; 556 } 557 558 memset(ring->data, 0, count * sizeof (struct rt2560_tx_data)); 559 for (i = 0; i < count; i++) { 560 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 561 RT2560_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT, 562 &ring->data[i].map); 563 if (error != 0) { 564 printf("%s: could not create DMA map\n", 565 sc->sc_dev.dv_xname); 566 goto fail; 567 } 568 } 569 570 return 0; 571 572fail: rt2560_free_tx_ring(sc, ring); 573 return error; 574} 575 576void 577rt2560_reset_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring) 578{ 579 struct ieee80211com *ic = &sc->sc_ic; 580 struct rt2560_tx_desc *desc; 581 struct rt2560_tx_data *data; 582 int i; 583 584 for (i = 0; i < ring->count; i++) { 585 desc = &ring->desc[i]; 586 data = &ring->data[i]; 587 588 if (data->m != NULL) { 589 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 590 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 591 bus_dmamap_unload(sc->sc_dmat, data->map); 592 m_freem(data->m); 593 data->m = NULL; 594 } 595 596 if (data->ni != NULL) { 597 ieee80211_release_node(ic, data->ni); 598 data->ni = NULL; 599 } 600 601 desc->flags = 0; 602 } 603 604 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 605 BUS_DMASYNC_PREWRITE); 606 607 ring->queued = 0; 608 ring->cur = ring->next = 0; 609 ring->cur_encrypt = ring->next_encrypt = 0; 610} 611 612void 613rt2560_free_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring) 614{ 615 struct ieee80211com *ic = &sc->sc_ic; 616 struct rt2560_tx_data *data; 617 int i; 618 619 if (ring->desc != NULL) { 620 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 621 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 622 bus_dmamap_unload(sc->sc_dmat, ring->map); 623 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->desc, 624 ring->count * RT2560_TX_DESC_SIZE); 625 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 626 } 627 628 if (ring->data != NULL) { 629 for (i = 0; i < ring->count; i++) { 630 data = &ring->data[i]; 631 632 if (data->m != NULL) { 633 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 634 data->map->dm_mapsize, 635 BUS_DMASYNC_POSTWRITE); 636 bus_dmamap_unload(sc->sc_dmat, data->map); 637 m_freem(data->m); 638 } 639 640 if (data->ni != NULL) 641 ieee80211_release_node(ic, data->ni); 642 643 if (data->map != NULL) 644 bus_dmamap_destroy(sc->sc_dmat, data->map); 645 } 646 free(ring->data, M_DEVBUF); 647 } 648} 649 650int 651rt2560_alloc_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring, 652 int count) 653{ 654 struct rt2560_rx_desc *desc; 655 struct rt2560_rx_data *data; 656 int i, nsegs, error; 657 658 ring->count = count; 659 ring->cur = ring->next = 0; 660 ring->cur_decrypt = 0; 661 662 error = bus_dmamap_create(sc->sc_dmat, count * RT2560_RX_DESC_SIZE, 1, 663 count * RT2560_RX_DESC_SIZE, 0, BUS_DMA_NOWAIT, &ring->map); 664 if (error != 0) { 665 printf("%s: could not create desc DMA map\n", 666 sc->sc_dev.dv_xname); 667 goto fail; 668 } 669 670 error = bus_dmamem_alloc(sc->sc_dmat, count * RT2560_RX_DESC_SIZE, 671 PAGE_SIZE, 0, &ring->seg, 1, &nsegs, BUS_DMA_NOWAIT); 672 if (error != 0) { 673 printf("%s: could not allocate DMA memory\n", 674 sc->sc_dev.dv_xname); 675 goto fail; 676 } 677 678 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, 679 count * RT2560_RX_DESC_SIZE, (caddr_t *)&ring->desc, 680 BUS_DMA_NOWAIT); 681 if (error != 0) { 682 printf("%s: could not map desc DMA memory\n", 683 sc->sc_dev.dv_xname); 684 goto fail; 685 } 686 687 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->desc, 688 count * RT2560_RX_DESC_SIZE, NULL, BUS_DMA_NOWAIT); 689 if (error != 0) { 690 printf("%s: could not load desc DMA map\n", 691 sc->sc_dev.dv_xname); 692 goto fail; 693 } 694 695 memset(ring->desc, 0, count * RT2560_RX_DESC_SIZE); 696 ring->physaddr = ring->map->dm_segs->ds_addr; 697 698 ring->data = malloc(count * sizeof (struct rt2560_rx_data), M_DEVBUF, 699 M_NOWAIT); 700 if (ring->data == NULL) { 701 printf("%s: could not allocate soft data\n", 702 sc->sc_dev.dv_xname); 703 error = ENOMEM; 704 goto fail; 705 } 706 707 /* 708 * Pre-allocate Rx buffers and populate Rx ring. 709 */ 710 memset(ring->data, 0, count * sizeof (struct rt2560_rx_data)); 711 for (i = 0; i < count; i++) { 712 desc = &sc->rxq.desc[i]; 713 data = &sc->rxq.data[i]; 714 715 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 716 0, BUS_DMA_NOWAIT, &data->map); 717 if (error != 0) { 718 printf("%s: could not create DMA map\n", 719 sc->sc_dev.dv_xname); 720 goto fail; 721 } 722 723 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 724 if (data->m == NULL) { 725 printf("%s: could not allocate rx mbuf\n", 726 sc->sc_dev.dv_xname); 727 error = ENOMEM; 728 goto fail; 729 } 730 731 MCLGET(data->m, M_DONTWAIT); 732 if (!(data->m->m_flags & M_EXT)) { 733 printf("%s: could not allocate rx mbuf cluster\n", 734 sc->sc_dev.dv_xname); 735 error = ENOMEM; 736 goto fail; 737 } 738 739 error = bus_dmamap_load(sc->sc_dmat, data->map, 740 mtod(data->m, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 741 if (error != 0) { 742 printf("%s: could not load rx buf DMA map", 743 sc->sc_dev.dv_xname); 744 goto fail; 745 } 746 747 desc->flags = htole32(RT2560_RX_BUSY); 748 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 749 } 750 751 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 752 BUS_DMASYNC_PREWRITE); 753 754 return 0; 755 756fail: rt2560_free_rx_ring(sc, ring); 757 return error; 758} 759 760void 761rt2560_reset_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring) 762{ 763 int i; 764 765 for (i = 0; i < ring->count; i++) { 766 ring->desc[i].flags = htole32(RT2560_RX_BUSY); 767 ring->data[i].drop = 0; 768 } 769 770 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize, 771 BUS_DMASYNC_PREWRITE); 772 773 ring->cur = ring->next = 0; 774 ring->cur_decrypt = 0; 775} 776 777void 778rt2560_free_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring) 779{ 780 struct rt2560_rx_data *data; 781 int i; 782 783 if (ring->desc != NULL) { 784 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, 785 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 786 bus_dmamap_unload(sc->sc_dmat, ring->map); 787 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->desc, 788 ring->count * RT2560_RX_DESC_SIZE); 789 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1); 790 } 791 792 if (ring->data != NULL) { 793 for (i = 0; i < ring->count; i++) { 794 data = &ring->data[i]; 795 796 if (data->m != NULL) { 797 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 798 data->map->dm_mapsize, 799 BUS_DMASYNC_POSTREAD); 800 bus_dmamap_unload(sc->sc_dmat, data->map); 801 m_freem(data->m); 802 } 803 804 if (data->map != NULL) 805 bus_dmamap_destroy(sc->sc_dmat, data->map); 806 } 807 free(ring->data, M_DEVBUF); 808 } 809} 810 811struct ieee80211_node * 812rt2560_node_alloc(struct ieee80211com *ic) 813{ 814 struct rt2560_node *rn; 815 816 rn = malloc(sizeof (struct rt2560_node), M_DEVBUF, M_NOWAIT); 817 if (rn == NULL) 818 return NULL; 819 820 memset(rn, 0, sizeof (struct rt2560_node)); 821 822 return &rn->ni; 823} 824 825void 826rt2560_node_copy(struct ieee80211com *ic, struct ieee80211_node *dst, 827 const struct ieee80211_node *src) 828{ 829 *(struct rt2560_node *)dst = *(const struct rt2560_node *)src; 830} 831 832int 833rt2560_media_change(struct ifnet *ifp) 834{ 835 int error; 836 837 error = ieee80211_media_change(ifp); 838 if (error != ENETRESET) 839 return error; 840 841 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 842 rt2560_init(ifp); 843 844 return 0; 845} 846 847/* 848 * This function is called periodically (every 200ms) during scanning to 849 * switch from one channel to another. 850 */ 851void 852rt2560_next_scan(void *arg) 853{ 854 struct rt2560_softc *sc = arg; 855 struct ieee80211com *ic = &sc->sc_ic; 856 struct ifnet *ifp = &ic->ic_if; 857 858 if (ic->ic_state == IEEE80211_S_SCAN) 859 ieee80211_next_scan(ifp); 860} 861 862/* 863 * This function is called for each neighbor node. 864 */ 865void 866rt2560_iter_func(void *arg, struct ieee80211_node *ni) 867{ 868 struct rt2560_node *rn = (struct rt2560_node *)ni; 869 870 ieee80211_rssadapt_updatestats(&rn->rssadapt); 871} 872 873/* 874 * This function is called periodically (every 100ms) in RUN state to update 875 * the rate adaptation statistics. 876 */ 877void 878rt2560_rssadapt_updatestats(void *arg) 879{ 880 struct rt2560_softc *sc = arg; 881 struct ieee80211com *ic = &sc->sc_ic; 882 883 ieee80211_iterate_nodes(ic, rt2560_iter_func, arg); 884 885 timeout_add(&sc->rssadapt_ch, hz / 10); 886} 887 888int 889rt2560_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 890{ 891 struct rt2560_softc *sc = ic->ic_if.if_softc; 892 enum ieee80211_state ostate; 893 struct mbuf *m; 894 int error = 0; 895 896 ostate = ic->ic_state; 897 timeout_del(&sc->scan_ch); 898 899 switch (nstate) { 900 case IEEE80211_S_INIT: 901 timeout_del(&sc->rssadapt_ch); 902 903 if (ostate == IEEE80211_S_RUN) { 904 /* abort TSF synchronization */ 905 RAL_WRITE(sc, RT2560_CSR14, 0); 906 907 /* turn association led off */ 908 rt2560_update_led(sc, 0, 0); 909 } 910 break; 911 912 case IEEE80211_S_SCAN: 913 rt2560_set_chan(sc, ic->ic_bss->ni_chan); 914 timeout_add(&sc->scan_ch, hz / 5); 915 break; 916 917 case IEEE80211_S_AUTH: 918 rt2560_set_chan(sc, ic->ic_bss->ni_chan); 919 break; 920 921 case IEEE80211_S_ASSOC: 922 rt2560_set_chan(sc, ic->ic_bss->ni_chan); 923 break; 924 925 case IEEE80211_S_RUN: 926 rt2560_set_chan(sc, ic->ic_bss->ni_chan); 927 928 /* update basic rate set */ 929 if (ic->ic_curmode == IEEE80211_MODE_11B) { 930 /* 11b basic rates: 1, 2Mbps */ 931 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x3); 932 } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) { 933 /* 11a basic rates: 6, 12, 24Mbps */ 934 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x150); 935 } else { 936 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 937 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x15f); 938 } 939 940 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 941 rt2560_set_bssid(sc, ic->ic_bss->ni_bssid); 942 rt2560_update_slot(sc); 943 } 944 945 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 946 ic->ic_opmode == IEEE80211_M_IBSS) { 947 m = ieee80211_beacon_alloc(ic, ic->ic_bss); 948 if (m == NULL) { 949 printf("%s: could not allocate beacon\n", 950 sc->sc_dev.dv_xname); 951 error = ENOBUFS; 952 break; 953 } 954 955 error = rt2560_tx_bcn(sc, m, ic->ic_bss); 956 if (error != 0) 957 break; 958 } 959 960 /* turn assocation led on */ 961 rt2560_update_led(sc, 1, 0); 962 963 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 964 timeout_add(&sc->rssadapt_ch, hz / 10); 965 rt2560_enable_tsf_sync(sc); 966 } 967 break; 968 } 969 970 return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg); 971} 972 973/* 974 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 975 * 93C66). 976 */ 977uint16_t 978rt2560_eeprom_read(struct rt2560_softc *sc, uint8_t addr) 979{ 980 uint32_t tmp; 981 uint16_t val; 982 int n; 983 984 /* clock C once before the first command */ 985 RT2560_EEPROM_CTL(sc, 0); 986 987 RT2560_EEPROM_CTL(sc, RT2560_S); 988 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C); 989 RT2560_EEPROM_CTL(sc, RT2560_S); 990 991 /* write start bit (1) */ 992 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D); 993 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C); 994 995 /* write READ opcode (10) */ 996 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D); 997 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C); 998 RT2560_EEPROM_CTL(sc, RT2560_S); 999 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C); 1000 1001 /* write address (A5-A0 or A7-A0) */ 1002 n = (RAL_READ(sc, RT2560_CSR21) & RT2560_93C46) ? 5 : 7; 1003 for (; n >= 0; n--) { 1004 RT2560_EEPROM_CTL(sc, RT2560_S | 1005 (((addr >> n) & 1) << RT2560_SHIFT_D)); 1006 RT2560_EEPROM_CTL(sc, RT2560_S | 1007 (((addr >> n) & 1) << RT2560_SHIFT_D) | RT2560_C); 1008 } 1009 1010 RT2560_EEPROM_CTL(sc, RT2560_S); 1011 1012 /* read data Q15-Q0 */ 1013 val = 0; 1014 for (n = 15; n >= 0; n--) { 1015 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C); 1016 tmp = RAL_READ(sc, RT2560_CSR21); 1017 val |= ((tmp & RT2560_Q) >> RT2560_SHIFT_Q) << n; 1018 RT2560_EEPROM_CTL(sc, RT2560_S); 1019 } 1020 1021 RT2560_EEPROM_CTL(sc, 0); 1022 1023 /* clear Chip Select and clock C */ 1024 RT2560_EEPROM_CTL(sc, RT2560_S); 1025 RT2560_EEPROM_CTL(sc, 0); 1026 RT2560_EEPROM_CTL(sc, RT2560_C); 1027 1028 return val; 1029} 1030 1031/* 1032 * Some frames were processed by the hardware cipher engine and are ready for 1033 * transmission. 1034 */ 1035void 1036rt2560_encryption_intr(struct rt2560_softc *sc) 1037{ 1038 struct rt2560_tx_desc *desc; 1039 int hw; 1040 1041 /* retrieve last descriptor index processed by cipher engine */ 1042 hw = (RAL_READ(sc, RT2560_SECCSR1) - sc->txq.physaddr) / 1043 RT2560_TX_DESC_SIZE; 1044 1045 for (; sc->txq.next_encrypt != hw;) { 1046 desc = &sc->txq.desc[sc->txq.next_encrypt]; 1047 1048 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 1049 sc->txq.next_encrypt * RT2560_TX_DESC_SIZE, 1050 RT2560_TX_DESC_SIZE, BUS_DMASYNC_POSTREAD); 1051 1052 if (letoh32(desc->flags) & 1053 (RT2560_TX_BUSY | RT2560_TX_CIPHER_BUSY)) 1054 break; 1055 1056 /* for TKIP, swap eiv field to fix a bug in ASIC */ 1057 if ((letoh32(desc->flags) & RT2560_TX_CIPHER_MASK) == 1058 RT2560_TX_CIPHER_TKIP) 1059 desc->eiv = swap32(desc->eiv); 1060 1061 /* mark the frame ready for transmission */ 1062 desc->flags |= htole32(RT2560_TX_BUSY | RT2560_TX_VALID); 1063 1064 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 1065 sc->txq.next_encrypt * RT2560_TX_DESC_SIZE, 1066 RT2560_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1067 1068 DPRINTFN(15, ("encryption done idx=%u\n", 1069 sc->txq.next_encrypt)); 1070 1071 sc->txq.next_encrypt = 1072 (sc->txq.next_encrypt + 1) % RT2560_TX_RING_COUNT; 1073 } 1074 1075 /* kick Tx */ 1076 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_TX); 1077} 1078 1079void 1080rt2560_tx_intr(struct rt2560_softc *sc) 1081{ 1082 struct ieee80211com *ic = &sc->sc_ic; 1083 struct ifnet *ifp = &ic->ic_if; 1084 struct rt2560_tx_desc *desc; 1085 struct rt2560_tx_data *data; 1086 struct rt2560_node *rn; 1087 1088 for (;;) { 1089 desc = &sc->txq.desc[sc->txq.next]; 1090 data = &sc->txq.data[sc->txq.next]; 1091 1092 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 1093 sc->txq.next * RT2560_TX_DESC_SIZE, RT2560_TX_DESC_SIZE, 1094 BUS_DMASYNC_POSTREAD); 1095 1096 if ((letoh32(desc->flags) & RT2560_TX_BUSY) || 1097 (letoh32(desc->flags) & RT2560_TX_CIPHER_BUSY) || 1098 !(letoh32(desc->flags) & RT2560_TX_VALID)) 1099 break; 1100 1101 rn = (struct rt2560_node *)data->ni; 1102 1103 switch (letoh32(desc->flags) & RT2560_TX_RESULT_MASK) { 1104 case RT2560_TX_SUCCESS: 1105 DPRINTFN(10, ("data frame sent successfully\n")); 1106 if (data->id.id_node != NULL) { 1107 ieee80211_rssadapt_raise_rate(ic, 1108 &rn->rssadapt, &data->id); 1109 } 1110 ifp->if_opackets++; 1111 break; 1112 1113 case RT2560_TX_SUCCESS_RETRY: 1114 DPRINTFN(9, ("data frame sent after %u retries\n", 1115 (letoh32(desc->flags) >> 5) & 0x7)); 1116 ifp->if_opackets++; 1117 break; 1118 1119 case RT2560_TX_FAIL_RETRY: 1120 DPRINTFN(9, ("sending data frame failed (too much " 1121 "retries)\n")); 1122 if (data->id.id_node != NULL) { 1123 ieee80211_rssadapt_lower_rate(ic, data->ni, 1124 &rn->rssadapt, &data->id); 1125 } 1126 ifp->if_oerrors++; 1127 break; 1128 1129 case RT2560_TX_FAIL_INVALID: 1130 case RT2560_TX_FAIL_OTHER: 1131 default: 1132 printf("%s: sending data frame failed 0x%08x\n", 1133 sc->sc_dev.dv_xname, letoh32(desc->flags)); 1134 ifp->if_oerrors++; 1135 } 1136 1137 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1138 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1139 bus_dmamap_unload(sc->sc_dmat, data->map); 1140 m_freem(data->m); 1141 data->m = NULL; 1142 ieee80211_release_node(ic, data->ni); 1143 data->ni = NULL; 1144 1145 /* descriptor is no longer valid */ 1146 desc->flags &= ~htole32(RT2560_TX_VALID); 1147 1148 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 1149 sc->txq.next * RT2560_TX_DESC_SIZE, RT2560_TX_DESC_SIZE, 1150 BUS_DMASYNC_PREWRITE); 1151 1152 DPRINTFN(15, ("tx done idx=%u\n", sc->txq.next)); 1153 1154 sc->txq.queued--; 1155 sc->txq.next = (sc->txq.next + 1) % RT2560_TX_RING_COUNT; 1156 } 1157 1158 sc->sc_tx_timer = 0; 1159 ifp->if_flags &= ~IFF_OACTIVE; 1160 rt2560_start(ifp); 1161} 1162 1163void 1164rt2560_prio_intr(struct rt2560_softc *sc) 1165{ 1166 struct ieee80211com *ic = &sc->sc_ic; 1167 struct ifnet *ifp = &ic->ic_if; 1168 struct rt2560_tx_desc *desc; 1169 struct rt2560_tx_data *data; 1170 1171 for (;;) { 1172 desc = &sc->prioq.desc[sc->prioq.next]; 1173 data = &sc->prioq.data[sc->prioq.next]; 1174 1175 bus_dmamap_sync(sc->sc_dmat, sc->prioq.map, 1176 sc->prioq.next * RT2560_TX_DESC_SIZE, RT2560_TX_DESC_SIZE, 1177 BUS_DMASYNC_POSTREAD); 1178 1179 if ((letoh32(desc->flags) & RT2560_TX_BUSY) || 1180 !(letoh32(desc->flags) & RT2560_TX_VALID)) 1181 break; 1182 1183 switch (letoh32(desc->flags) & RT2560_TX_RESULT_MASK) { 1184 case RT2560_TX_SUCCESS: 1185 DPRINTFN(10, ("mgt frame sent successfully\n")); 1186 break; 1187 1188 case RT2560_TX_SUCCESS_RETRY: 1189 DPRINTFN(9, ("mgt frame sent after %u retries\n", 1190 (letoh32(desc->flags) >> 5) & 0x7)); 1191 break; 1192 1193 case RT2560_TX_FAIL_RETRY: 1194 DPRINTFN(9, ("sending mgt frame failed (too much " 1195 "retries)\n")); 1196 break; 1197 1198 case RT2560_TX_FAIL_INVALID: 1199 case RT2560_TX_FAIL_OTHER: 1200 default: 1201 printf("%s: sending mgt frame failed 0x%08x\n", 1202 sc->sc_dev.dv_xname, letoh32(desc->flags)); 1203 } 1204 1205 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1206 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1207 bus_dmamap_unload(sc->sc_dmat, data->map); 1208 m_freem(data->m); 1209 data->m = NULL; 1210 ieee80211_release_node(ic, data->ni); 1211 data->ni = NULL; 1212 1213 /* descriptor is no longer valid */ 1214 desc->flags &= ~htole32(RT2560_TX_VALID); 1215 1216 bus_dmamap_sync(sc->sc_dmat, sc->prioq.map, 1217 sc->prioq.next * RT2560_TX_DESC_SIZE, RT2560_TX_DESC_SIZE, 1218 BUS_DMASYNC_PREWRITE); 1219 1220 DPRINTFN(15, ("prio done idx=%u\n", sc->prioq.next)); 1221 1222 sc->prioq.queued--; 1223 sc->prioq.next = (sc->prioq.next + 1) % RT2560_PRIO_RING_COUNT; 1224 } 1225 1226 sc->sc_tx_timer = 0; 1227 ifp->if_flags &= ~IFF_OACTIVE; 1228 rt2560_start(ifp); 1229} 1230 1231/* 1232 * Some frames were processed by the hardware cipher engine and are ready for 1233 * transmission to the IEEE802.11 layer. 1234 */ 1235void 1236rt2560_decryption_intr(struct rt2560_softc *sc) 1237{ 1238 struct ieee80211com *ic = &sc->sc_ic; 1239 struct ifnet *ifp = &ic->ic_if; 1240 struct rt2560_rx_desc *desc; 1241 struct rt2560_rx_data *data; 1242 struct rt2560_node *rn; 1243 struct ieee80211_frame *wh; 1244 struct ieee80211_node *ni; 1245 struct mbuf *mnew, *m; 1246 int hw, error; 1247 1248 /* retrieve last decriptor index processed by cipher engine */ 1249 hw = (RAL_READ(sc, RT2560_SECCSR0) - sc->rxq.physaddr) / 1250 RT2560_RX_DESC_SIZE; 1251 1252 for (; sc->rxq.cur_decrypt != hw;) { 1253 desc = &sc->rxq.desc[sc->rxq.cur_decrypt]; 1254 data = &sc->rxq.data[sc->rxq.cur_decrypt]; 1255 1256 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1257 sc->rxq.cur_decrypt * RT2560_TX_DESC_SIZE, 1258 RT2560_TX_DESC_SIZE, BUS_DMASYNC_POSTREAD); 1259 1260 if (letoh32(desc->flags) & 1261 (RT2560_RX_BUSY | RT2560_RX_CIPHER_BUSY)) 1262 break; 1263 1264 if (data->drop) { 1265 ifp->if_ierrors++; 1266 goto skip; 1267 } 1268 1269 if ((letoh32(desc->flags) & RT2560_RX_CIPHER_MASK) != 0 && 1270 (letoh32(desc->flags) & RT2560_RX_ICV_ERROR)) { 1271 ifp->if_ierrors++; 1272 goto skip; 1273 } 1274 1275 /* 1276 * Try to allocate a new mbuf for this ring element and load it 1277 * before processing the current mbuf. If the ring element 1278 * cannot be loaded, drop the received packet and reuse the old 1279 * mbuf. In the unlikely case that the old mbuf can't be 1280 * reloaded either, explicitly panic. 1281 */ 1282 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1283 if (mnew == NULL) { 1284 ifp->if_ierrors++; 1285 goto skip; 1286 } 1287 1288 MCLGET(mnew, M_DONTWAIT); 1289 if (!(mnew->m_flags & M_EXT)) { 1290 m_freem(mnew); 1291 ifp->if_ierrors++; 1292 goto skip; 1293 } 1294 1295 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1296 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1297 bus_dmamap_unload(sc->sc_dmat, data->map); 1298 1299 error = bus_dmamap_load(sc->sc_dmat, data->map, 1300 mtod(mnew, void *), MCLBYTES, NULL, BUS_DMA_NOWAIT); 1301 if (error != 0) { 1302 m_freem(mnew); 1303 1304 /* try to reload the old mbuf */ 1305 error = bus_dmamap_load(sc->sc_dmat, data->map, 1306 mtod(data->m, void *), MCLBYTES, NULL, 1307 BUS_DMA_NOWAIT); 1308 if (error != 0) { 1309 /* very unlikely that it will fail... */ 1310 panic("%s: could not load old rx mbuf", 1311 sc->sc_dev.dv_xname); 1312 } 1313 ifp->if_ierrors++; 1314 goto skip; 1315 } 1316 1317 /* 1318 * New mbuf successfully loaded, update Rx ring and continue 1319 * processing. 1320 */ 1321 m = data->m; 1322 data->m = mnew; 1323 desc->physaddr = htole32(data->map->dm_segs->ds_addr); 1324 1325 /* finalize mbuf */ 1326 m->m_pkthdr.rcvif = ifp; 1327 m->m_pkthdr.len = m->m_len = 1328 (letoh32(desc->flags) >> 16) & 0xfff; 1329 1330#if NBPFILTER > 0 1331 if (sc->sc_drvbpf != NULL) { 1332 struct mbuf mb; 1333 struct rt2560_rx_radiotap_header *tap = &sc->sc_rxtap; 1334 uint32_t tsf_lo, tsf_hi; 1335 1336 /* get timestamp (low and high 32 bits) */ 1337 tsf_lo = RAL_READ(sc, RT2560_CSR16); 1338 tsf_hi = RAL_READ(sc, RT2560_CSR17); 1339 1340 tap->wr_tsf = 1341 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1342 tap->wr_flags = 0; 1343 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1344 tap->wr_chan_flags = 1345 htole16(ic->ic_ibss_chan->ic_flags); 1346 tap->wr_antenna = sc->rx_ant; 1347 tap->wr_antsignal = desc->rssi; 1348 1349 M_DUP_PKTHDR(&mb, m); 1350 mb.m_data = (caddr_t)tap; 1351 mb.m_len = sc->sc_txtap_len; 1352 mb.m_next = m; 1353 mb.m_pkthdr.len += mb.m_len; 1354 bpf_mtap(sc->sc_drvbpf, &mb); 1355 } 1356#endif 1357 1358 wh = mtod(m, struct ieee80211_frame *); 1359 ni = ieee80211_find_rxnode(ic, wh); 1360 1361 /* send the frame to the 802.11 layer */ 1362 ieee80211_input(ifp, m, ni, desc->rssi, 0); 1363 1364 /* give rssi to the rate adatation algorithm */ 1365 rn = (struct rt2560_node *)ni; 1366 ieee80211_rssadapt_input(ic, ni, &rn->rssadapt, desc->rssi); 1367 1368 /* node is no longer needed */ 1369 ieee80211_release_node(ic, ni); 1370 1371skip: desc->flags = htole32(RT2560_RX_BUSY); 1372 1373 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1374 sc->rxq.cur_decrypt * RT2560_TX_DESC_SIZE, 1375 RT2560_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1376 1377 DPRINTFN(15, ("decryption done idx=%u\n", sc->rxq.cur_decrypt)); 1378 1379 sc->rxq.cur_decrypt = 1380 (sc->rxq.cur_decrypt + 1) % RT2560_RX_RING_COUNT; 1381 } 1382 1383 /* 1384 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 1385 * without calling if_start(). 1386 */ 1387 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 1388 rt2560_start(ifp); 1389} 1390 1391/* 1392 * Some frames were received. Pass them to the hardware cipher engine before 1393 * sending them to the 802.11 layer. 1394 */ 1395void 1396rt2560_rx_intr(struct rt2560_softc *sc) 1397{ 1398 struct rt2560_rx_desc *desc; 1399 struct rt2560_rx_data *data; 1400 1401 for (;;) { 1402 desc = &sc->rxq.desc[sc->rxq.cur]; 1403 data = &sc->rxq.data[sc->rxq.cur]; 1404 1405 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1406 sc->rxq.cur * RT2560_RX_DESC_SIZE, RT2560_RX_DESC_SIZE, 1407 BUS_DMASYNC_POSTREAD); 1408 1409 if (letoh32(desc->flags) & 1410 (RT2560_RX_BUSY | RT2560_RX_CIPHER_BUSY)) 1411 break; 1412 1413 data->drop = 0; 1414 1415 if (letoh32(desc->flags) & 1416 (RT2560_RX_PHY_ERROR | RT2560_RX_CRC_ERROR)) { 1417 /* 1418 * This should not happen since we did not request 1419 * to receive those frames when we filled RXCSR0. 1420 */ 1421 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1422 letoh32(desc->flags))); 1423 data->drop = 1; 1424 } 1425 1426 if (((letoh32(desc->flags) >> 16) & 0xfff) > MCLBYTES) { 1427 DPRINTFN(5, ("bad length\n")); 1428 data->drop = 1; 1429 } 1430 1431 /* mark the frame for decryption */ 1432 desc->flags |= htole32(RT2560_RX_CIPHER_BUSY); 1433 1434 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map, 1435 sc->rxq.cur * RT2560_RX_DESC_SIZE, RT2560_RX_DESC_SIZE, 1436 BUS_DMASYNC_PREWRITE); 1437 1438 DPRINTFN(15, ("rx done idx=%u\n", sc->rxq.cur)); 1439 1440 sc->rxq.cur = (sc->rxq.cur + 1) % RT2560_RX_RING_COUNT; 1441 } 1442 1443 /* kick decrypt */ 1444 RAL_WRITE(sc, RT2560_SECCSR0, RT2560_KICK_DECRYPT); 1445} 1446 1447/* 1448 * This function is called periodically in IBSS mode when a new beacon must be 1449 * sent out. 1450 */ 1451void 1452rt2560_beacon_expire(struct rt2560_softc *sc) 1453{ 1454 struct ieee80211com *ic = &sc->sc_ic; 1455 struct rt2560_tx_data *data; 1456 1457 if (ic->ic_opmode != IEEE80211_M_IBSS && 1458 ic->ic_opmode != IEEE80211_M_HOSTAP) 1459 return; 1460 1461 data = &sc->bcnq.data[sc->bcnq.next]; 1462 1463#if NBPFILTER > 0 1464 if (ic->ic_rawbpf != NULL) 1465 bpf_mtap(ic->ic_rawbpf, data->m); 1466#endif 1467 1468 DPRINTFN(15, ("beacon expired\n")); 1469} 1470 1471void 1472rt2560_wakeup_expire(struct rt2560_softc *sc) 1473{ 1474 DPRINTFN(15, ("wakeup expired\n")); 1475} 1476 1477int 1478rt2560_intr(void *arg) 1479{ 1480 struct rt2560_softc *sc = arg; 1481 uint32_t r; 1482 1483 /* disable interrupts */ 1484 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff); 1485 1486 r = RAL_READ(sc, RT2560_CSR7); 1487 RAL_WRITE(sc, RT2560_CSR7, r); 1488 1489 if (r & RT2560_BEACON_EXPIRE) 1490 rt2560_beacon_expire(sc); 1491 1492 if (r & RT2560_WAKEUP_EXPIRE) 1493 rt2560_wakeup_expire(sc); 1494 1495 if (r & RT2560_ENCRYPTION_DONE) 1496 rt2560_encryption_intr(sc); 1497 1498 if (r & RT2560_TX_DONE) 1499 rt2560_tx_intr(sc); 1500 1501 if (r & RT2560_PRIO_DONE) 1502 rt2560_prio_intr(sc); 1503 1504 if (r & RT2560_DECRYPTION_DONE) 1505 rt2560_decryption_intr(sc); 1506 1507 if (r & RT2560_RX_DONE) 1508 rt2560_rx_intr(sc); 1509 1510 /* re-enable interrupts */ 1511 RAL_WRITE(sc, RT2560_CSR8, RT2560_INTR_MASK); 1512 1513 return 1; 1514} 1515 1516/* quickly determine if a given rate is CCK or OFDM */ 1517#define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1518 1519#define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1520#define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1521 1522#define RAL_SIFS 10 /* us */ 1523 1524#define RT2560_RXTX_TURNAROUND 10 /* us */ 1525 1526/* 1527 * Return the expected ack rate for a frame transmitted at rate `rate'. 1528 * XXX: this should depend on the destination node basic rate set. 1529 */ 1530int 1531rt2560_ack_rate(struct ieee80211com *ic, int rate) 1532{ 1533 switch (rate) { 1534 /* CCK rates */ 1535 case 2: 1536 return 2; 1537 case 4: 1538 case 11: 1539 case 22: 1540 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1541 1542 /* OFDM rates */ 1543 case 12: 1544 case 18: 1545 return 12; 1546 case 24: 1547 case 36: 1548 return 24; 1549 case 48: 1550 case 72: 1551 case 96: 1552 case 108: 1553 return 48; 1554 } 1555 1556 /* default to 1Mbps */ 1557 return 2; 1558} 1559 1560/* 1561 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1562 * The function automatically determines the operating mode depending on the 1563 * given rate. `flags' indicates whether short preamble is in use or not. 1564 */ 1565uint16_t 1566rt2560_txtime(int len, int rate, uint32_t flags) 1567{ 1568 uint16_t txtime; 1569 1570 if (RAL_RATE_IS_OFDM(rate)) { 1571 /* IEEE Std 802.11a-1999, pp. 37 */ 1572 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1573 txtime = 16 + 4 + 4 * txtime + 6; 1574 } else { 1575 /* IEEE Std 802.11b-1999, pp. 28 */ 1576 txtime = (16 * len + rate - 1) / rate; 1577 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1578 txtime += 72 + 24; 1579 else 1580 txtime += 144 + 48; 1581 } 1582 return txtime; 1583} 1584 1585uint8_t 1586rt2560_plcp_signal(int rate) 1587{ 1588 switch (rate) { 1589 /* CCK rates (returned values are device-dependent) */ 1590 case 2: return 0x0; 1591 case 4: return 0x1; 1592 case 11: return 0x2; 1593 case 22: return 0x3; 1594 1595 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1596 case 12: return 0xb; 1597 case 18: return 0xf; 1598 case 24: return 0xa; 1599 case 36: return 0xe; 1600 case 48: return 0x9; 1601 case 72: return 0xd; 1602 case 96: return 0x8; 1603 case 108: return 0xc; 1604 1605 /* unsupported rates (should not get there) */ 1606 default: return 0xff; 1607 } 1608} 1609 1610void 1611rt2560_setup_tx_desc(struct rt2560_softc *sc, struct rt2560_tx_desc *desc, 1612 uint32_t flags, int len, int rate, int encrypt, bus_addr_t physaddr) 1613{ 1614 struct ieee80211com *ic = &sc->sc_ic; 1615 uint16_t plcp_length; 1616 int remainder; 1617 1618 desc->flags = htole32(flags); 1619 desc->flags |= htole32(len << 16); 1620 desc->flags |= encrypt ? htole32(RT2560_TX_CIPHER_BUSY) : 1621 htole32(RT2560_TX_BUSY | RT2560_TX_VALID); 1622 1623 desc->physaddr = htole32(physaddr); 1624 desc->wme = htole16( 1625 RT2560_AIFSN(2) | 1626 RT2560_LOGCWMIN(3) | 1627 RT2560_LOGCWMAX(8)); 1628 1629 /* setup PLCP fields */ 1630 desc->plcp_signal = rt2560_plcp_signal(rate); 1631 desc->plcp_service = 4; 1632 1633 len += IEEE80211_CRC_LEN; 1634 if (RAL_RATE_IS_OFDM(rate)) { 1635 desc->flags |= htole32(RT2560_TX_OFDM); 1636 1637 plcp_length = len & 0xfff; 1638 desc->plcp_length_hi = plcp_length >> 6; 1639 desc->plcp_length_lo = plcp_length & 0x3f; 1640 } else { 1641 plcp_length = (16 * len + rate - 1) / rate; 1642 if (rate == 22) { 1643 remainder = (16 * len) % 22; 1644 if (remainder != 0 && remainder < 7) 1645 desc->plcp_service |= RT2560_PLCP_LENGEXT; 1646 } 1647 desc->plcp_length_hi = plcp_length >> 8; 1648 desc->plcp_length_lo = plcp_length & 0xff; 1649 1650 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1651 desc->plcp_signal |= 0x08; 1652 } 1653} 1654 1655int 1656rt2560_tx_bcn(struct rt2560_softc *sc, struct mbuf *m0, 1657 struct ieee80211_node *ni) 1658{ 1659 struct rt2560_tx_desc *desc; 1660 struct rt2560_tx_data *data; 1661 int rate, error; 1662 1663 desc = &sc->bcnq.desc[sc->bcnq.cur]; 1664 data = &sc->bcnq.data[sc->bcnq.cur]; 1665 1666 rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 1667 1668 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1669 BUS_DMA_NOWAIT); 1670 if (error != 0) { 1671 printf("%s: could not map mbuf (error %d)\n", 1672 sc->sc_dev.dv_xname, error); 1673 m_freem(m0); 1674 return error; 1675 } 1676 1677 data->m = m0; 1678 data->ni = ni; 1679 1680 rt2560_setup_tx_desc(sc, desc, RT2560_TX_IFS_NEWBACKOFF | 1681 RT2560_TX_TIMESTAMP, m0->m_pkthdr.len, rate, 0, 1682 data->map->dm_segs->ds_addr); 1683 1684 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1685 BUS_DMASYNC_PREWRITE); 1686 bus_dmamap_sync(sc->sc_dmat, sc->bcnq.map, 1687 sc->bcnq.cur * RT2560_TX_DESC_SIZE, RT2560_TX_DESC_SIZE, 1688 BUS_DMASYNC_PREWRITE); 1689 1690 return 0; 1691} 1692 1693int 1694rt2560_tx_mgt(struct rt2560_softc *sc, struct mbuf *m0, 1695 struct ieee80211_node *ni) 1696{ 1697 struct ieee80211com *ic = &sc->sc_ic; 1698 struct rt2560_tx_desc *desc; 1699 struct rt2560_tx_data *data; 1700 struct ieee80211_frame *wh; 1701 uint16_t dur; 1702 uint32_t flags = 0; 1703 int rate, error; 1704 1705 desc = &sc->prioq.desc[sc->prioq.cur]; 1706 data = &sc->prioq.data[sc->prioq.cur]; 1707 1708 rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 1709 1710 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1711 BUS_DMA_NOWAIT); 1712 if (error != 0) { 1713 printf("%s: could not map mbuf (error %d)\n", 1714 sc->sc_dev.dv_xname, error); 1715 m_freem(m0); 1716 return error; 1717 } 1718 1719#if NBPFILTER > 0 1720 if (sc->sc_drvbpf != NULL) { 1721 struct mbuf mb; 1722 struct rt2560_tx_radiotap_header *tap = &sc->sc_txtap; 1723 1724 tap->wt_flags = 0; 1725 tap->wt_rate = rate; 1726 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1727 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1728 tap->wt_antenna = sc->tx_ant; 1729 1730 M_DUP_PKTHDR(&mb, m0); 1731 mb.m_data = (caddr_t)tap; 1732 mb.m_len = sc->sc_txtap_len; 1733 mb.m_next = m0; 1734 mb.m_pkthdr.len += mb.m_len; 1735 bpf_mtap(sc->sc_drvbpf, &mb); 1736 } 1737#endif 1738 1739 data->m = m0; 1740 data->ni = ni; 1741 1742 wh = mtod(m0, struct ieee80211_frame *); 1743 1744 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1745 flags |= RT2560_TX_ACK; 1746 1747 dur = rt2560_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1748 RAL_SIFS; 1749 *(uint16_t *)wh->i_dur = htole16(dur); 1750 1751 /* tell hardware to add timestamp for probe responses */ 1752 if ((wh->i_fc[0] & 1753 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1754 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1755 flags |= RT2560_TX_TIMESTAMP; 1756 } 1757 1758 rt2560_setup_tx_desc(sc, desc, flags, m0->m_pkthdr.len, rate, 0, 1759 data->map->dm_segs->ds_addr); 1760 1761 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 1762 BUS_DMASYNC_PREWRITE); 1763 bus_dmamap_sync(sc->sc_dmat, sc->prioq.map, 1764 sc->prioq.cur * RT2560_TX_DESC_SIZE, RT2560_TX_DESC_SIZE, 1765 BUS_DMASYNC_PREWRITE); 1766 1767 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1768 m0->m_pkthdr.len, sc->prioq.cur, rate)); 1769 1770 /* kick prio */ 1771 sc->prioq.queued++; 1772 sc->prioq.cur = (sc->prioq.cur + 1) % RT2560_PRIO_RING_COUNT; 1773 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_PRIO); 1774 1775 return 0; 1776} 1777 1778/* 1779 * Build a RTS control frame. 1780 */ 1781struct mbuf * 1782rt2560_get_rts(struct rt2560_softc *sc, struct ieee80211_frame *wh, 1783 uint16_t dur) 1784{ 1785 struct ieee80211_frame_rts *rts; 1786 struct mbuf *m; 1787 1788 MGETHDR(m, M_DONTWAIT, MT_DATA); 1789 if (m == NULL) { 1790 sc->sc_ic.ic_stats.is_tx_nombuf++; 1791 printf("%s: could not allocate RTS frame\n", 1792 sc->sc_dev.dv_xname); 1793 return NULL; 1794 } 1795 1796 rts = mtod(m, struct ieee80211_frame_rts *); 1797 1798 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1799 IEEE80211_FC0_SUBTYPE_RTS; 1800 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1801 *(uint16_t *)rts->i_dur = htole16(dur); 1802 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1803 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1804 1805 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1806 1807 return m; 1808} 1809 1810int 1811rt2560_tx_data(struct rt2560_softc *sc, struct mbuf *m0, 1812 struct ieee80211_node *ni) 1813{ 1814 struct ieee80211com *ic = &sc->sc_ic; 1815 struct ifnet *ifp = &ic->ic_if; 1816 struct rt2560_tx_desc *desc; 1817 struct rt2560_tx_data *data; 1818 struct rt2560_node *rn; 1819 struct ieee80211_rateset *rs; 1820 struct ieee80211_frame *wh; 1821 struct mbuf *mnew; 1822 uint16_t dur; 1823 uint32_t flags = 0; 1824 int rate, error; 1825 1826 wh = mtod(m0, struct ieee80211_frame *); 1827 1828 /* XXX this should be reworked! */ 1829 if (ic->ic_fixed_rate != -1) { 1830 if (ic->ic_curmode != IEEE80211_MODE_AUTO) 1831 rs = &ic->ic_sup_rates[ic->ic_curmode]; 1832 else 1833 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 1834 1835 rate = rs->rs_rates[ic->ic_fixed_rate]; 1836 } else { 1837 rs = &ni->ni_rates; 1838 rn = (struct rt2560_node *)ni; 1839 ni->ni_txrate = ieee80211_rssadapt_choose(&rn->rssadapt, rs, 1840 wh, m0->m_pkthdr.len, -1, NULL, 0); 1841 rate = rs->rs_rates[ni->ni_txrate]; 1842 } 1843 rate &= IEEE80211_RATE_VAL; 1844 1845 /* assert tx rate is non-null so we don't end up dividing by zero */ 1846 KASSERT(rate != 0); 1847 1848 if (ic->ic_flags & IEEE80211_F_WEPON) { 1849 m0 = ieee80211_wep_crypt(ifp, m0, 1); 1850 if (m0 == NULL) 1851 return ENOBUFS; 1852 1853 /* packet header may have moved, reset our local pointer */ 1854 wh = mtod(m0, struct ieee80211_frame *); 1855 } 1856 1857 /* 1858 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1859 * for directed frames only when the length of the MPDU is greater 1860 * than the length threshold indicated by [...]" ic_rtsthreshold. 1861 */ 1862 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1863 m0->m_pkthdr.len > ic->ic_rtsthreshold) { 1864 struct mbuf *m; 1865 uint16_t dur; 1866 int rtsrate, ackrate; 1867 1868 rtsrate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 2; 1869 ackrate = rt2560_ack_rate(ic, rate); 1870 1871 dur = rt2560_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1872 rt2560_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1873 rt2560_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1874 3 * RAL_SIFS; 1875 1876 m = rt2560_get_rts(sc, wh, dur); 1877 1878 desc = &sc->txq.desc[sc->txq.cur_encrypt]; 1879 data = &sc->txq.data[sc->txq.cur_encrypt]; 1880 1881 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1882 BUS_DMA_NOWAIT); 1883 if (error != 0) { 1884 printf("%s: could not map mbuf (error %d)\n", 1885 sc->sc_dev.dv_xname, error); 1886 m_freem(m); 1887 m_freem(m0); 1888 return error; 1889 } 1890 1891 /* avoid multiple free() of the same node for each fragment */ 1892 ieee80211_ref_node(ni); 1893 1894 data->m = m; 1895 data->ni = ni; 1896 1897 /* RTS frames are not taken into account for rssadapt */ 1898 data->id.id_node = NULL; 1899 1900 rt2560_setup_tx_desc(sc, desc, RT2560_TX_ACK | 1901 RT2560_TX_MORE_FRAG, m->m_pkthdr.len, rtsrate, 1, 1902 data->map->dm_segs->ds_addr); 1903 1904 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1905 data->map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1906 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 1907 sc->txq.cur_encrypt * RT2560_TX_DESC_SIZE, 1908 RT2560_TX_DESC_SIZE, BUS_DMASYNC_PREWRITE); 1909 1910 sc->txq.queued++; 1911 sc->txq.cur_encrypt = 1912 (sc->txq.cur_encrypt + 1) % RT2560_TX_RING_COUNT; 1913 1914 /* 1915 * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the 1916 * asynchronous data frame shall be transmitted after the CTS 1917 * frame and a SIFS period. 1918 */ 1919 flags |= RT2560_TX_LONG_RETRY | RT2560_TX_IFS_SIFS; 1920 } 1921 1922 data = &sc->txq.data[sc->txq.cur_encrypt]; 1923 desc = &sc->txq.desc[sc->txq.cur_encrypt]; 1924 1925 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1926 BUS_DMA_NOWAIT); 1927 if (error != 0 && error != EFBIG) { 1928 printf("%s: could not map mbuf (error %d)\n", 1929 sc->sc_dev.dv_xname, error); 1930 m_freem(m0); 1931 return error; 1932 } 1933 if (error != 0) { 1934 /* too many fragments, linearize */ 1935 1936 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1937 if (mnew == NULL) { 1938 m_freem(m0); 1939 return ENOMEM; 1940 } 1941 1942 M_DUP_PKTHDR(mnew, m0); 1943 if (m0->m_pkthdr.len > MHLEN) { 1944 MCLGET(mnew, M_DONTWAIT); 1945 if (!(mnew->m_flags & M_EXT)) { 1946 m_freem(m0); 1947 m_freem(mnew); 1948 return ENOMEM; 1949 } 1950 } 1951 1952 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, caddr_t)); 1953 m_freem(m0); 1954 mnew->m_len = mnew->m_pkthdr.len; 1955 m0 = mnew; 1956 1957 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m0, 1958 BUS_DMA_NOWAIT); 1959 if (error != 0) { 1960 printf("%s: could not map mbuf (error %d)\n", 1961 sc->sc_dev.dv_xname, error); 1962 m_freem(m0); 1963 return error; 1964 } 1965 1966 /* packet header have moved, reset our local pointer */ 1967 wh = mtod(m0, struct ieee80211_frame *); 1968 } 1969 1970#if NBPFILTER > 0 1971 if (sc->sc_drvbpf != NULL) { 1972 struct mbuf mb; 1973 struct rt2560_tx_radiotap_header *tap = &sc->sc_txtap; 1974 1975 tap->wt_flags = 0; 1976 tap->wt_rate = rate; 1977 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1978 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1979 tap->wt_antenna = sc->tx_ant; 1980 1981 M_DUP_PKTHDR(&mb, m0); 1982 mb.m_data = (caddr_t)tap; 1983 mb.m_len = sc->sc_txtap_len; 1984 mb.m_next = m0; 1985 mb.m_pkthdr.len += mb.m_len; 1986 bpf_mtap(sc->sc_drvbpf, &mb); 1987 } 1988#endif 1989 1990 data->m = m0; 1991 data->ni = ni; 1992 1993 /* remember link conditions for rate adaptation algorithm */ 1994 if (ic->ic_fixed_rate == -1) { 1995 data->id.id_len = m0->m_pkthdr.len; 1996 data->id.id_rateidx = ni->ni_txrate; 1997 data->id.id_node = ni; 1998 data->id.id_rssi = ni->ni_rssi; 1999 } else 2000 data->id.id_node = NULL; 2001 2002 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2003 flags |= RT2560_TX_ACK; 2004 2005 dur = rt2560_txtime(RAL_ACK_SIZE, rt2560_ack_rate(ic, rate), 2006 ic->ic_flags) + RAL_SIFS; 2007 *(uint16_t *)wh->i_dur = htole16(dur); 2008 } 2009 2010 rt2560_setup_tx_desc(sc, desc, flags, m0->m_pkthdr.len, rate, 1, 2011 data->map->dm_segs->ds_addr); 2012 2013 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2014 BUS_DMASYNC_PREWRITE); 2015 bus_dmamap_sync(sc->sc_dmat, sc->txq.map, 2016 sc->txq.cur_encrypt * RT2560_TX_DESC_SIZE, RT2560_TX_DESC_SIZE, 2017 BUS_DMASYNC_PREWRITE); 2018 2019 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 2020 m0->m_pkthdr.len, sc->txq.cur_encrypt, rate)); 2021 2022 /* kick encrypt */ 2023 sc->txq.queued++; 2024 sc->txq.cur_encrypt = (sc->txq.cur_encrypt + 1) % RT2560_TX_RING_COUNT; 2025 RAL_WRITE(sc, RT2560_SECCSR1, RT2560_KICK_ENCRYPT); 2026 2027 return 0; 2028} 2029 2030void 2031rt2560_start(struct ifnet *ifp) 2032{ 2033 struct rt2560_softc *sc = ifp->if_softc; 2034 struct ieee80211com *ic = &sc->sc_ic; 2035 struct mbuf *m0; 2036 struct ieee80211_node *ni; 2037 2038 for (;;) { 2039 IF_POLL(&ic->ic_mgtq, m0); 2040 if (m0 != NULL) { 2041 if (sc->prioq.queued >= RT2560_PRIO_RING_COUNT) { 2042 ifp->if_flags |= IFF_OACTIVE; 2043 break; 2044 } 2045 IF_DEQUEUE(&ic->ic_mgtq, m0); 2046 2047 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 2048 m0->m_pkthdr.rcvif = NULL; 2049#if NBPFILTER > 0 2050 if (ic->ic_rawbpf != NULL) 2051 bpf_mtap(ic->ic_rawbpf, m0); 2052#endif 2053 if (rt2560_tx_mgt(sc, m0, ni) != 0) 2054 break; 2055 2056 } else { 2057 if (ic->ic_state != IEEE80211_S_RUN) 2058 break; 2059 IFQ_DEQUEUE(&ifp->if_snd, m0); 2060 if (m0 == NULL) 2061 break; 2062 if (sc->txq.queued >= RT2560_TX_RING_COUNT - 1) { 2063 IF_PREPEND(&ifp->if_snd, m0); 2064 ifp->if_flags |= IFF_OACTIVE; 2065 break; 2066 } 2067#if NBPFILTER > 0 2068 if (ifp->if_bpf != NULL) 2069 bpf_mtap(ifp->if_bpf, m0); 2070#endif 2071 m0 = ieee80211_encap(ifp, m0, &ni); 2072 if (m0 == NULL) 2073 continue; 2074#if NBPFILTER > 0 2075 if (ic->ic_rawbpf != NULL) 2076 bpf_mtap(ic->ic_rawbpf, m0); 2077#endif 2078 if (rt2560_tx_data(sc, m0, ni) != 0) { 2079 if (ni != NULL) 2080 ieee80211_release_node(ic, ni); 2081 ifp->if_oerrors++; 2082 break; 2083 } 2084 } 2085 2086 sc->sc_tx_timer = 5; 2087 ifp->if_timer = 1; 2088 } 2089} 2090 2091void 2092rt2560_watchdog(struct ifnet *ifp) 2093{ 2094 struct rt2560_softc *sc = ifp->if_softc; 2095 2096 ifp->if_timer = 0; 2097 2098 if (sc->sc_tx_timer > 0) { 2099 if (--sc->sc_tx_timer == 0) { 2100 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2101 rt2560_init(ifp); 2102 ifp->if_oerrors++; 2103 return; 2104 } 2105 ifp->if_timer = 1; 2106 } 2107 2108 ieee80211_watchdog(ifp); 2109} 2110 2111int 2112rt2560_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2113{ 2114 struct rt2560_softc *sc = ifp->if_softc; 2115 struct ieee80211com *ic = &sc->sc_ic; 2116 struct ifaddr *ifa; 2117 struct ifreq *ifr; 2118 int s, error = 0; 2119 2120 s = splnet(); 2121 2122 switch (cmd) { 2123 case SIOCSIFADDR: 2124 ifa = (struct ifaddr *)data; 2125 ifp->if_flags |= IFF_UP; 2126#ifdef INET 2127 if (ifa->ifa_addr->sa_family == AF_INET) 2128 arp_ifinit(&ic->ic_ac, ifa); 2129#endif 2130 /* FALLTHROUGH */ 2131 case SIOCSIFFLAGS: 2132 if (ifp->if_flags & IFF_UP) { 2133 if (ifp->if_flags & IFF_RUNNING) 2134 rt2560_update_promisc(sc); 2135 else 2136 rt2560_init(ifp); 2137 } else { 2138 if (ifp->if_flags & IFF_RUNNING) 2139 rt2560_stop(ifp, 1); 2140 } 2141 break; 2142 2143 case SIOCADDMULTI: 2144 case SIOCDELMULTI: 2145 ifr = (struct ifreq *)data; 2146 error = (cmd == SIOCADDMULTI) ? 2147 ether_addmulti(ifr, &ic->ic_ac) : 2148 ether_delmulti(ifr, &ic->ic_ac); 2149 2150 if (error == ENETRESET) 2151 error = 0; 2152 break; 2153 2154 case SIOCS80211CHANNEL: 2155 /* 2156 * This allows for fast channel switching in monitor mode 2157 * (used by kismet). In IBSS mode, we must explicitly reset 2158 * the interface to generate a new beacon frame. 2159 */ 2160 error = ieee80211_ioctl(ifp, cmd, data); 2161 if (error == ENETRESET && 2162 ic->ic_opmode == IEEE80211_M_MONITOR) { 2163 rt2560_set_chan(sc, ic->ic_ibss_chan); 2164 error = 0; 2165 } 2166 break; 2167 2168 default: 2169 error = ieee80211_ioctl(ifp, cmd, data); 2170 } 2171 2172 if (error == ENETRESET) { 2173 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2174 (IFF_UP | IFF_RUNNING)) 2175 rt2560_init(ifp); 2176 error = 0; 2177 } 2178 2179 splx(s); 2180 2181 return error; 2182} 2183 2184void 2185rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val) 2186{ 2187 uint32_t tmp; 2188 int ntries; 2189 2190 for (ntries = 0; ntries < 100; ntries++) { 2191 if (!(RAL_READ(sc, RT2560_BBPCSR) & RT2560_BBP_BUSY)) 2192 break; 2193 DELAY(1); 2194 } 2195 if (ntries == 100) { 2196 printf("%s: could not write to BBP\n", sc->sc_dev.dv_xname); 2197 return; 2198 } 2199 2200 tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val; 2201 RAL_WRITE(sc, RT2560_BBPCSR, tmp); 2202 2203 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 2204} 2205 2206uint8_t 2207rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg) 2208{ 2209 uint32_t val; 2210 int ntries; 2211 2212 val = RT2560_BBP_BUSY | reg << 8; 2213 RAL_WRITE(sc, RT2560_BBPCSR, val); 2214 2215 for (ntries = 0; ntries < 100; ntries++) { 2216 val = RAL_READ(sc, RT2560_BBPCSR); 2217 if (!(val & RT2560_BBP_BUSY)) 2218 return val & 0xff; 2219 DELAY(1); 2220 } 2221 2222 printf("%s: could not read from BBP\n", sc->sc_dev.dv_xname); 2223 return 0; 2224} 2225 2226void 2227rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val) 2228{ 2229 uint32_t tmp; 2230 int ntries; 2231 2232 for (ntries = 0; ntries < 100; ntries++) { 2233 if (!(RAL_READ(sc, RT2560_RFCSR) & RT2560_RF_BUSY)) 2234 break; 2235 DELAY(1); 2236 } 2237 if (ntries == 100) { 2238 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname); 2239 return; 2240 } 2241 2242 tmp = RT2560_RF_BUSY | RT2560_RF_20BIT | (val & 0xfffff) << 2 | 2243 (reg & 0x3); 2244 RAL_WRITE(sc, RT2560_RFCSR, tmp); 2245 2246 /* remember last written value in sc */ 2247 sc->rf_regs[reg] = val; 2248 2249 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff)); 2250} 2251 2252void 2253rt2560_set_chan(struct rt2560_softc *sc, struct ieee80211_channel *c) 2254{ 2255#define N(a) (sizeof (a) / sizeof ((a)[0])) 2256 struct ieee80211com *ic = &sc->sc_ic; 2257 uint8_t power, tmp; 2258 u_int i, chan; 2259 2260 chan = ieee80211_chan2ieee(ic, c); 2261 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2262 return; 2263 2264 if (IEEE80211_IS_CHAN_2GHZ(c)) 2265 power = min(sc->txpow[chan - 1], 31); 2266 else 2267 power = 31; 2268 2269 DPRINTFN(2, ("setting channel to %u, txpower to %u\n", chan, power)); 2270 2271 switch (sc->rf_rev) { 2272 case RT2560_RF_2522: 2273 rt2560_rf_write(sc, RT2560_RF1, 0x00814); 2274 rt2560_rf_write(sc, RT2560_RF2, rt2560_rf2522_r2[chan - 1]); 2275 rt2560_rf_write(sc, RT2560_RF3, power << 7 | 0x00040); 2276 break; 2277 2278 case RT2560_RF_2523: 2279 rt2560_rf_write(sc, RT2560_RF1, 0x08804); 2280 rt2560_rf_write(sc, RT2560_RF2, rt2560_rf2523_r2[chan - 1]); 2281 rt2560_rf_write(sc, RT2560_RF3, power << 7 | 0x38044); 2282 rt2560_rf_write(sc, RT2560_RF4, 2283 (chan == 14) ? 0x00280 : 0x00286); 2284 break; 2285 2286 case RT2560_RF_2524: 2287 rt2560_rf_write(sc, RT2560_RF1, 0x0c808); 2288 rt2560_rf_write(sc, RT2560_RF2, rt2560_rf2524_r2[chan - 1]); 2289 rt2560_rf_write(sc, RT2560_RF3, power << 7 | 0x00040); 2290 rt2560_rf_write(sc, RT2560_RF4, 2291 (chan == 14) ? 0x00280 : 0x00286); 2292 break; 2293 2294 case RT2560_RF_2525: 2295 rt2560_rf_write(sc, RT2560_RF1, 0x08808); 2296 rt2560_rf_write(sc, RT2560_RF2, rt2560_rf2525_hi_r2[chan - 1]); 2297 rt2560_rf_write(sc, RT2560_RF3, power << 7 | 0x18044); 2298 rt2560_rf_write(sc, RT2560_RF4, 2299 (chan == 14) ? 0x00280 : 0x00286); 2300 2301 rt2560_rf_write(sc, RT2560_RF1, 0x08808); 2302 rt2560_rf_write(sc, RT2560_RF2, rt2560_rf2525_r2[chan - 1]); 2303 rt2560_rf_write(sc, RT2560_RF3, power << 7 | 0x18044); 2304 rt2560_rf_write(sc, RT2560_RF4, 2305 (chan == 14) ? 0x00280 : 0x00286); 2306 break; 2307 2308 case RT2560_RF_2525E: 2309 rt2560_rf_write(sc, RT2560_RF1, 0x08808); 2310 rt2560_rf_write(sc, RT2560_RF2, rt2560_rf2525e_r2[chan - 1]); 2311 rt2560_rf_write(sc, RT2560_RF3, power << 7 | 0x18044); 2312 rt2560_rf_write(sc, RT2560_RF4, 2313 (chan == 14) ? 0x00286 : 0x00282); 2314 break; 2315 2316 case RT2560_RF_2526: 2317 rt2560_rf_write(sc, RT2560_RF2, rt2560_rf2526_hi_r2[chan - 1]); 2318 rt2560_rf_write(sc, RT2560_RF4, 2319 (chan & 1) ? 0x00386 : 0x00381); 2320 rt2560_rf_write(sc, RT2560_RF1, 0x08804); 2321 2322 rt2560_rf_write(sc, RT2560_RF2, rt2560_rf2526_r2[chan - 1]); 2323 rt2560_rf_write(sc, RT2560_RF3, power << 7 | 0x18044); 2324 rt2560_rf_write(sc, RT2560_RF4, 2325 (chan & 1) ? 0x00386 : 0x00381); 2326 break; 2327 2328 /* dual-band RF */ 2329 case RT2560_RF_5222: 2330 for (i = 0; i < N(rt2560_rf5222); i++) 2331 if (rt2560_rf5222[i].chan == chan) 2332 break; 2333 2334 if (i < N(rt2560_rf5222)) { 2335 rt2560_rf_write(sc, RT2560_RF1, rt2560_rf5222[i].r1); 2336 rt2560_rf_write(sc, RT2560_RF2, rt2560_rf5222[i].r2); 2337 rt2560_rf_write(sc, RT2560_RF3, power << 7 | 0x00040); 2338 rt2560_rf_write(sc, RT2560_RF4, rt2560_rf5222[i].r4); 2339 } 2340 break; 2341 } 2342 2343 if (ic->ic_opmode != IEEE80211_M_MONITOR && 2344 ic->ic_state != IEEE80211_S_SCAN) { 2345 /* set Japan filter bit for channel 14 */ 2346 tmp = rt2560_bbp_read(sc, 70); 2347 2348 tmp &= ~RT2560_JAPAN_FILTER; 2349 if (chan == 14) 2350 tmp |= RT2560_JAPAN_FILTER; 2351 2352 rt2560_bbp_write(sc, 70, tmp); 2353 2354 DELAY(1000); /* RF needs a 1ms delay here */ 2355 rt2560_disable_rf_tune(sc); 2356 2357 /* clear CRC errors */ 2358 RAL_READ(sc, RT2560_CNT0); 2359 } 2360#undef N 2361} 2362 2363/* 2364 * Disable RF auto-tuning. 2365 */ 2366void 2367rt2560_disable_rf_tune(struct rt2560_softc *sc) 2368{ 2369 uint32_t tmp; 2370 2371 if (sc->rf_rev != RT2560_RF_2523) { 2372 tmp = sc->rf_regs[RT2560_RF1] & ~RT2560_RF1_AUTOTUNE; 2373 rt2560_rf_write(sc, RT2560_RF1, tmp); 2374 } 2375 2376 tmp = sc->rf_regs[RT2560_RF3] & ~RT2560_RF3_AUTOTUNE; 2377 rt2560_rf_write(sc, RT2560_RF3, tmp); 2378 2379 DPRINTFN(2, ("disabling RF autotune\n")); 2380} 2381 2382/* 2383 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 2384 * synchronization. 2385 */ 2386void 2387rt2560_enable_tsf_sync(struct rt2560_softc *sc) 2388{ 2389 struct ieee80211com *ic = &sc->sc_ic; 2390 uint16_t logcwmin, preload; 2391 uint32_t tmp; 2392 2393 /* first, disable TSF synchronization */ 2394 RAL_WRITE(sc, RT2560_CSR14, 0); 2395 2396 tmp = 16 * ic->ic_bss->ni_intval; 2397 RAL_WRITE(sc, RT2560_CSR12, tmp); 2398 2399 RAL_WRITE(sc, RT2560_CSR13, 0); 2400 2401 logcwmin = 5; 2402 preload = (ic->ic_opmode == IEEE80211_M_STA) ? 384 : 1024; 2403 tmp = logcwmin << 16 | preload; 2404 RAL_WRITE(sc, RT2560_BCNOCSR, tmp); 2405 2406 /* finally, enable TSF synchronization */ 2407 tmp = RT2560_ENABLE_TSF | RT2560_ENABLE_TBCN; 2408 if (ic->ic_opmode == IEEE80211_M_STA) 2409 tmp |= RT2560_ENABLE_TSF_SYNC(1); 2410 else 2411 tmp |= RT2560_ENABLE_TSF_SYNC(2) | 2412 RT2560_ENABLE_BEACON_GENERATOR; 2413 RAL_WRITE(sc, RT2560_CSR14, tmp); 2414 2415 DPRINTF(("enabling TSF synchronization\n")); 2416} 2417 2418void 2419rt2560_update_plcp(struct rt2560_softc *sc) 2420{ 2421 struct ieee80211com *ic = &sc->sc_ic; 2422 2423 /* no short preamble for 1Mbps */ 2424 RAL_WRITE(sc, RT2560_PLCP1MCSR, 0x00700400); 2425 2426 if (!(ic->ic_flags & IEEE80211_F_SHPREAMBLE)) { 2427 /* values taken from the reference driver */ 2428 RAL_WRITE(sc, RT2560_PLCP2MCSR, 0x00380401); 2429 RAL_WRITE(sc, RT2560_PLCP5p5MCSR, 0x00150402); 2430 RAL_WRITE(sc, RT2560_PLCP11MCSR, 0x000b8403); 2431 } else { 2432 /* same values as above or'ed 0x8 */ 2433 RAL_WRITE(sc, RT2560_PLCP2MCSR, 0x00380409); 2434 RAL_WRITE(sc, RT2560_PLCP5p5MCSR, 0x0015040a); 2435 RAL_WRITE(sc, RT2560_PLCP11MCSR, 0x000b840b); 2436 } 2437 2438 DPRINTF(("updating PLCP for %s preamble\n", 2439 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ? "short" : "long")); 2440} 2441 2442/* 2443 * IEEE 802.11a uses short slot time. Refer to IEEE Std 802.11-1999 pp. 85 to 2444 * know how these values are computed. 2445 */ 2446void 2447rt2560_update_slot(struct rt2560_softc *sc) 2448{ 2449 struct ieee80211com *ic = &sc->sc_ic; 2450 uint8_t slottime; 2451 uint16_t sifs, pifs, difs, eifs; 2452 uint32_t tmp; 2453 2454 slottime = (ic->ic_curmode == IEEE80211_MODE_11A) ? 9 : 20; 2455 2456 /* define the MAC slot boundaries */ 2457 sifs = RAL_SIFS - RT2560_RXTX_TURNAROUND; 2458 pifs = sifs + slottime; 2459 difs = sifs + 2 * slottime; 2460 eifs = (ic->ic_curmode == IEEE80211_MODE_11B) ? 364 : 60; 2461 2462 tmp = RAL_READ(sc, RT2560_CSR11); 2463 tmp = (tmp & ~0x1f00) | slottime << 8; 2464 RAL_WRITE(sc, RT2560_CSR11, tmp); 2465 2466 tmp = pifs << 16 | sifs; 2467 RAL_WRITE(sc, RT2560_CSR18, tmp); 2468 2469 tmp = eifs << 16 | difs; 2470 RAL_WRITE(sc, RT2560_CSR19, tmp); 2471 2472 DPRINTF(("setting slottime to %uus\n", slottime)); 2473} 2474 2475void 2476rt2560_update_led(struct rt2560_softc *sc, int led1, int led2) 2477{ 2478 uint32_t tmp; 2479 2480 /* set ON period to 70ms and OFF period to 30ms */ 2481 tmp = led1 << 16 | led2 << 17 | 70 << 8 | 30; 2482 RAL_WRITE(sc, RT2560_LEDCSR, tmp); 2483} 2484 2485void 2486rt2560_set_bssid(struct rt2560_softc *sc, uint8_t *bssid) 2487{ 2488 uint32_t tmp; 2489 2490 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2491 RAL_WRITE(sc, RT2560_CSR5, tmp); 2492 2493 tmp = bssid[4] | bssid[5] << 8; 2494 RAL_WRITE(sc, RT2560_CSR6, tmp); 2495 2496 DPRINTF(("setting BSSID to %s\n", ether_sprintf(bssid))); 2497} 2498 2499void 2500rt2560_set_macaddr(struct rt2560_softc *sc, uint8_t *addr) 2501{ 2502 uint32_t tmp; 2503 2504 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2505 RAL_WRITE(sc, RT2560_CSR3, tmp); 2506 2507 tmp = addr[4] | addr[5] << 8; 2508 RAL_WRITE(sc, RT2560_CSR4, tmp); 2509 2510 DPRINTF(("setting MAC address to %s\n", ether_sprintf(addr))); 2511} 2512 2513void 2514rt2560_get_macaddr(struct rt2560_softc *sc, uint8_t *addr) 2515{ 2516 uint32_t tmp; 2517 2518 tmp = RAL_READ(sc, RT2560_CSR3); 2519 addr[0] = tmp & 0xff; 2520 addr[1] = (tmp >> 8) & 0xff; 2521 addr[2] = (tmp >> 16) & 0xff; 2522 addr[3] = (tmp >> 24); 2523 2524 tmp = RAL_READ(sc, RT2560_CSR4); 2525 addr[4] = tmp & 0xff; 2526 addr[5] = (tmp >> 8) & 0xff; 2527} 2528 2529void 2530rt2560_update_promisc(struct rt2560_softc *sc) 2531{ 2532 struct ifnet *ifp = &sc->sc_ic.ic_if; 2533 uint32_t tmp; 2534 2535 tmp = RAL_READ(sc, RT2560_RXCSR0); 2536 2537 tmp &= ~RT2560_DROP_NOT_TO_ME; 2538 if (!(ifp->if_flags & IFF_PROMISC)) 2539 tmp |= RT2560_DROP_NOT_TO_ME; 2540 2541 RAL_WRITE(sc, RT2560_RXCSR0, tmp); 2542 2543 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2544 "entering" : "leaving")); 2545} 2546 2547void 2548rt2560_set_txantenna(struct rt2560_softc *sc, int antenna) 2549{ 2550 uint32_t tmp; 2551 uint8_t tx; 2552 2553 tx = rt2560_bbp_read(sc, RT2560_BBP_TX) & ~RT2560_BBP_ANTMASK; 2554 if (antenna == 1) 2555 tx |= RT2560_BBP_ANTA; 2556 else if (antenna == 2) 2557 tx |= RT2560_BBP_ANTB; 2558 else 2559 tx |= RT2560_BBP_DIVERSITY; 2560 2561 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 2562 if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526 || 2563 sc->rf_rev == RT2560_RF_5222) 2564 tx |= RT2560_BBP_FLIPIQ; 2565 2566 rt2560_bbp_write(sc, RT2560_BBP_TX, tx); 2567 2568 /* update values for CCK and OFDM in BBPCSR1 */ 2569 tmp = RAL_READ(sc, RT2560_BBPCSR1) & ~0x00070007; 2570 tmp |= (tx & 0x7) << 16 | (tx & 0x7); 2571 RAL_WRITE(sc, RT2560_BBPCSR1, tmp); 2572} 2573 2574void 2575rt2560_set_rxantenna(struct rt2560_softc *sc, int antenna) 2576{ 2577 uint8_t rx; 2578 2579 rx = rt2560_bbp_read(sc, RT2560_BBP_RX) & ~RT2560_BBP_ANTMASK; 2580 if (antenna == 1) 2581 rx |= RT2560_BBP_ANTA; 2582 else if (antenna == 2) 2583 rx |= RT2560_BBP_ANTB; 2584 else 2585 rx |= RT2560_BBP_DIVERSITY; 2586 2587 /* need to force no I/Q flip for RF 2525e and 2526 */ 2588 if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526) 2589 rx &= ~RT2560_BBP_FLIPIQ; 2590 2591 rt2560_bbp_write(sc, RT2560_BBP_RX, rx); 2592} 2593 2594const char * 2595rt2560_get_rf(int rev) 2596{ 2597 switch (rev) { 2598 case RT2560_RF_2522: return "RT2522"; 2599 case RT2560_RF_2523: return "RT2523"; 2600 case RT2560_RF_2524: return "RT2524"; 2601 case RT2560_RF_2525: return "RT2525"; 2602 case RT2560_RF_2525E: return "RT2525e"; 2603 case RT2560_RF_2526: return "RT2526"; 2604 case RT2560_RF_5222: return "RT5222"; 2605 default: return "unknown"; 2606 } 2607} 2608 2609void 2610rt2560_read_eeprom(struct rt2560_softc *sc) 2611{ 2612 uint16_t val; 2613 int i; 2614 2615 val = rt2560_eeprom_read(sc, RT2560_EEPROM_CONFIG0); 2616 sc->rf_rev = (val >> 11) & 0x1f; 2617 sc->hw_radio = (val >> 10) & 0x1; 2618 sc->led_mode = (val >> 6) & 0x7; 2619 sc->rx_ant = (val >> 4) & 0x3; 2620 sc->tx_ant = (val >> 2) & 0x3; 2621 sc->nb_ant = val & 0x3; 2622 2623 /* read default values for BBP registers */ 2624 for (i = 0; i < 16; i++) { 2625 val = rt2560_eeprom_read(sc, RT2560_EEPROM_BBP_BASE + i); 2626 sc->bbp_prom[i].reg = val >> 8; 2627 sc->bbp_prom[i].val = val & 0xff; 2628 } 2629 2630 /* read Tx power for all b/g channels */ 2631 for (i = 0; i < 14 / 2; i++) { 2632 val = rt2560_eeprom_read(sc, RT2560_EEPROM_TXPOWER + i); 2633 sc->txpow[i * 2] = val >> 8; 2634 sc->txpow[i * 2 + 1] = val & 0xff; 2635 } 2636} 2637 2638int 2639rt2560_bbp_init(struct rt2560_softc *sc) 2640{ 2641#define N(a) (sizeof (a) / sizeof ((a)[0])) 2642 int i, ntries; 2643 2644 /* wait for BBP to be ready */ 2645 for (ntries = 0; ntries < 100; ntries++) { 2646 if (rt2560_bbp_read(sc, RT2560_BBP_VERSION) != 0) 2647 break; 2648 DELAY(1); 2649 } 2650 if (ntries == 100) { 2651 printf("%s: timeout waiting for BBP\n", sc->sc_dev.dv_xname); 2652 return EIO; 2653 } 2654 2655 /* initialize BBP registers to default values */ 2656 for (i = 0; i < N(rt2560_def_bbp); i++) { 2657 rt2560_bbp_write(sc, rt2560_def_bbp[i].reg, 2658 rt2560_def_bbp[i].val); 2659 } 2660#if 0 2661 /* initialize BBP registers to values stored in EEPROM */ 2662 for (i = 0; i < 16; i++) { 2663 if (sc->bbp_prom[i].reg == 0xff) 2664 continue; 2665 rt2560_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2666 } 2667#endif 2668 2669 return 0; 2670#undef N 2671} 2672 2673int 2674rt2560_init(struct ifnet *ifp) 2675{ 2676#define N(a) (sizeof (a) / sizeof ((a)[0])) 2677 struct rt2560_softc *sc = ifp->if_softc; 2678 struct ieee80211com *ic = &sc->sc_ic; 2679 uint32_t tmp; 2680 int i; 2681 2682 /* for CardBus, power on the socket */ 2683 if (!(sc->sc_flags & RT2560_ENABLED)) { 2684 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 2685 printf("%s: could not enable device\n"); 2686 return EIO; 2687 } 2688 sc->sc_flags |= RT2560_ENABLED; 2689 } 2690 2691 rt2560_stop(ifp, 0); 2692 2693 /* setup tx rings */ 2694 tmp = RT2560_PRIO_RING_COUNT << 24 | 2695 RT2560_ATIM_RING_COUNT << 16 | 2696 RT2560_TX_RING_COUNT << 8 | 2697 RT2560_TX_DESC_SIZE; 2698 2699 /* rings _must_ be initialized in this _exact_ order! */ 2700 RAL_WRITE(sc, RT2560_TXCSR2, tmp); 2701 RAL_WRITE(sc, RT2560_TXCSR3, sc->txq.physaddr); 2702 RAL_WRITE(sc, RT2560_TXCSR5, sc->prioq.physaddr); 2703 RAL_WRITE(sc, RT2560_TXCSR4, sc->atimq.physaddr); 2704 RAL_WRITE(sc, RT2560_TXCSR6, sc->bcnq.physaddr); 2705 2706 /* setup rx ring */ 2707 tmp = RT2560_RX_RING_COUNT << 8 | RT2560_RX_DESC_SIZE; 2708 2709 RAL_WRITE(sc, RT2560_RXCSR1, tmp); 2710 RAL_WRITE(sc, RT2560_RXCSR2, sc->rxq.physaddr); 2711 2712 /* initialize MAC registers to default values */ 2713 for (i = 0; i < N(rt2560_def_mac); i++) 2714 RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val); 2715 2716 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2717 rt2560_set_macaddr(sc, ic->ic_myaddr); 2718 2719 /* set basic rate set (will be updated later) */ 2720 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x153); 2721 2722 rt2560_set_txantenna(sc, 1); 2723 rt2560_set_rxantenna(sc, 1); 2724 rt2560_update_slot(sc); 2725 rt2560_update_plcp(sc); 2726 rt2560_update_led(sc, 0, 0); 2727 2728 RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC); 2729 RAL_WRITE(sc, RT2560_CSR1, RT2560_HOST_READY); 2730 2731 if (rt2560_bbp_init(sc) != 0) { 2732 rt2560_stop(ifp, 1); 2733 return EIO; 2734 } 2735 2736 /* set default BSS channel */ 2737 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2738 rt2560_set_chan(sc, ic->ic_bss->ni_chan); 2739 2740 /* kick Rx */ 2741 tmp = RT2560_DROP_PHY_ERROR | RT2560_DROP_CRC_ERROR; 2742 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2743 tmp |= RT2560_DROP_CTL | RT2560_DROP_VERSION_ERROR; 2744 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2745 tmp |= RT2560_DROP_TODS; 2746 if (!(ifp->if_flags & IFF_PROMISC)) 2747 tmp |= RT2560_DROP_NOT_TO_ME; 2748 } 2749 RAL_WRITE(sc, RT2560_RXCSR0, tmp); 2750 2751 /* clear old FCS and Rx FIFO errors */ 2752 RAL_READ(sc, RT2560_CNT0); 2753 RAL_READ(sc, RT2560_CNT4); 2754 2755 /* clear any pending interrupts */ 2756 RAL_WRITE(sc, RT2560_CSR7, 0xffffffff); 2757 2758 /* enable interrupts */ 2759 RAL_WRITE(sc, RT2560_CSR8, RT2560_INTR_MASK); 2760 2761 ifp->if_flags &= ~IFF_OACTIVE; 2762 ifp->if_flags |= IFF_RUNNING; 2763 2764 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2765 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2766 else 2767 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2768 2769 return 0; 2770#undef N 2771} 2772 2773void 2774rt2560_stop(struct ifnet *ifp, int disable) 2775{ 2776 struct rt2560_softc *sc = ifp->if_softc; 2777 struct ieee80211com *ic = &sc->sc_ic; 2778 2779 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2780 2781 sc->sc_tx_timer = 0; 2782 ifp->if_timer = 0; 2783 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2784 2785 /* abort Tx */ 2786 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_ABORT_TX); 2787 2788 /* disable Rx */ 2789 RAL_WRITE(sc, RT2560_RXCSR0, RT2560_DISABLE_RX); 2790 2791 /* reset ASIC (and thus, BBP) */ 2792 RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC); 2793 RAL_WRITE(sc, RT2560_CSR1, 0); 2794 2795 /* disable interrupts */ 2796 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff); 2797 2798 /* reset Tx and Rx rings */ 2799 rt2560_reset_tx_ring(sc, &sc->txq); 2800 rt2560_reset_tx_ring(sc, &sc->atimq); 2801 rt2560_reset_tx_ring(sc, &sc->prioq); 2802 rt2560_reset_tx_ring(sc, &sc->bcnq); 2803 rt2560_reset_rx_ring(sc, &sc->rxq); 2804 2805 /* for CardBus, power down the socket */ 2806 if (disable && sc->sc_disable != NULL) { 2807 if (sc->sc_flags & RT2560_ENABLED) { 2808 (*sc->sc_disable)(sc); 2809 sc->sc_flags &= ~RT2560_ENABLED; 2810 } 2811 } 2812} 2813 2814struct cfdriver ral_cd = { 2815 0, "ral", DV_IFNET 2816}; 2817