1/*	$OpenBSD: qwzreg.h,v 1.6 2024/09/01 03:14:48 jsg Exp $	*/
2
3/*
4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc.
5 * Copyright (c) 2018-2021 The Linux Foundation.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted (subject to the limitations in the disclaimer
10 * below) provided that the following conditions are met:
11 *
12 *  * Redistributions of source code must retain the above copyright notice,
13 *    this list of conditions and the following disclaimer.
14 *
15 *  * Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 *  * Neither the name of [Owner Organization] nor the names of its
20 *    contributors may be used to endorse or promote products derived from
21 *    this software without specific prior written permission.
22 *
23 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY
24 * THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
25 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
26 * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
27 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
28 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * core.h
39 */
40
41#define ATH12K_TX_MGMT_NUM_PENDING_MAX	512
42
43#define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
44
45/* Pending management packets threshold for dropping probe responses */
46#define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
47
48#define ATH12K_INVALID_HW_MAC_ID	0xFF
49#define ATH12K_CONNECTION_LOSS_HZ	(3 * HZ)
50
51enum ath12k_hw_rev {
52	ATH12K_HW_QCN9274_HW10,
53	ATH12K_HW_QCN9274_HW20,
54	ATH12K_HW_WCN7850_HW20
55};
56
57enum ath12k_firmware_mode {
58	/* the default mode, standard 802.11 functionality */
59	ATH12K_FIRMWARE_MODE_NORMAL,
60
61	/* factory tests etc */
62	ATH12K_FIRMWARE_MODE_FTM,
63
64	/* Cold boot calibration */
65	ATH12K_FIRMWARE_MODE_COLD_BOOT = 7,
66};
67
68enum ath12k_crypt_mode {
69	/* Only use hardware crypto engine */
70	ATH12K_CRYPT_MODE_HW,
71	/* Only use software crypto */
72	ATH12K_CRYPT_MODE_SW,
73};
74
75/* IPQ8074 HW channel counters frequency value in hertz */
76#define IPQ8074_CC_FREQ_HERTZ 320000
77
78#define ATH12K_MIN_5G_FREQ 4150
79#define ATH12K_MIN_6G_FREQ 5925
80#define ATH12K_MAX_6G_FREQ 7115
81#define ATH12K_NUM_CHANS 102
82#define ATH12K_MAX_5G_CHAN 177
83
84/* Antenna noise floor */
85#define ATH12K_DEFAULT_NOISE_FLOOR -95
86
87/*
88 * wmi.h
89 */
90
91#define PSOC_HOST_MAX_NUM_SS (8)
92
93/* defines to set Packet extension values which can be 0 us, 8 usec or 16 usec */
94#define MAX_HE_NSS               8
95#define MAX_HE_MODULATION        8
96#define MAX_HE_RU                4
97#define HE_MODULATION_NONE       7
98#define HE_PET_0_USEC            0
99#define HE_PET_8_USEC            1
100#define HE_PET_16_USEC           2
101
102#define WMI_MAX_CHAINS		 8
103
104#define WMI_MAX_NUM_SS                    MAX_HE_NSS
105#define WMI_MAX_NUM_RU                    MAX_HE_RU
106
107#define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1)
108#define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1)
109#define WMI_TLV_CMD_UNSUPPORTED 0
110#define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0
111#define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0
112
113struct wmi_cmd_hdr {
114	uint32_t cmd_id;
115} __packed;
116
117struct wmi_tlv {
118	uint32_t header;
119	uint8_t value[];
120} __packed;
121
122#define WMI_TLV_LEN	GENMASK(15, 0)
123#define WMI_TLV_TAG	GENMASK(31, 16)
124#define TLV_HDR_SIZE	sizeof(uint32_t) /* wmi_tlv.header */
125
126#define WMI_CMD_HDR_CMD_ID      GENMASK(23, 0)
127#define WMI_MAX_MEM_REQS        32
128#define ATH12K_MAX_HW_LISTEN_INTERVAL 5
129
130#define WLAN_SCAN_MAX_HINT_S_SSID        10
131#define WLAN_SCAN_MAX_HINT_BSSID         10
132#define MAX_RNR_BSS                    5
133
134#define WLAN_SCAN_MAX_HINT_S_SSID        10
135#define WLAN_SCAN_MAX_HINT_BSSID         10
136#define MAX_RNR_BSS                    5
137
138#define WLAN_SCAN_PARAMS_MAX_SSID    16
139#define WLAN_SCAN_PARAMS_MAX_BSSID   4
140#define WLAN_SCAN_PARAMS_MAX_IE_LEN  256
141
142#define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1
143
144#define MAX_WMI_UTF_LEN 252
145#define WMI_BA_MODE_BUFFER_SIZE_256  3
146
147/*
148 * HW mode config type replicated from FW header
149 * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active.
150 * @WMI_HOST_HW_MODE_DBS: Both PHYs are active in different bands,
151 *                        one in 2G and another in 5G.
152 * @WMI_HOST_HW_MODE_SBS_PASSIVE: Both PHYs are in passive mode (only rx) in
153 *                        same band; no tx allowed.
154 * @WMI_HOST_HW_MODE_SBS: Both PHYs are active in the same band.
155 *                        Support for both PHYs within one band is planned
156 *                        for 5G only(as indicated in WMI_MAC_PHY_CAPABILITIES),
157 *                        but could be extended to other bands in the future.
158 *                        The separation of the band between the two PHYs needs
159 *                        to be communicated separately.
160 * @WMI_HOST_HW_MODE_DBS_SBS: 3 PHYs, with 2 on the same band doing SBS
161 *                           as in WMI_HW_MODE_SBS, and 3rd on the other band
162 * @WMI_HOST_HW_MODE_DBS_OR_SBS: Two PHY with one PHY capable of both 2G and
163 *                        5G. It can support SBS (5G + 5G) OR DBS (5G + 2G).
164 * @WMI_HOST_HW_MODE_MAX: Max hw_mode_id. Used to indicate invalid mode.
165 */
166enum wmi_host_hw_mode_config_type {
167	WMI_HOST_HW_MODE_SINGLE       = 0,
168	WMI_HOST_HW_MODE_DBS          = 1,
169	WMI_HOST_HW_MODE_SBS_PASSIVE  = 2,
170	WMI_HOST_HW_MODE_SBS          = 3,
171	WMI_HOST_HW_MODE_DBS_SBS      = 4,
172	WMI_HOST_HW_MODE_DBS_OR_SBS   = 5,
173
174	/* keep last */
175	WMI_HOST_HW_MODE_MAX
176};
177
178/* HW mode priority values used to detect the preferred HW mode
179 * on the available modes.
180 */
181enum wmi_host_hw_mode_priority {
182	WMI_HOST_HW_MODE_DBS_SBS_PRI,
183	WMI_HOST_HW_MODE_DBS_PRI,
184	WMI_HOST_HW_MODE_DBS_OR_SBS_PRI,
185	WMI_HOST_HW_MODE_SBS_PRI,
186	WMI_HOST_HW_MODE_SBS_PASSIVE_PRI,
187	WMI_HOST_HW_MODE_SINGLE_PRI,
188
189	/* keep last the lowest priority */
190	WMI_HOST_HW_MODE_MAX_PRI
191};
192
193enum WMI_HOST_WLAN_BAND {
194	WMI_HOST_WLAN_2G_CAP	= 0x1,
195	WMI_HOST_WLAN_5G_CAP	= 0x2,
196	WMI_HOST_WLAN_2G_5G_CAP	= WMI_HOST_WLAN_2G_CAP | WMI_HOST_WLAN_5G_CAP,
197};
198
199/* Parameters used for WMI_VDEV_PARAM_AUTORATE_MISC_CFG command.
200 * Used only for HE auto rate mode.
201 */
202enum {
203	/* HE LTF related configuration */
204	WMI_HE_AUTORATE_LTF_1X = BIT(0),
205	WMI_HE_AUTORATE_LTF_2X = BIT(1),
206	WMI_HE_AUTORATE_LTF_4X = BIT(2),
207
208	/* HE GI related configuration */
209	WMI_AUTORATE_400NS_GI = BIT(8),
210	WMI_AUTORATE_800NS_GI = BIT(9),
211	WMI_AUTORATE_1600NS_GI = BIT(10),
212	WMI_AUTORATE_3200NS_GI = BIT(11),
213};
214
215enum {
216	WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP       = 0x00000001,
217	WMI_HOST_VDEV_FLAGS_TRANSMIT_AP         = 0x00000002,
218	WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP     = 0x00000004,
219	WMI_HOST_VDEV_FLAGS_EMA_MODE            = 0x00000008,
220	WMI_HOST_VDEV_FLAGS_SCAN_MODE_VAP       = 0x00000010,
221};
222
223/*
224 * wmi command groups.
225 */
226enum wmi_cmd_group {
227	/* 0 to 2 are reserved */
228	WMI_GRP_START = 0x3,
229	WMI_GRP_SCAN = WMI_GRP_START,
230	WMI_GRP_PDEV		= 0x4,
231	WMI_GRP_VDEV           = 0x5,
232	WMI_GRP_PEER           = 0x6,
233	WMI_GRP_MGMT           = 0x7,
234	WMI_GRP_BA_NEG         = 0x8,
235	WMI_GRP_STA_PS         = 0x9,
236	WMI_GRP_DFS            = 0xa,
237	WMI_GRP_ROAM           = 0xb,
238	WMI_GRP_OFL_SCAN       = 0xc,
239	WMI_GRP_P2P            = 0xd,
240	WMI_GRP_AP_PS          = 0xe,
241	WMI_GRP_RATE_CTRL      = 0xf,
242	WMI_GRP_PROFILE        = 0x10,
243	WMI_GRP_SUSPEND        = 0x11,
244	WMI_GRP_BCN_FILTER     = 0x12,
245	WMI_GRP_WOW            = 0x13,
246	WMI_GRP_RTT            = 0x14,
247	WMI_GRP_SPECTRAL       = 0x15,
248	WMI_GRP_STATS          = 0x16,
249	WMI_GRP_ARP_NS_OFL     = 0x17,
250	WMI_GRP_NLO_OFL        = 0x18,
251	WMI_GRP_GTK_OFL        = 0x19,
252	WMI_GRP_CSA_OFL        = 0x1a,
253	WMI_GRP_CHATTER        = 0x1b,
254	WMI_GRP_TID_ADDBA      = 0x1c,
255	WMI_GRP_MISC           = 0x1d,
256	WMI_GRP_GPIO           = 0x1e,
257	WMI_GRP_FWTEST         = 0x1f,
258	WMI_GRP_TDLS           = 0x20,
259	WMI_GRP_RESMGR         = 0x21,
260	WMI_GRP_STA_SMPS       = 0x22,
261	WMI_GRP_WLAN_HB        = 0x23,
262	WMI_GRP_RMC            = 0x24,
263	WMI_GRP_MHF_OFL        = 0x25,
264	WMI_GRP_LOCATION_SCAN  = 0x26,
265	WMI_GRP_OEM            = 0x27,
266	WMI_GRP_NAN            = 0x28,
267	WMI_GRP_COEX           = 0x29,
268	WMI_GRP_OBSS_OFL       = 0x2a,
269	WMI_GRP_LPI            = 0x2b,
270	WMI_GRP_EXTSCAN        = 0x2c,
271	WMI_GRP_DHCP_OFL       = 0x2d,
272	WMI_GRP_IPA            = 0x2e,
273	WMI_GRP_MDNS_OFL       = 0x2f,
274	WMI_GRP_SAP_OFL        = 0x30,
275	WMI_GRP_OCB            = 0x31,
276	WMI_GRP_SOC            = 0x32,
277	WMI_GRP_PKT_FILTER     = 0x33,
278	WMI_GRP_MAWC           = 0x34,
279	WMI_GRP_PMF_OFFLOAD    = 0x35,
280	WMI_GRP_BPF_OFFLOAD    = 0x36,
281	WMI_GRP_NAN_DATA       = 0x37,
282	WMI_GRP_PROTOTYPE      = 0x38,
283	WMI_GRP_MONITOR        = 0x39,
284	WMI_GRP_REGULATORY     = 0x3a,
285	WMI_GRP_HW_DATA_FILTER = 0x3b,
286	WMI_GRP_WLM            = 0x3c,
287	WMI_GRP_11K_OFFLOAD    = 0x3d,
288	WMI_GRP_TWT            = 0x3e,
289	WMI_GRP_MOTION_DET     = 0x3f,
290	WMI_GRP_SPATIAL_REUSE  = 0x40,
291};
292
293
294#define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1)
295#define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1)
296
297#define WMI_CMD_UNSUPPORTED 0
298
299enum wmi_tlv_cmd_id {
300	WMI_INIT_CMDID = 0x1,
301	WMI_START_SCAN_CMDID = WMI_TLV_CMD(WMI_GRP_SCAN),
302	WMI_STOP_SCAN_CMDID,
303	WMI_SCAN_CHAN_LIST_CMDID,
304	WMI_SCAN_SCH_PRIO_TBL_CMDID,
305	WMI_SCAN_UPDATE_REQUEST_CMDID,
306	WMI_SCAN_PROB_REQ_OUI_CMDID,
307	WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID,
308	WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_TLV_CMD(WMI_GRP_PDEV),
309	WMI_PDEV_SET_CHANNEL_CMDID,
310	WMI_PDEV_SET_PARAM_CMDID,
311	WMI_PDEV_PKTLOG_ENABLE_CMDID,
312	WMI_PDEV_PKTLOG_DISABLE_CMDID,
313	WMI_PDEV_SET_WMM_PARAMS_CMDID,
314	WMI_PDEV_SET_HT_CAP_IE_CMDID,
315	WMI_PDEV_SET_VHT_CAP_IE_CMDID,
316	WMI_PDEV_SET_DSCP_TID_MAP_CMDID,
317	WMI_PDEV_SET_QUIET_MODE_CMDID,
318	WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID,
319	WMI_PDEV_GET_TPC_CONFIG_CMDID,
320	WMI_PDEV_SET_BASE_MACADDR_CMDID,
321	WMI_PDEV_DUMP_CMDID,
322	WMI_PDEV_SET_LED_CONFIG_CMDID,
323	WMI_PDEV_GET_TEMPERATURE_CMDID,
324	WMI_PDEV_SET_LED_FLASHING_CMDID,
325	WMI_PDEV_SMART_ANT_ENABLE_CMDID,
326	WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID,
327	WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID,
328	WMI_PDEV_SET_CTL_TABLE_CMDID,
329	WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID,
330	WMI_PDEV_FIPS_CMDID,
331	WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID,
332	WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID,
333	WMI_PDEV_GET_NFCAL_POWER_CMDID,
334	WMI_PDEV_GET_TPC_CMDID,
335	WMI_MIB_STATS_ENABLE_CMDID,
336	WMI_PDEV_SET_PCL_CMDID,
337	WMI_PDEV_SET_HW_MODE_CMDID,
338	WMI_PDEV_SET_MAC_CONFIG_CMDID,
339	WMI_PDEV_SET_ANTENNA_MODE_CMDID,
340	WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID,
341	WMI_PDEV_WAL_POWER_DEBUG_CMDID,
342	WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID,
343	WMI_PDEV_SET_WAKEUP_CONFIG_CMDID,
344	WMI_PDEV_GET_ANTDIV_STATUS_CMDID,
345	WMI_PDEV_GET_CHIP_POWER_STATS_CMDID,
346	WMI_PDEV_SET_STATS_THRESHOLD_CMDID,
347	WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID,
348	WMI_PDEV_UPDATE_PKT_ROUTING_CMDID,
349	WMI_PDEV_CHECK_CAL_VERSION_CMDID,
350	WMI_PDEV_SET_DIVERSITY_GAIN_CMDID,
351	WMI_PDEV_DIV_GET_RSSI_ANTID_CMDID,
352	WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID,
353	WMI_PDEV_UPDATE_PMK_CACHE_CMDID,
354	WMI_PDEV_UPDATE_FILS_HLP_PKT_CMDID,
355	WMI_PDEV_UPDATE_CTLTABLE_REQUEST_CMDID,
356	WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID,
357	WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID,
358	WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID,
359	WMI_PDEV_DMA_RING_CFG_REQ_CMDID,
360	WMI_PDEV_HE_TB_ACTION_FRM_CMDID,
361	WMI_PDEV_PKTLOG_FILTER_CMDID,
362	WMI_PDEV_SET_RAP_CONFIG_CMDID,
363	WMI_PDEV_DSM_FILTER_CMDID,
364	WMI_PDEV_FRAME_INJECT_CMDID,
365	WMI_PDEV_TBTT_OFFSET_SYNC_CMDID,
366	WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID,
367	WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID,
368	WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID,
369	WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID,
370	WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID,
371	WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID,
372	WMI_PDEV_GET_TPC_STATS_CMDID,
373	WMI_PDEV_ENABLE_DURATION_BASED_TX_MODE_SELECTION_CMDID,
374	WMI_PDEV_GET_DPD_STATUS_CMDID,
375	WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID,
376	WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID,
377	WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV),
378	WMI_VDEV_DELETE_CMDID,
379	WMI_VDEV_START_REQUEST_CMDID,
380	WMI_VDEV_RESTART_REQUEST_CMDID,
381	WMI_VDEV_UP_CMDID,
382	WMI_VDEV_STOP_CMDID,
383	WMI_VDEV_DOWN_CMDID,
384	WMI_VDEV_SET_PARAM_CMDID,
385	WMI_VDEV_INSTALL_KEY_CMDID,
386	WMI_VDEV_WNM_SLEEPMODE_CMDID,
387	WMI_VDEV_WMM_ADDTS_CMDID,
388	WMI_VDEV_WMM_DELTS_CMDID,
389	WMI_VDEV_SET_WMM_PARAMS_CMDID,
390	WMI_VDEV_SET_GTX_PARAMS_CMDID,
391	WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID,
392	WMI_VDEV_PLMREQ_START_CMDID,
393	WMI_VDEV_PLMREQ_STOP_CMDID,
394	WMI_VDEV_TSF_TSTAMP_ACTION_CMDID,
395	WMI_VDEV_SET_IE_CMDID,
396	WMI_VDEV_RATEMASK_CMDID,
397	WMI_VDEV_ATF_REQUEST_CMDID,
398	WMI_VDEV_SET_DSCP_TID_MAP_CMDID,
399	WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID,
400	WMI_VDEV_SET_QUIET_MODE_CMDID,
401	WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID,
402	WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID,
403	WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID,
404	WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER),
405	WMI_PEER_DELETE_CMDID,
406	WMI_PEER_FLUSH_TIDS_CMDID,
407	WMI_PEER_SET_PARAM_CMDID,
408	WMI_PEER_ASSOC_CMDID,
409	WMI_PEER_ADD_WDS_ENTRY_CMDID,
410	WMI_PEER_REMOVE_WDS_ENTRY_CMDID,
411	WMI_PEER_MCAST_GROUP_CMDID,
412	WMI_PEER_INFO_REQ_CMDID,
413	WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID,
414	WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID,
415	WMI_PEER_UPDATE_WDS_ENTRY_CMDID,
416	WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID,
417	WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID,
418	WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID,
419	WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID,
420	WMI_PEER_ATF_REQUEST_CMDID,
421	WMI_PEER_BWF_REQUEST_CMDID,
422	WMI_PEER_REORDER_QUEUE_SETUP_CMDID,
423	WMI_PEER_REORDER_QUEUE_REMOVE_CMDID,
424	WMI_PEER_SET_RX_BLOCKSIZE_CMDID,
425	WMI_PEER_ANTDIV_INFO_REQ_CMDID,
426	WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT),
427	WMI_PDEV_SEND_BCN_CMDID,
428	WMI_BCN_TMPL_CMDID,
429	WMI_BCN_FILTER_RX_CMDID,
430	WMI_PRB_REQ_FILTER_RX_CMDID,
431	WMI_MGMT_TX_CMDID,
432	WMI_PRB_TMPL_CMDID,
433	WMI_MGMT_TX_SEND_CMDID,
434	WMI_OFFCHAN_DATA_TX_SEND_CMDID,
435	WMI_PDEV_SEND_FD_CMDID,
436	WMI_BCN_OFFLOAD_CTRL_CMDID,
437	WMI_BSS_COLOR_CHANGE_ENABLE_CMDID,
438	WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID,
439	WMI_FILS_DISCOVERY_TMPL_CMDID,
440	WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG),
441	WMI_ADDBA_SEND_CMDID,
442	WMI_ADDBA_STATUS_CMDID,
443	WMI_DELBA_SEND_CMDID,
444	WMI_ADDBA_SET_RESP_CMDID,
445	WMI_SEND_SINGLEAMSDU_CMDID,
446	WMI_STA_POWERSAVE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_PS),
447	WMI_STA_POWERSAVE_PARAM_CMDID,
448	WMI_STA_MIMO_PS_MODE_CMDID,
449	WMI_PDEV_DFS_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_DFS),
450	WMI_PDEV_DFS_DISABLE_CMDID,
451	WMI_DFS_PHYERR_FILTER_ENA_CMDID,
452	WMI_DFS_PHYERR_FILTER_DIS_CMDID,
453	WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID,
454	WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID,
455	WMI_VDEV_ADFS_CH_CFG_CMDID,
456	WMI_VDEV_ADFS_OCAC_ABORT_CMDID,
457	WMI_ROAM_SCAN_MODE = WMI_TLV_CMD(WMI_GRP_ROAM),
458	WMI_ROAM_SCAN_RSSI_THRESHOLD,
459	WMI_ROAM_SCAN_PERIOD,
460	WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
461	WMI_ROAM_AP_PROFILE,
462	WMI_ROAM_CHAN_LIST,
463	WMI_ROAM_SCAN_CMD,
464	WMI_ROAM_SYNCH_COMPLETE,
465	WMI_ROAM_SET_RIC_REQUEST_CMDID,
466	WMI_ROAM_INVOKE_CMDID,
467	WMI_ROAM_FILTER_CMDID,
468	WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID,
469	WMI_ROAM_CONFIGURE_MAWC_CMDID,
470	WMI_ROAM_SET_MBO_PARAM_CMDID,
471	WMI_ROAM_PER_CONFIG_CMDID,
472	WMI_ROAM_BTM_CONFIG_CMDID,
473	WMI_ENABLE_FILS_CMDID,
474	WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_TLV_CMD(WMI_GRP_OFL_SCAN),
475	WMI_OFL_SCAN_REMOVE_AP_PROFILE,
476	WMI_OFL_SCAN_PERIOD,
477	WMI_P2P_DEV_SET_DEVICE_INFO = WMI_TLV_CMD(WMI_GRP_P2P),
478	WMI_P2P_DEV_SET_DISCOVERABILITY,
479	WMI_P2P_GO_SET_BEACON_IE,
480	WMI_P2P_GO_SET_PROBE_RESP_IE,
481	WMI_P2P_SET_VENDOR_IE_DATA_CMDID,
482	WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID,
483	WMI_P2P_DISC_OFFLOAD_APPIE_CMDID,
484	WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID,
485	WMI_P2P_SET_OPPPS_PARAM_CMDID,
486	WMI_P2P_LISTEN_OFFLOAD_START_CMDID,
487	WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID,
488	WMI_AP_PS_PEER_PARAM_CMDID = WMI_TLV_CMD(WMI_GRP_AP_PS),
489	WMI_AP_PS_PEER_UAPSD_COEX_CMDID,
490	WMI_AP_PS_EGAP_PARAM_CMDID,
491	WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_TLV_CMD(WMI_GRP_RATE_CTRL),
492	WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_TLV_CMD(WMI_GRP_PROFILE),
493	WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
494	WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
495	WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
496	WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
497	WMI_PDEV_SUSPEND_CMDID = WMI_TLV_CMD(WMI_GRP_SUSPEND),
498	WMI_PDEV_RESUME_CMDID,
499	WMI_ADD_BCN_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_BCN_FILTER),
500	WMI_RMV_BCN_FILTER_CMDID,
501	WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_TLV_CMD(WMI_GRP_WOW),
502	WMI_WOW_DEL_WAKE_PATTERN_CMDID,
503	WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
504	WMI_WOW_ENABLE_CMDID,
505	WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
506	WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID,
507	WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID,
508	WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID,
509	WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID,
510	WMI_D0_WOW_ENABLE_DISABLE_CMDID,
511	WMI_EXTWOW_ENABLE_CMDID,
512	WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID,
513	WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID,
514	WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID,
515	WMI_WOW_UDP_SVC_OFLD_CMDID,
516	WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID,
517	WMI_WOW_SET_ACTION_WAKE_UP_CMDID,
518	WMI_RTT_MEASREQ_CMDID = WMI_TLV_CMD(WMI_GRP_RTT),
519	WMI_RTT_TSF_CMDID,
520	WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_TLV_CMD(WMI_GRP_SPECTRAL),
521	WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
522	WMI_REQUEST_STATS_CMDID = WMI_TLV_CMD(WMI_GRP_STATS),
523	WMI_MCC_SCHED_TRAFFIC_STATS_CMDID,
524	WMI_REQUEST_STATS_EXT_CMDID,
525	WMI_REQUEST_LINK_STATS_CMDID,
526	WMI_START_LINK_STATS_CMDID,
527	WMI_CLEAR_LINK_STATS_CMDID,
528	WMI_GET_FW_MEM_DUMP_CMDID,
529	WMI_DEBUG_MESG_FLUSH_CMDID,
530	WMI_DIAG_EVENT_LOG_CONFIG_CMDID,
531	WMI_REQUEST_WLAN_STATS_CMDID,
532	WMI_REQUEST_RCPI_CMDID,
533	WMI_REQUEST_PEER_STATS_INFO_CMDID,
534	WMI_REQUEST_RADIO_CHAN_STATS_CMDID,
535	WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL),
536	WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID,
537	WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID,
538	WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_NLO_OFL),
539	WMI_APFIND_CMDID,
540	WMI_PASSPOINT_LIST_CONFIG_CMDID,
541	WMI_NLO_CONFIGURE_MAWC_CMDID,
542	WMI_GTK_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_GTK_OFL),
543	WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_CSA_OFL),
544	WMI_CSA_OFFLOAD_CHANSWITCH_CMDID,
545	WMI_CHATTER_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_CHATTER),
546	WMI_CHATTER_ADD_COALESCING_FILTER_CMDID,
547	WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID,
548	WMI_CHATTER_COALESCING_QUERY_CMDID,
549	WMI_PEER_TID_ADDBA_CMDID = WMI_TLV_CMD(WMI_GRP_TID_ADDBA),
550	WMI_PEER_TID_DELBA_CMDID,
551	WMI_STA_DTIM_PS_METHOD_CMDID,
552	WMI_STA_UAPSD_AUTO_TRIG_CMDID,
553	WMI_STA_KEEPALIVE_CMDID,
554	WMI_BA_REQ_SSN_CMDID,
555	WMI_ECHO_CMDID = WMI_TLV_CMD(WMI_GRP_MISC),
556	WMI_PDEV_UTF_CMDID,
557	WMI_DBGLOG_CFG_CMDID,
558	WMI_PDEV_QVIT_CMDID,
559	WMI_PDEV_FTM_INTG_CMDID,
560	WMI_VDEV_SET_KEEPALIVE_CMDID,
561	WMI_VDEV_GET_KEEPALIVE_CMDID,
562	WMI_FORCE_FW_HANG_CMDID,
563	WMI_SET_MCASTBCAST_FILTER_CMDID,
564	WMI_THERMAL_MGMT_CMDID,
565	WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID,
566	WMI_TPC_CHAINMASK_CONFIG_CMDID,
567	WMI_SET_ANTENNA_DIVERSITY_CMDID,
568	WMI_OCB_SET_SCHED_CMDID,
569	WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID,
570	WMI_LRO_CONFIG_CMDID,
571	WMI_TRANSFER_DATA_TO_FLASH_CMDID,
572	WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID,
573	WMI_VDEV_WISA_CMDID,
574	WMI_DBGLOG_TIME_STAMP_SYNC_CMDID,
575	WMI_SET_MULTIPLE_MCAST_FILTER_CMDID,
576	WMI_READ_DATA_FROM_FLASH_CMDID,
577	WMI_THERM_THROT_SET_CONF_CMDID,
578	WMI_RUNTIME_DPD_RECAL_CMDID,
579	WMI_GET_TPC_POWER_CMDID,
580	WMI_IDLE_TRIGGER_MONITOR_CMDID,
581	WMI_GPIO_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_GPIO),
582	WMI_GPIO_OUTPUT_CMDID,
583	WMI_TXBF_CMDID,
584	WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_FWTEST),
585	WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID,
586	WMI_UNIT_TEST_CMDID,
587	WMI_FWTEST_CMDID,
588	WMI_QBOOST_CFG_CMDID,
589	WMI_TDLS_SET_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_TDLS),
590	WMI_TDLS_PEER_UPDATE_CMDID,
591	WMI_TDLS_SET_OFFCHAN_MODE_CMDID,
592	WMI_RESMGR_ADAPTIVE_OCS_EN_DIS_CMDID = WMI_TLV_CMD(WMI_GRP_RESMGR),
593	WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID,
594	WMI_RESMGR_SET_CHAN_LATENCY_CMDID,
595	WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_SMPS),
596	WMI_STA_SMPS_PARAM_CMDID,
597	WMI_HB_SET_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_WLAN_HB),
598	WMI_HB_SET_TCP_PARAMS_CMDID,
599	WMI_HB_SET_TCP_PKT_FILTER_CMDID,
600	WMI_HB_SET_UDP_PARAMS_CMDID,
601	WMI_HB_SET_UDP_PKT_FILTER_CMDID,
602	WMI_RMC_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_RMC),
603	WMI_RMC_SET_ACTION_PERIOD_CMDID,
604	WMI_RMC_CONFIG_CMDID,
605	WMI_RMC_SET_MANUAL_LEADER_CMDID,
606	WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_MHF_OFL),
607	WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID,
608	WMI_BATCH_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN),
609	WMI_BATCH_SCAN_DISABLE_CMDID,
610	WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID,
611	WMI_OEM_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_OEM),
612	WMI_OEM_REQUEST_CMDID,
613	WMI_LPI_OEM_REQ_CMDID,
614	WMI_NAN_CMDID = WMI_TLV_CMD(WMI_GRP_NAN),
615	WMI_MODEM_POWER_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_COEX),
616	WMI_CHAN_AVOID_UPDATE_CMDID,
617	WMI_COEX_CONFIG_CMDID,
618	WMI_CHAN_AVOID_RPT_ALLOW_CMDID,
619	WMI_COEX_GET_ANTENNA_ISOLATION_CMDID,
620	WMI_SAR_LIMITS_CMDID,
621	WMI_OBSS_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_OBSS_OFL),
622	WMI_OBSS_SCAN_DISABLE_CMDID,
623	WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID,
624	WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LPI),
625	WMI_LPI_START_SCAN_CMDID,
626	WMI_LPI_STOP_SCAN_CMDID,
627	WMI_EXTSCAN_START_CMDID = WMI_TLV_CMD(WMI_GRP_EXTSCAN),
628	WMI_EXTSCAN_STOP_CMDID,
629	WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID,
630	WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID,
631	WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID,
632	WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID,
633	WMI_EXTSCAN_SET_CAPABILITIES_CMDID,
634	WMI_EXTSCAN_GET_CAPABILITIES_CMDID,
635	WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID,
636	WMI_EXTSCAN_CONFIGURE_MAWC_CMDID,
637	WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_DHCP_OFL),
638	WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_TLV_CMD(WMI_GRP_IPA),
639	WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL),
640	WMI_MDNS_SET_FQDN_CMDID,
641	WMI_MDNS_SET_RESPONSE_CMDID,
642	WMI_MDNS_GET_STATS_CMDID,
643	WMI_SAP_OFL_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_SAP_OFL),
644	WMI_SAP_SET_BLACKLIST_PARAM_CMDID,
645	WMI_OCB_SET_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_OCB),
646	WMI_OCB_SET_UTC_TIME_CMDID,
647	WMI_OCB_START_TIMING_ADVERT_CMDID,
648	WMI_OCB_STOP_TIMING_ADVERT_CMDID,
649	WMI_OCB_GET_TSF_TIMER_CMDID,
650	WMI_DCC_GET_STATS_CMDID,
651	WMI_DCC_CLEAR_STATS_CMDID,
652	WMI_DCC_UPDATE_NDL_CMDID,
653	WMI_SOC_SET_PCL_CMDID = WMI_TLV_CMD(WMI_GRP_SOC),
654	WMI_SOC_SET_HW_MODE_CMDID,
655	WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID,
656	WMI_SOC_SET_ANTENNA_MODE_CMDID,
657	WMI_PACKET_FILTER_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_PKT_FILTER),
658	WMI_PACKET_FILTER_ENABLE_CMDID,
659	WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_TLV_CMD(WMI_GRP_MAWC),
660	WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_TLV_CMD(WMI_GRP_PMF_OFFLOAD),
661	WMI_BPF_GET_CAPABILITY_CMDID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD),
662	WMI_BPF_GET_VDEV_STATS_CMDID,
663	WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID,
664	WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID,
665	WMI_BPF_SET_VDEV_ACTIVE_MODE_CMDID,
666	WMI_MNT_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_MONITOR),
667	WMI_SET_CURRENT_COUNTRY_CMDID = WMI_TLV_CMD(WMI_GRP_REGULATORY),
668	WMI_11D_SCAN_START_CMDID,
669	WMI_11D_SCAN_STOP_CMDID,
670	WMI_SET_INIT_COUNTRY_CMDID,
671	WMI_NDI_GET_CAP_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE),
672	WMI_NDP_INITIATOR_REQ_CMDID,
673	WMI_NDP_RESPONDER_REQ_CMDID,
674	WMI_NDP_END_REQ_CMDID,
675	WMI_HW_DATA_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_HW_DATA_FILTER),
676	WMI_TWT_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_TWT),
677	WMI_TWT_DISABLE_CMDID,
678	WMI_TWT_ADD_DIALOG_CMDID,
679	WMI_TWT_DEL_DIALOG_CMDID,
680	WMI_TWT_PAUSE_DIALOG_CMDID,
681	WMI_TWT_RESUME_DIALOG_CMDID,
682	WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID =
683				WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE),
684	WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID,
685};
686
687enum wmi_tlv_event_id {
688	WMI_SERVICE_READY_EVENTID = 0x1,
689	WMI_READY_EVENTID,
690	WMI_SERVICE_AVAILABLE_EVENTID,
691	WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN),
692	WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV),
693	WMI_CHAN_INFO_EVENTID,
694	WMI_PHYERR_EVENTID,
695	WMI_PDEV_DUMP_EVENTID,
696	WMI_TX_PAUSE_EVENTID,
697	WMI_DFS_RADAR_EVENTID,
698	WMI_PDEV_L1SS_TRACK_EVENTID,
699	WMI_PDEV_TEMPERATURE_EVENTID,
700	WMI_SERVICE_READY_EXT_EVENTID,
701	WMI_PDEV_FIPS_EVENTID,
702	WMI_PDEV_CHANNEL_HOPPING_EVENTID,
703	WMI_PDEV_ANI_CCK_LEVEL_EVENTID,
704	WMI_PDEV_ANI_OFDM_LEVEL_EVENTID,
705	WMI_PDEV_TPC_EVENTID,
706	WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID,
707	WMI_PDEV_SET_HW_MODE_RESP_EVENTID,
708	WMI_PDEV_HW_MODE_TRANSITION_EVENTID,
709	WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID,
710	WMI_PDEV_ANTDIV_STATUS_EVENTID,
711	WMI_PDEV_CHIP_POWER_STATS_EVENTID,
712	WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID,
713	WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID,
714	WMI_PDEV_CHECK_CAL_VERSION_EVENTID,
715	WMI_PDEV_DIV_RSSI_ANTID_EVENTID,
716	WMI_PDEV_BSS_CHAN_INFO_EVENTID,
717	WMI_PDEV_UPDATE_CTLTABLE_EVENTID,
718	WMI_PDEV_DMA_RING_CFG_RSP_EVENTID,
719	WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID,
720	WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID,
721	WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID,
722	WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID,
723	WMI_PDEV_RAP_INFO_EVENTID,
724	WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID,
725	WMI_SERVICE_READY_EXT2_EVENTID,
726	WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV),
727	WMI_VDEV_STOPPED_EVENTID,
728	WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID,
729	WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID,
730	WMI_VDEV_TSF_REPORT_EVENTID,
731	WMI_VDEV_DELETE_RESP_EVENTID,
732	WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID,
733	WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENTID,
734	WMI_PEER_STA_KICKOUT_EVENTID = WMI_TLV_CMD(WMI_GRP_PEER),
735	WMI_PEER_INFO_EVENTID,
736	WMI_PEER_TX_FAIL_CNT_THR_EVENTID,
737	WMI_PEER_ESTIMATED_LINKSPEED_EVENTID,
738	WMI_PEER_STATE_EVENTID,
739	WMI_PEER_ASSOC_CONF_EVENTID,
740	WMI_PEER_DELETE_RESP_EVENTID,
741	WMI_PEER_RATECODE_LIST_EVENTID,
742	WMI_WDS_PEER_EVENTID,
743	WMI_PEER_STA_PS_STATECHG_EVENTID,
744	WMI_PEER_ANTDIV_INFO_EVENTID,
745	WMI_PEER_RESERVED0_EVENTID,
746	WMI_PEER_RESERVED1_EVENTID,
747	WMI_PEER_RESERVED2_EVENTID,
748	WMI_PEER_RESERVED3_EVENTID,
749	WMI_PEER_RESERVED4_EVENTID,
750	WMI_PEER_RESERVED5_EVENTID,
751	WMI_PEER_RESERVED6_EVENTID,
752	WMI_PEER_RESERVED7_EVENTID,
753	WMI_PEER_RESERVED8_EVENTID,
754	WMI_PEER_RESERVED9_EVENTID,
755	WMI_PEER_RESERVED10_EVENTID,
756	WMI_PEER_OPER_MODE_CHANGE_EVENTID,
757	WMI_PEER_TX_PN_RESPONSE_EVENTID,
758	WMI_PEER_CFR_CAPTURE_EVENTID,
759	WMI_PEER_CREATE_CONF_EVENTID,
760	WMI_MGMT_RX_EVENTID = WMI_TLV_CMD(WMI_GRP_MGMT),
761	WMI_HOST_SWBA_EVENTID,
762	WMI_TBTTOFFSET_UPDATE_EVENTID,
763	WMI_OFFLOAD_BCN_TX_STATUS_EVENTID,
764	WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID,
765	WMI_MGMT_TX_COMPLETION_EVENTID,
766	WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID,
767	WMI_TBTTOFFSET_EXT_UPDATE_EVENTID,
768	WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID,
769	WMI_HOST_FILS_DISCOVERY_EVENTID,
770	WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG),
771	WMI_TX_ADDBA_COMPLETE_EVENTID,
772	WMI_BA_RSP_SSN_EVENTID,
773	WMI_AGGR_STATE_TRIG_EVENTID,
774	WMI_ROAM_EVENTID = WMI_TLV_CMD(WMI_GRP_ROAM),
775	WMI_PROFILE_MATCH,
776	WMI_ROAM_SYNCH_EVENTID,
777	WMI_P2P_DISC_EVENTID = WMI_TLV_CMD(WMI_GRP_P2P),
778	WMI_P2P_NOA_EVENTID,
779	WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID,
780	WMI_AP_PS_EGAP_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_AP_PS),
781	WMI_PDEV_RESUME_EVENTID = WMI_TLV_CMD(WMI_GRP_SUSPEND),
782	WMI_WOW_WAKEUP_HOST_EVENTID = WMI_TLV_CMD(WMI_GRP_WOW),
783	WMI_D0_WOW_DISABLE_ACK_EVENTID,
784	WMI_WOW_INITIAL_WAKEUP_EVENTID,
785	WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_TLV_CMD(WMI_GRP_RTT),
786	WMI_TSF_MEASUREMENT_REPORT_EVENTID,
787	WMI_RTT_ERROR_REPORT_EVENTID,
788	WMI_STATS_EXT_EVENTID = WMI_TLV_CMD(WMI_GRP_STATS),
789	WMI_IFACE_LINK_STATS_EVENTID,
790	WMI_PEER_LINK_STATS_EVENTID,
791	WMI_RADIO_LINK_STATS_EVENTID,
792	WMI_UPDATE_FW_MEM_DUMP_EVENTID,
793	WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID,
794	WMI_INST_RSSI_STATS_EVENTID,
795	WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID,
796	WMI_REPORT_STATS_EVENTID,
797	WMI_UPDATE_RCPI_EVENTID,
798	WMI_PEER_STATS_INFO_EVENTID,
799	WMI_RADIO_CHAN_STATS_EVENTID,
800	WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL),
801	WMI_NLO_SCAN_COMPLETE_EVENTID,
802	WMI_APFIND_EVENTID,
803	WMI_PASSPOINT_MATCH_EVENTID,
804	WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_TLV_CMD(WMI_GRP_GTK_OFL),
805	WMI_GTK_REKEY_FAIL_EVENTID,
806	WMI_CSA_HANDLING_EVENTID = WMI_TLV_CMD(WMI_GRP_CSA_OFL),
807	WMI_CHATTER_PC_QUERY_EVENTID = WMI_TLV_CMD(WMI_GRP_CHATTER),
808	WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_TLV_CMD(WMI_GRP_DFS),
809	WMI_VDEV_DFS_CAC_COMPLETE_EVENTID,
810	WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID,
811	WMI_ECHO_EVENTID = WMI_TLV_CMD(WMI_GRP_MISC),
812	WMI_PDEV_UTF_EVENTID,
813	WMI_DEBUG_MESG_EVENTID,
814	WMI_UPDATE_STATS_EVENTID,
815	WMI_DEBUG_PRINT_EVENTID,
816	WMI_DCS_INTERFERENCE_EVENTID,
817	WMI_PDEV_QVIT_EVENTID,
818	WMI_WLAN_PROFILE_DATA_EVENTID,
819	WMI_PDEV_FTM_INTG_EVENTID,
820	WMI_WLAN_FREQ_AVOID_EVENTID,
821	WMI_VDEV_GET_KEEPALIVE_EVENTID,
822	WMI_THERMAL_MGMT_EVENTID,
823	WMI_DIAG_DATA_CONTAINER_EVENTID,
824	WMI_HOST_AUTO_SHUTDOWN_EVENTID,
825	WMI_UPDATE_WHAL_MIB_STATS_EVENTID,
826	WMI_UPDATE_VDEV_RATE_STATS_EVENTID,
827	WMI_DIAG_EVENTID,
828	WMI_OCB_SET_SCHED_EVENTID,
829	WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID,
830	WMI_RSSI_BREACH_EVENTID,
831	WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID,
832	WMI_PDEV_UTF_SCPC_EVENTID,
833	WMI_READ_DATA_FROM_FLASH_EVENTID,
834	WMI_REPORT_RX_AGGR_FAILURE_EVENTID,
835	WMI_PKGID_EVENTID,
836	WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO),
837	WMI_UPLOADH_EVENTID,
838	WMI_CAPTUREH_EVENTID,
839	WMI_RFKILL_STATE_CHANGE_EVENTID,
840	WMI_TDLS_PEER_EVENTID = WMI_TLV_CMD(WMI_GRP_TDLS),
841	WMI_STA_SMPS_FORCE_MODE_COMPL_EVENTID = WMI_TLV_CMD(WMI_GRP_STA_SMPS),
842	WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN),
843	WMI_BATCH_SCAN_RESULT_EVENTID,
844	WMI_OEM_CAPABILITY_EVENTID = WMI_TLV_CMD(WMI_GRP_OEM),
845	WMI_OEM_MEASUREMENT_REPORT_EVENTID,
846	WMI_OEM_ERROR_REPORT_EVENTID,
847	WMI_OEM_RESPONSE_EVENTID,
848	WMI_NAN_EVENTID = WMI_TLV_CMD(WMI_GRP_NAN),
849	WMI_NAN_DISC_IFACE_CREATED_EVENTID,
850	WMI_NAN_DISC_IFACE_DELETED_EVENTID,
851	WMI_NAN_STARTED_CLUSTER_EVENTID,
852	WMI_NAN_JOINED_CLUSTER_EVENTID,
853	WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_TLV_CMD(WMI_GRP_COEX),
854	WMI_LPI_RESULT_EVENTID = WMI_TLV_CMD(WMI_GRP_LPI),
855	WMI_LPI_STATUS_EVENTID,
856	WMI_LPI_HANDOFF_EVENTID,
857	WMI_EXTSCAN_START_STOP_EVENTID = WMI_TLV_CMD(WMI_GRP_EXTSCAN),
858	WMI_EXTSCAN_OPERATION_EVENTID,
859	WMI_EXTSCAN_TABLE_USAGE_EVENTID,
860	WMI_EXTSCAN_CACHED_RESULTS_EVENTID,
861	WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID,
862	WMI_EXTSCAN_HOTLIST_MATCH_EVENTID,
863	WMI_EXTSCAN_CAPABILITIES_EVENTID,
864	WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID,
865	WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL),
866	WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL),
867	WMI_SAP_OFL_DEL_STA_EVENTID,
868	WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID =
869		WMI_EVT_GRP_START_ID(WMI_GRP_OBSS_OFL),
870	WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB),
871	WMI_OCB_GET_TSF_TIMER_RESP_EVENTID,
872	WMI_DCC_GET_STATS_RESP_EVENTID,
873	WMI_DCC_UPDATE_NDL_RESP_EVENTID,
874	WMI_DCC_STATS_EVENTID,
875	WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_SOC),
876	WMI_SOC_HW_MODE_TRANSITION_EVENTID,
877	WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID,
878	WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_TLV_CMD(WMI_GRP_MAWC),
879	WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD),
880	WMI_BPF_VDEV_STATS_INFO_EVENTID,
881	WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC),
882	WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY),
883	WMI_11D_NEW_COUNTRY_EVENTID,
884	WMI_REG_CHAN_LIST_CC_EXT_EVENTID,
885	WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE),
886	WMI_NDP_INITIATOR_RSP_EVENTID,
887	WMI_NDP_RESPONDER_RSP_EVENTID,
888	WMI_NDP_END_RSP_EVENTID,
889	WMI_NDP_INDICATION_EVENTID,
890	WMI_NDP_CONFIRM_EVENTID,
891	WMI_NDP_END_INDICATION_EVENTID,
892
893	WMI_TWT_ENABLE_EVENTID = WMI_TLV_CMD(WMI_GRP_TWT),
894	WMI_TWT_DISABLE_EVENTID,
895	WMI_TWT_ADD_DIALOG_EVENTID,
896	WMI_TWT_DEL_DIALOG_EVENTID,
897	WMI_TWT_PAUSE_DIALOG_EVENTID,
898	WMI_TWT_RESUME_DIALOG_EVENTID,
899};
900
901enum wmi_tlv_pdev_param {
902	WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1,
903	WMI_PDEV_PARAM_RX_CHAIN_MASK,
904	WMI_PDEV_PARAM_TXPOWER_LIMIT2G,
905	WMI_PDEV_PARAM_TXPOWER_LIMIT5G,
906	WMI_PDEV_PARAM_TXPOWER_SCALE,
907	WMI_PDEV_PARAM_BEACON_GEN_MODE,
908	WMI_PDEV_PARAM_BEACON_TX_MODE,
909	WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE,
910	WMI_PDEV_PARAM_PROTECTION_MODE,
911	WMI_PDEV_PARAM_DYNAMIC_BW,
912	WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH,
913	WMI_PDEV_PARAM_AGG_SW_RETRY_TH,
914	WMI_PDEV_PARAM_STA_KICKOUT_TH,
915	WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING,
916	WMI_PDEV_PARAM_LTR_ENABLE,
917	WMI_PDEV_PARAM_LTR_AC_LATENCY_BE,
918	WMI_PDEV_PARAM_LTR_AC_LATENCY_BK,
919	WMI_PDEV_PARAM_LTR_AC_LATENCY_VI,
920	WMI_PDEV_PARAM_LTR_AC_LATENCY_VO,
921	WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT,
922	WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE,
923	WMI_PDEV_PARAM_LTR_RX_OVERRIDE,
924	WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT,
925	WMI_PDEV_PARAM_L1SS_ENABLE,
926	WMI_PDEV_PARAM_DSLEEP_ENABLE,
927	WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH,
928	WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK,
929	WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN,
930	WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE,
931	WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD,
932	WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD,
933	WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD,
934	WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD,
935	WMI_PDEV_PARAM_PMF_QOS,
936	WMI_PDEV_PARAM_ARP_AC_OVERRIDE,
937	WMI_PDEV_PARAM_DCS,
938	WMI_PDEV_PARAM_ANI_ENABLE,
939	WMI_PDEV_PARAM_ANI_POLL_PERIOD,
940	WMI_PDEV_PARAM_ANI_LISTEN_PERIOD,
941	WMI_PDEV_PARAM_ANI_OFDM_LEVEL,
942	WMI_PDEV_PARAM_ANI_CCK_LEVEL,
943	WMI_PDEV_PARAM_DYNTXCHAIN,
944	WMI_PDEV_PARAM_PROXY_STA,
945	WMI_PDEV_PARAM_IDLE_PS_CONFIG,
946	WMI_PDEV_PARAM_POWER_GATING_SLEEP,
947	WMI_PDEV_PARAM_RFKILL_ENABLE,
948	WMI_PDEV_PARAM_BURST_DUR,
949	WMI_PDEV_PARAM_BURST_ENABLE,
950	WMI_PDEV_PARAM_HW_RFKILL_CONFIG,
951	WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE,
952	WMI_PDEV_PARAM_L1SS_TRACK,
953	WMI_PDEV_PARAM_HYST_EN,
954	WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE,
955	WMI_PDEV_PARAM_LED_SYS_STATE,
956	WMI_PDEV_PARAM_LED_ENABLE,
957	WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY,
958	WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE,
959	WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE,
960	WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD,
961	WMI_PDEV_PARAM_CTS_CBW,
962	WMI_PDEV_PARAM_WNTS_CONFIG,
963	WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE,
964	WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP,
965	WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP,
966	WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP,
967	WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE,
968	WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT,
969	WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP,
970	WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT,
971	WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE,
972	WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE,
973	WMI_PDEV_PARAM_TX_CHAIN_MASK_2G,
974	WMI_PDEV_PARAM_RX_CHAIN_MASK_2G,
975	WMI_PDEV_PARAM_TX_CHAIN_MASK_5G,
976	WMI_PDEV_PARAM_RX_CHAIN_MASK_5G,
977	WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK,
978	WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS,
979	WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG,
980	WMI_PDEV_PARAM_TXPOWER_DECR_DB,
981	WMI_PDEV_PARAM_AGGR_BURST,
982	WMI_PDEV_PARAM_RX_DECAP_MODE,
983	WMI_PDEV_PARAM_FAST_CHANNEL_RESET,
984	WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA,
985	WMI_PDEV_PARAM_ANTENNA_GAIN,
986	WMI_PDEV_PARAM_RX_FILTER,
987	WMI_PDEV_SET_MCAST_TO_UCAST_TID,
988	WMI_PDEV_PARAM_PROXY_STA_MODE,
989	WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE,
990	WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER,
991	WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER,
992	WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE,
993	WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE,
994	WMI_PDEV_PARAM_BLOCK_INTERBSS,
995	WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID,
996	WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID,
997	WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID,
998	WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID,
999	WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID,
1000	WMI_PDEV_PARAM_SET_BURST_MODE_CMDID,
1001	WMI_PDEV_PARAM_EN_STATS,
1002	WMI_PDEV_PARAM_MU_GROUP_POLICY,
1003	WMI_PDEV_PARAM_NOISE_DETECTION,
1004	WMI_PDEV_PARAM_NOISE_THRESHOLD,
1005	WMI_PDEV_PARAM_DPD_ENABLE,
1006	WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO,
1007	WMI_PDEV_PARAM_ATF_STRICT_SCH,
1008	WMI_PDEV_PARAM_ATF_SCHED_DURATION,
1009	WMI_PDEV_PARAM_ANT_PLZN,
1010	WMI_PDEV_PARAM_MGMT_RETRY_LIMIT,
1011	WMI_PDEV_PARAM_SENSITIVITY_LEVEL,
1012	WMI_PDEV_PARAM_SIGNED_TXPOWER_2G,
1013	WMI_PDEV_PARAM_SIGNED_TXPOWER_5G,
1014	WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU,
1015	WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU,
1016	WMI_PDEV_PARAM_CCA_THRESHOLD,
1017	WMI_PDEV_PARAM_RTS_FIXED_RATE,
1018	WMI_PDEV_PARAM_PDEV_RESET,
1019	WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET,
1020	WMI_PDEV_PARAM_ARP_DBG_SRCADDR,
1021	WMI_PDEV_PARAM_ARP_DBG_DSTADDR,
1022	WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH,
1023	WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR,
1024	WMI_PDEV_PARAM_CUST_TXPOWER_SCALE,
1025	WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE,
1026	WMI_PDEV_PARAM_CTRL_RETRY_LIMIT,
1027	WMI_PDEV_PARAM_PROPAGATION_DELAY,
1028	WMI_PDEV_PARAM_ENA_ANT_DIV,
1029	WMI_PDEV_PARAM_FORCE_CHAIN_ANT,
1030	WMI_PDEV_PARAM_ANT_DIV_SELFTEST,
1031	WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL,
1032	WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD,
1033	WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS,
1034	WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN,
1035	WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN,
1036	WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN,
1037	WMI_PDEV_PARAM_TX_SCH_DELAY,
1038	WMI_PDEV_PARAM_ENABLE_RTS_SIFS_BURSTING,
1039	WMI_PDEV_PARAM_MAX_MPDUS_IN_AMPDU,
1040	WMI_PDEV_PARAM_PEER_STATS_INFO_ENABLE,
1041	WMI_PDEV_PARAM_FAST_PWR_TRANSITION,
1042	WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE,
1043	WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE,
1044	WMI_PDEV_PARAM_MESH_MCAST_ENABLE,
1045	WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD = 0xbc,
1046	WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC = 0xbe,
1047	WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT = 0xc6,
1048};
1049
1050enum wmi_tlv_vdev_param {
1051	WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1,
1052	WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD,
1053	WMI_VDEV_PARAM_BEACON_INTERVAL,
1054	WMI_VDEV_PARAM_LISTEN_INTERVAL,
1055	WMI_VDEV_PARAM_MULTICAST_RATE,
1056	WMI_VDEV_PARAM_MGMT_TX_RATE,
1057	WMI_VDEV_PARAM_SLOT_TIME,
1058	WMI_VDEV_PARAM_PREAMBLE,
1059	WMI_VDEV_PARAM_SWBA_TIME,
1060	WMI_VDEV_STATS_UPDATE_PERIOD,
1061	WMI_VDEV_PWRSAVE_AGEOUT_TIME,
1062	WMI_VDEV_HOST_SWBA_INTERVAL,
1063	WMI_VDEV_PARAM_DTIM_PERIOD,
1064	WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT,
1065	WMI_VDEV_PARAM_WDS,
1066	WMI_VDEV_PARAM_ATIM_WINDOW,
1067	WMI_VDEV_PARAM_BMISS_COUNT_MAX,
1068	WMI_VDEV_PARAM_BMISS_FIRST_BCNT,
1069	WMI_VDEV_PARAM_BMISS_FINAL_BCNT,
1070	WMI_VDEV_PARAM_FEATURE_WMM,
1071	WMI_VDEV_PARAM_CHWIDTH,
1072	WMI_VDEV_PARAM_CHEXTOFFSET,
1073	WMI_VDEV_PARAM_DISABLE_HTPROTECTION,
1074	WMI_VDEV_PARAM_STA_QUICKKICKOUT,
1075	WMI_VDEV_PARAM_MGMT_RATE,
1076	WMI_VDEV_PARAM_PROTECTION_MODE,
1077	WMI_VDEV_PARAM_FIXED_RATE,
1078	WMI_VDEV_PARAM_SGI,
1079	WMI_VDEV_PARAM_LDPC,
1080	WMI_VDEV_PARAM_TX_STBC,
1081	WMI_VDEV_PARAM_RX_STBC,
1082	WMI_VDEV_PARAM_INTRA_BSS_FWD,
1083	WMI_VDEV_PARAM_DEF_KEYID,
1084	WMI_VDEV_PARAM_NSS,
1085	WMI_VDEV_PARAM_BCAST_DATA_RATE,
1086	WMI_VDEV_PARAM_MCAST_DATA_RATE,
1087	WMI_VDEV_PARAM_MCAST_INDICATE,
1088	WMI_VDEV_PARAM_DHCP_INDICATE,
1089	WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE,
1090	WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS,
1091	WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS,
1092	WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS,
1093	WMI_VDEV_PARAM_AP_ENABLE_NAWDS,
1094	WMI_VDEV_PARAM_ENABLE_RTSCTS,
1095	WMI_VDEV_PARAM_TXBF,
1096	WMI_VDEV_PARAM_PACKET_POWERSAVE,
1097	WMI_VDEV_PARAM_DROP_UNENCRY,
1098	WMI_VDEV_PARAM_TX_ENCAP_TYPE,
1099	WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS,
1100	WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE,
1101	WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM,
1102	WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE,
1103	WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP,
1104	WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP,
1105	WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE,
1106	WMI_VDEV_PARAM_TX_PWRLIMIT,
1107	WMI_VDEV_PARAM_SNR_NUM_FOR_CAL,
1108	WMI_VDEV_PARAM_ROAM_FW_OFFLOAD,
1109	WMI_VDEV_PARAM_ENABLE_RMC,
1110	WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS,
1111	WMI_VDEV_PARAM_MAX_RATE,
1112	WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE,
1113	WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR,
1114	WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT,
1115	WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE,
1116	WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED,
1117	WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED,
1118	WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED,
1119	WMI_VDEV_PARAM_INACTIVITY_CNT,
1120	WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS,
1121	WMI_VDEV_PARAM_DTIM_POLICY,
1122	WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS,
1123	WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE,
1124	WMI_VDEV_PARAM_RX_LEAK_WINDOW,
1125	WMI_VDEV_PARAM_STATS_AVG_FACTOR,
1126	WMI_VDEV_PARAM_DISCONNECT_TH,
1127	WMI_VDEV_PARAM_RTSCTS_RATE,
1128	WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE,
1129	WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE,
1130	WMI_VDEV_PARAM_TXPOWER_SCALE,
1131	WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB,
1132	WMI_VDEV_PARAM_MCAST2UCAST_SET,
1133	WMI_VDEV_PARAM_RC_NUM_RETRIES,
1134	WMI_VDEV_PARAM_CABQ_MAXDUR,
1135	WMI_VDEV_PARAM_MFPTEST_SET,
1136	WMI_VDEV_PARAM_RTS_FIXED_RATE,
1137	WMI_VDEV_PARAM_VHT_SGIMASK,
1138	WMI_VDEV_PARAM_VHT80_RATEMASK,
1139	WMI_VDEV_PARAM_PROXY_STA,
1140	WMI_VDEV_PARAM_VIRTUAL_CELL_MODE,
1141	WMI_VDEV_PARAM_RX_DECAP_TYPE,
1142	WMI_VDEV_PARAM_BW_NSS_RATEMASK,
1143	WMI_VDEV_PARAM_SENSOR_AP,
1144	WMI_VDEV_PARAM_BEACON_RATE,
1145	WMI_VDEV_PARAM_DTIM_ENABLE_CTS,
1146	WMI_VDEV_PARAM_STA_KICKOUT,
1147	WMI_VDEV_PARAM_CAPABILITIES,
1148	WMI_VDEV_PARAM_TSF_INCREMENT,
1149	WMI_VDEV_PARAM_AMPDU_PER_AC,
1150	WMI_VDEV_PARAM_RX_FILTER,
1151	WMI_VDEV_PARAM_MGMT_TX_POWER,
1152	WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH,
1153	WMI_VDEV_PARAM_AGG_SW_RETRY_TH,
1154	WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS,
1155	WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY,
1156	WMI_VDEV_PARAM_HE_DCM,
1157	WMI_VDEV_PARAM_HE_RANGE_EXT,
1158	WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE,
1159	WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME,
1160	WMI_VDEV_PARAM_HE_LTF = 0x74,
1161	WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_RESPONDER_ROLE = 0x7d,
1162	WMI_VDEV_PARAM_BA_MODE = 0x7e,
1163	WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80,
1164	WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87,
1165	WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99,
1166	WMI_VDEV_PARAM_PROTOTYPE = 0x8000,
1167	WMI_VDEV_PARAM_BSS_COLOR,
1168	WMI_VDEV_PARAM_SET_HEMU_MODE,
1169	WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003,
1170};
1171
1172enum wmi_tlv_peer_flags {
1173	WMI_TLV_PEER_AUTH = 0x00000001,
1174	WMI_TLV_PEER_QOS = 0x00000002,
1175	WMI_TLV_PEER_NEED_PTK_4_WAY = 0x00000004,
1176	WMI_TLV_PEER_NEED_GTK_2_WAY = 0x00000010,
1177	WMI_TLV_PEER_APSD = 0x00000800,
1178	WMI_TLV_PEER_HT = 0x00001000,
1179	WMI_TLV_PEER_40MHZ = 0x00002000,
1180	WMI_TLV_PEER_STBC = 0x00008000,
1181	WMI_TLV_PEER_LDPC = 0x00010000,
1182	WMI_TLV_PEER_DYN_MIMOPS = 0x00020000,
1183	WMI_TLV_PEER_STATIC_MIMOPS = 0x00040000,
1184	WMI_TLV_PEER_SPATIAL_MUX = 0x00200000,
1185	WMI_TLV_PEER_VHT = 0x02000000,
1186	WMI_TLV_PEER_80MHZ = 0x04000000,
1187	WMI_TLV_PEER_PMF = 0x08000000,
1188	WMI_PEER_IS_P2P_CAPABLE = 0x20000000,
1189	WMI_PEER_160MHZ         = 0x40000000,
1190	WMI_PEER_SAFEMODE_EN    = 0x80000000,
1191
1192};
1193
1194/** Enum list of TLV Tags for each parameter structure type. */
1195enum wmi_tlv_tag {
1196	WMI_TAG_LAST_RESERVED = 15,
1197	WMI_TAG_FIRST_ARRAY_ENUM,
1198	WMI_TAG_ARRAY_UINT32 = WMI_TAG_FIRST_ARRAY_ENUM,
1199	WMI_TAG_ARRAY_BYTE,
1200	WMI_TAG_ARRAY_STRUCT,
1201	WMI_TAG_ARRAY_FIXED_STRUCT,
1202	WMI_TAG_LAST_ARRAY_ENUM = 31,
1203	WMI_TAG_SERVICE_READY_EVENT,
1204	WMI_TAG_HAL_REG_CAPABILITIES,
1205	WMI_TAG_WLAN_HOST_MEM_REQ,
1206	WMI_TAG_READY_EVENT,
1207	WMI_TAG_SCAN_EVENT,
1208	WMI_TAG_PDEV_TPC_CONFIG_EVENT,
1209	WMI_TAG_CHAN_INFO_EVENT,
1210	WMI_TAG_COMB_PHYERR_RX_HDR,
1211	WMI_TAG_VDEV_START_RESPONSE_EVENT,
1212	WMI_TAG_VDEV_STOPPED_EVENT,
1213	WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT,
1214	WMI_TAG_PEER_STA_KICKOUT_EVENT,
1215	WMI_TAG_MGMT_RX_HDR,
1216	WMI_TAG_TBTT_OFFSET_EVENT,
1217	WMI_TAG_TX_DELBA_COMPLETE_EVENT,
1218	WMI_TAG_TX_ADDBA_COMPLETE_EVENT,
1219	WMI_TAG_ROAM_EVENT,
1220	WMI_TAG_WOW_EVENT_INFO,
1221	WMI_TAG_WOW_EVENT_INFO_SECTION_BITMAP,
1222	WMI_TAG_RTT_EVENT_HEADER,
1223	WMI_TAG_RTT_ERROR_REPORT_EVENT,
1224	WMI_TAG_RTT_MEAS_EVENT,
1225	WMI_TAG_ECHO_EVENT,
1226	WMI_TAG_FTM_INTG_EVENT,
1227	WMI_TAG_VDEV_GET_KEEPALIVE_EVENT,
1228	WMI_TAG_GPIO_INPUT_EVENT,
1229	WMI_TAG_CSA_EVENT,
1230	WMI_TAG_GTK_OFFLOAD_STATUS_EVENT,
1231	WMI_TAG_IGTK_INFO,
1232	WMI_TAG_DCS_INTERFERENCE_EVENT,
1233	WMI_TAG_ATH_DCS_CW_INT,
1234	WMI_TAG_WLAN_DCS_CW_INT = /* ALIAS */
1235		WMI_TAG_ATH_DCS_CW_INT,
1236	WMI_TAG_ATH_DCS_WLAN_INT_STAT,
1237	WMI_TAG_WLAN_DCS_IM_TGT_STATS_T = /* ALIAS */
1238		WMI_TAG_ATH_DCS_WLAN_INT_STAT,
1239	WMI_TAG_WLAN_PROFILE_CTX_T,
1240	WMI_TAG_WLAN_PROFILE_T,
1241	WMI_TAG_PDEV_QVIT_EVENT,
1242	WMI_TAG_HOST_SWBA_EVENT,
1243	WMI_TAG_TIM_INFO,
1244	WMI_TAG_P2P_NOA_INFO,
1245	WMI_TAG_STATS_EVENT,
1246	WMI_TAG_AVOID_FREQ_RANGES_EVENT,
1247	WMI_TAG_AVOID_FREQ_RANGE_DESC,
1248	WMI_TAG_GTK_REKEY_FAIL_EVENT,
1249	WMI_TAG_INIT_CMD,
1250	WMI_TAG_RESOURCE_CONFIG,
1251	WMI_TAG_WLAN_HOST_MEMORY_CHUNK,
1252	WMI_TAG_START_SCAN_CMD,
1253	WMI_TAG_STOP_SCAN_CMD,
1254	WMI_TAG_SCAN_CHAN_LIST_CMD,
1255	WMI_TAG_CHANNEL,
1256	WMI_TAG_PDEV_SET_REGDOMAIN_CMD,
1257	WMI_TAG_PDEV_SET_PARAM_CMD,
1258	WMI_TAG_PDEV_SET_WMM_PARAMS_CMD,
1259	WMI_TAG_WMM_PARAMS,
1260	WMI_TAG_PDEV_SET_QUIET_CMD,
1261	WMI_TAG_VDEV_CREATE_CMD,
1262	WMI_TAG_VDEV_DELETE_CMD,
1263	WMI_TAG_VDEV_START_REQUEST_CMD,
1264	WMI_TAG_P2P_NOA_DESCRIPTOR,
1265	WMI_TAG_P2P_GO_SET_BEACON_IE,
1266	WMI_TAG_GTK_OFFLOAD_CMD,
1267	WMI_TAG_VDEV_UP_CMD,
1268	WMI_TAG_VDEV_STOP_CMD,
1269	WMI_TAG_VDEV_DOWN_CMD,
1270	WMI_TAG_VDEV_SET_PARAM_CMD,
1271	WMI_TAG_VDEV_INSTALL_KEY_CMD,
1272	WMI_TAG_PEER_CREATE_CMD,
1273	WMI_TAG_PEER_DELETE_CMD,
1274	WMI_TAG_PEER_FLUSH_TIDS_CMD,
1275	WMI_TAG_PEER_SET_PARAM_CMD,
1276	WMI_TAG_PEER_ASSOC_COMPLETE_CMD,
1277	WMI_TAG_VHT_RATE_SET,
1278	WMI_TAG_BCN_TMPL_CMD,
1279	WMI_TAG_PRB_TMPL_CMD,
1280	WMI_TAG_BCN_PRB_INFO,
1281	WMI_TAG_PEER_TID_ADDBA_CMD,
1282	WMI_TAG_PEER_TID_DELBA_CMD,
1283	WMI_TAG_STA_POWERSAVE_MODE_CMD,
1284	WMI_TAG_STA_POWERSAVE_PARAM_CMD,
1285	WMI_TAG_STA_DTIM_PS_METHOD_CMD,
1286	WMI_TAG_ROAM_SCAN_MODE,
1287	WMI_TAG_ROAM_SCAN_RSSI_THRESHOLD,
1288	WMI_TAG_ROAM_SCAN_PERIOD,
1289	WMI_TAG_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
1290	WMI_TAG_PDEV_SUSPEND_CMD,
1291	WMI_TAG_PDEV_RESUME_CMD,
1292	WMI_TAG_ADD_BCN_FILTER_CMD,
1293	WMI_TAG_RMV_BCN_FILTER_CMD,
1294	WMI_TAG_WOW_ENABLE_CMD,
1295	WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD,
1296	WMI_TAG_STA_UAPSD_AUTO_TRIG_CMD,
1297	WMI_TAG_STA_UAPSD_AUTO_TRIG_PARAM,
1298	WMI_TAG_SET_ARP_NS_OFFLOAD_CMD,
1299	WMI_TAG_ARP_OFFLOAD_TUPLE,
1300	WMI_TAG_NS_OFFLOAD_TUPLE,
1301	WMI_TAG_FTM_INTG_CMD,
1302	WMI_TAG_STA_KEEPALIVE_CMD,
1303	WMI_TAG_STA_KEEPALIVE_ARP_RESPONSE,
1304	WMI_TAG_P2P_SET_VENDOR_IE_DATA_CMD,
1305	WMI_TAG_AP_PS_PEER_CMD,
1306	WMI_TAG_PEER_RATE_RETRY_SCHED_CMD,
1307	WMI_TAG_WLAN_PROFILE_TRIGGER_CMD,
1308	WMI_TAG_WLAN_PROFILE_SET_HIST_INTVL_CMD,
1309	WMI_TAG_WLAN_PROFILE_GET_PROF_DATA_CMD,
1310	WMI_TAG_WLAN_PROFILE_ENABLE_PROFILE_ID_CMD,
1311	WMI_TAG_WOW_DEL_PATTERN_CMD,
1312	WMI_TAG_WOW_ADD_DEL_EVT_CMD,
1313	WMI_TAG_RTT_MEASREQ_HEAD,
1314	WMI_TAG_RTT_MEASREQ_BODY,
1315	WMI_TAG_RTT_TSF_CMD,
1316	WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD,
1317	WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD,
1318	WMI_TAG_REQUEST_STATS_CMD,
1319	WMI_TAG_NLO_CONFIG_CMD,
1320	WMI_TAG_NLO_CONFIGURED_PARAMETERS,
1321	WMI_TAG_CSA_OFFLOAD_ENABLE_CMD,
1322	WMI_TAG_CSA_OFFLOAD_CHANSWITCH_CMD,
1323	WMI_TAG_CHATTER_SET_MODE_CMD,
1324	WMI_TAG_ECHO_CMD,
1325	WMI_TAG_VDEV_SET_KEEPALIVE_CMD,
1326	WMI_TAG_VDEV_GET_KEEPALIVE_CMD,
1327	WMI_TAG_FORCE_FW_HANG_CMD,
1328	WMI_TAG_GPIO_CONFIG_CMD,
1329	WMI_TAG_GPIO_OUTPUT_CMD,
1330	WMI_TAG_PEER_ADD_WDS_ENTRY_CMD,
1331	WMI_TAG_PEER_REMOVE_WDS_ENTRY_CMD,
1332	WMI_TAG_BCN_TX_HDR,
1333	WMI_TAG_BCN_SEND_FROM_HOST_CMD,
1334	WMI_TAG_MGMT_TX_HDR,
1335	WMI_TAG_ADDBA_CLEAR_RESP_CMD,
1336	WMI_TAG_ADDBA_SEND_CMD,
1337	WMI_TAG_DELBA_SEND_CMD,
1338	WMI_TAG_ADDBA_SETRESPONSE_CMD,
1339	WMI_TAG_SEND_SINGLEAMSDU_CMD,
1340	WMI_TAG_PDEV_PKTLOG_ENABLE_CMD,
1341	WMI_TAG_PDEV_PKTLOG_DISABLE_CMD,
1342	WMI_TAG_PDEV_SET_HT_IE_CMD,
1343	WMI_TAG_PDEV_SET_VHT_IE_CMD,
1344	WMI_TAG_PDEV_SET_DSCP_TID_MAP_CMD,
1345	WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD,
1346	WMI_TAG_PDEV_GET_TPC_CONFIG_CMD,
1347	WMI_TAG_PDEV_SET_BASE_MACADDR_CMD,
1348	WMI_TAG_PEER_MCAST_GROUP_CMD,
1349	WMI_TAG_ROAM_AP_PROFILE,
1350	WMI_TAG_AP_PROFILE,
1351	WMI_TAG_SCAN_SCH_PRIORITY_TABLE_CMD,
1352	WMI_TAG_PDEV_DFS_ENABLE_CMD,
1353	WMI_TAG_PDEV_DFS_DISABLE_CMD,
1354	WMI_TAG_WOW_ADD_PATTERN_CMD,
1355	WMI_TAG_WOW_BITMAP_PATTERN_T,
1356	WMI_TAG_WOW_IPV4_SYNC_PATTERN_T,
1357	WMI_TAG_WOW_IPV6_SYNC_PATTERN_T,
1358	WMI_TAG_WOW_MAGIC_PATTERN_CMD,
1359	WMI_TAG_SCAN_UPDATE_REQUEST_CMD,
1360	WMI_TAG_CHATTER_PKT_COALESCING_FILTER,
1361	WMI_TAG_CHATTER_COALESCING_ADD_FILTER_CMD,
1362	WMI_TAG_CHATTER_COALESCING_DELETE_FILTER_CMD,
1363	WMI_TAG_CHATTER_COALESCING_QUERY_CMD,
1364	WMI_TAG_TXBF_CMD,
1365	WMI_TAG_DEBUG_LOG_CONFIG_CMD,
1366	WMI_TAG_NLO_EVENT,
1367	WMI_TAG_CHATTER_QUERY_REPLY_EVENT,
1368	WMI_TAG_UPLOAD_H_HDR,
1369	WMI_TAG_CAPTURE_H_EVENT_HDR,
1370	WMI_TAG_VDEV_WNM_SLEEPMODE_CMD,
1371	WMI_TAG_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD,
1372	WMI_TAG_VDEV_WMM_ADDTS_CMD,
1373	WMI_TAG_VDEV_WMM_DELTS_CMD,
1374	WMI_TAG_VDEV_SET_WMM_PARAMS_CMD,
1375	WMI_TAG_TDLS_SET_STATE_CMD,
1376	WMI_TAG_TDLS_PEER_UPDATE_CMD,
1377	WMI_TAG_TDLS_PEER_EVENT,
1378	WMI_TAG_TDLS_PEER_CAPABILITIES,
1379	WMI_TAG_VDEV_MCC_SET_TBTT_MODE_CMD,
1380	WMI_TAG_ROAM_CHAN_LIST,
1381	WMI_TAG_VDEV_MCC_BCN_INTVL_CHANGE_EVENT,
1382	WMI_TAG_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMD,
1383	WMI_TAG_RESMGR_SET_CHAN_TIME_QUOTA_CMD,
1384	WMI_TAG_RESMGR_SET_CHAN_LATENCY_CMD,
1385	WMI_TAG_BA_REQ_SSN_CMD,
1386	WMI_TAG_BA_RSP_SSN_EVENT,
1387	WMI_TAG_STA_SMPS_FORCE_MODE_CMD,
1388	WMI_TAG_SET_MCASTBCAST_FILTER_CMD,
1389	WMI_TAG_P2P_SET_OPPPS_CMD,
1390	WMI_TAG_P2P_SET_NOA_CMD,
1391	WMI_TAG_BA_REQ_SSN_CMD_SUB_STRUCT_PARAM,
1392	WMI_TAG_BA_REQ_SSN_EVENT_SUB_STRUCT_PARAM,
1393	WMI_TAG_STA_SMPS_PARAM_CMD,
1394	WMI_TAG_VDEV_SET_GTX_PARAMS_CMD,
1395	WMI_TAG_MCC_SCHED_TRAFFIC_STATS_CMD,
1396	WMI_TAG_MCC_SCHED_STA_TRAFFIC_STATS,
1397	WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT,
1398	WMI_TAG_P2P_NOA_EVENT,
1399	WMI_TAG_HB_SET_ENABLE_CMD,
1400	WMI_TAG_HB_SET_TCP_PARAMS_CMD,
1401	WMI_TAG_HB_SET_TCP_PKT_FILTER_CMD,
1402	WMI_TAG_HB_SET_UDP_PARAMS_CMD,
1403	WMI_TAG_HB_SET_UDP_PKT_FILTER_CMD,
1404	WMI_TAG_HB_IND_EVENT,
1405	WMI_TAG_TX_PAUSE_EVENT,
1406	WMI_TAG_RFKILL_EVENT,
1407	WMI_TAG_DFS_RADAR_EVENT,
1408	WMI_TAG_DFS_PHYERR_FILTER_ENA_CMD,
1409	WMI_TAG_DFS_PHYERR_FILTER_DIS_CMD,
1410	WMI_TAG_BATCH_SCAN_RESULT_SCAN_LIST,
1411	WMI_TAG_BATCH_SCAN_RESULT_NETWORK_INFO,
1412	WMI_TAG_BATCH_SCAN_ENABLE_CMD,
1413	WMI_TAG_BATCH_SCAN_DISABLE_CMD,
1414	WMI_TAG_BATCH_SCAN_TRIGGER_RESULT_CMD,
1415	WMI_TAG_BATCH_SCAN_ENABLED_EVENT,
1416	WMI_TAG_BATCH_SCAN_RESULT_EVENT,
1417	WMI_TAG_VDEV_PLMREQ_START_CMD,
1418	WMI_TAG_VDEV_PLMREQ_STOP_CMD,
1419	WMI_TAG_THERMAL_MGMT_CMD,
1420	WMI_TAG_THERMAL_MGMT_EVENT,
1421	WMI_TAG_PEER_INFO_REQ_CMD,
1422	WMI_TAG_PEER_INFO_EVENT,
1423	WMI_TAG_PEER_INFO,
1424	WMI_TAG_PEER_TX_FAIL_CNT_THR_EVENT,
1425	WMI_TAG_RMC_SET_MODE_CMD,
1426	WMI_TAG_RMC_SET_ACTION_PERIOD_CMD,
1427	WMI_TAG_RMC_CONFIG_CMD,
1428	WMI_TAG_MHF_OFFLOAD_SET_MODE_CMD,
1429	WMI_TAG_MHF_OFFLOAD_PLUMB_ROUTING_TABLE_CMD,
1430	WMI_TAG_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD,
1431	WMI_TAG_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD,
1432	WMI_TAG_NAN_CMD_PARAM,
1433	WMI_TAG_NAN_EVENT_HDR,
1434	WMI_TAG_PDEV_L1SS_TRACK_EVENT,
1435	WMI_TAG_DIAG_DATA_CONTAINER_EVENT,
1436	WMI_TAG_MODEM_POWER_STATE_CMD_PARAM,
1437	WMI_TAG_PEER_GET_ESTIMATED_LINKSPEED_CMD,
1438	WMI_TAG_PEER_ESTIMATED_LINKSPEED_EVENT,
1439	WMI_TAG_AGGR_STATE_TRIG_EVENT,
1440	WMI_TAG_MHF_OFFLOAD_ROUTING_TABLE_ENTRY,
1441	WMI_TAG_ROAM_SCAN_CMD,
1442	WMI_TAG_REQ_STATS_EXT_CMD,
1443	WMI_TAG_STATS_EXT_EVENT,
1444	WMI_TAG_OBSS_SCAN_ENABLE_CMD,
1445	WMI_TAG_OBSS_SCAN_DISABLE_CMD,
1446	WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT,
1447	WMI_TAG_PDEV_SET_LED_CONFIG_CMD,
1448	WMI_TAG_HOST_AUTO_SHUTDOWN_CFG_CMD,
1449	WMI_TAG_HOST_AUTO_SHUTDOWN_EVENT,
1450	WMI_TAG_UPDATE_WHAL_MIB_STATS_EVENT,
1451	WMI_TAG_CHAN_AVOID_UPDATE_CMD_PARAM,
1452	WMI_TAG_WOW_IOAC_PKT_PATTERN_T,
1453	WMI_TAG_WOW_IOAC_TMR_PATTERN_T,
1454	WMI_TAG_WOW_IOAC_ADD_KEEPALIVE_CMD,
1455	WMI_TAG_WOW_IOAC_DEL_KEEPALIVE_CMD,
1456	WMI_TAG_WOW_IOAC_KEEPALIVE_T,
1457	WMI_TAG_WOW_IOAC_ADD_PATTERN_CMD,
1458	WMI_TAG_WOW_IOAC_DEL_PATTERN_CMD,
1459	WMI_TAG_START_LINK_STATS_CMD,
1460	WMI_TAG_CLEAR_LINK_STATS_CMD,
1461	WMI_TAG_REQUEST_LINK_STATS_CMD,
1462	WMI_TAG_IFACE_LINK_STATS_EVENT,
1463	WMI_TAG_RADIO_LINK_STATS_EVENT,
1464	WMI_TAG_PEER_STATS_EVENT,
1465	WMI_TAG_CHANNEL_STATS,
1466	WMI_TAG_RADIO_LINK_STATS,
1467	WMI_TAG_RATE_STATS,
1468	WMI_TAG_PEER_LINK_STATS,
1469	WMI_TAG_WMM_AC_STATS,
1470	WMI_TAG_IFACE_LINK_STATS,
1471	WMI_TAG_LPI_MGMT_SNOOPING_CONFIG_CMD,
1472	WMI_TAG_LPI_START_SCAN_CMD,
1473	WMI_TAG_LPI_STOP_SCAN_CMD,
1474	WMI_TAG_LPI_RESULT_EVENT,
1475	WMI_TAG_PEER_STATE_EVENT,
1476	WMI_TAG_EXTSCAN_BUCKET_CMD,
1477	WMI_TAG_EXTSCAN_BUCKET_CHANNEL_EVENT,
1478	WMI_TAG_EXTSCAN_START_CMD,
1479	WMI_TAG_EXTSCAN_STOP_CMD,
1480	WMI_TAG_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMD,
1481	WMI_TAG_EXTSCAN_WLAN_CHANGE_BSSID_PARAM_CMD,
1482	WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMD,
1483	WMI_TAG_EXTSCAN_GET_CACHED_RESULTS_CMD,
1484	WMI_TAG_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMD,
1485	WMI_TAG_EXTSCAN_SET_CAPABILITIES_CMD,
1486	WMI_TAG_EXTSCAN_GET_CAPABILITIES_CMD,
1487	WMI_TAG_EXTSCAN_OPERATION_EVENT,
1488	WMI_TAG_EXTSCAN_START_STOP_EVENT,
1489	WMI_TAG_EXTSCAN_TABLE_USAGE_EVENT,
1490	WMI_TAG_EXTSCAN_WLAN_DESCRIPTOR_EVENT,
1491	WMI_TAG_EXTSCAN_RSSI_INFO_EVENT,
1492	WMI_TAG_EXTSCAN_CACHED_RESULTS_EVENT,
1493	WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULTS_EVENT,
1494	WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULT_BSSID_EVENT,
1495	WMI_TAG_EXTSCAN_HOTLIST_MATCH_EVENT,
1496	WMI_TAG_EXTSCAN_CAPABILITIES_EVENT,
1497	WMI_TAG_EXTSCAN_CACHE_CAPABILITIES_EVENT,
1498	WMI_TAG_EXTSCAN_WLAN_CHANGE_MONITOR_CAPABILITIES_EVENT,
1499	WMI_TAG_EXTSCAN_HOTLIST_MONITOR_CAPABILITIES_EVENT,
1500	WMI_TAG_D0_WOW_ENABLE_DISABLE_CMD,
1501	WMI_TAG_D0_WOW_DISABLE_ACK_EVENT,
1502	WMI_TAG_UNIT_TEST_CMD,
1503	WMI_TAG_ROAM_OFFLOAD_TLV_PARAM,
1504	WMI_TAG_ROAM_11I_OFFLOAD_TLV_PARAM,
1505	WMI_TAG_ROAM_11R_OFFLOAD_TLV_PARAM,
1506	WMI_TAG_ROAM_ESE_OFFLOAD_TLV_PARAM,
1507	WMI_TAG_ROAM_SYNCH_EVENT,
1508	WMI_TAG_ROAM_SYNCH_COMPLETE,
1509	WMI_TAG_EXTWOW_ENABLE_CMD,
1510	WMI_TAG_EXTWOW_SET_APP_TYPE1_PARAMS_CMD,
1511	WMI_TAG_EXTWOW_SET_APP_TYPE2_PARAMS_CMD,
1512	WMI_TAG_LPI_STATUS_EVENT,
1513	WMI_TAG_LPI_HANDOFF_EVENT,
1514	WMI_TAG_VDEV_RATE_STATS_EVENT,
1515	WMI_TAG_VDEV_RATE_HT_INFO,
1516	WMI_TAG_RIC_REQUEST,
1517	WMI_TAG_PDEV_GET_TEMPERATURE_CMD,
1518	WMI_TAG_PDEV_TEMPERATURE_EVENT,
1519	WMI_TAG_SET_DHCP_SERVER_OFFLOAD_CMD,
1520	WMI_TAG_TPC_CHAINMASK_CONFIG_CMD,
1521	WMI_TAG_RIC_TSPEC,
1522	WMI_TAG_TPC_CHAINMASK_CONFIG,
1523	WMI_TAG_IPA_OFFLOAD_ENABLE_DISABLE_CMD,
1524	WMI_TAG_SCAN_PROB_REQ_OUI_CMD,
1525	WMI_TAG_KEY_MATERIAL,
1526	WMI_TAG_TDLS_SET_OFFCHAN_MODE_CMD,
1527	WMI_TAG_SET_LED_FLASHING_CMD,
1528	WMI_TAG_MDNS_OFFLOAD_CMD,
1529	WMI_TAG_MDNS_SET_FQDN_CMD,
1530	WMI_TAG_MDNS_SET_RESP_CMD,
1531	WMI_TAG_MDNS_GET_STATS_CMD,
1532	WMI_TAG_MDNS_STATS_EVENT,
1533	WMI_TAG_ROAM_INVOKE_CMD,
1534	WMI_TAG_PDEV_RESUME_EVENT,
1535	WMI_TAG_PDEV_SET_ANTENNA_DIVERSITY_CMD,
1536	WMI_TAG_SAP_OFL_ENABLE_CMD,
1537	WMI_TAG_SAP_OFL_ADD_STA_EVENT,
1538	WMI_TAG_SAP_OFL_DEL_STA_EVENT,
1539	WMI_TAG_APFIND_CMD_PARAM,
1540	WMI_TAG_APFIND_EVENT_HDR,
1541	WMI_TAG_OCB_SET_SCHED_CMD,
1542	WMI_TAG_OCB_SET_SCHED_EVENT,
1543	WMI_TAG_OCB_SET_CONFIG_CMD,
1544	WMI_TAG_OCB_SET_CONFIG_RESP_EVENT,
1545	WMI_TAG_OCB_SET_UTC_TIME_CMD,
1546	WMI_TAG_OCB_START_TIMING_ADVERT_CMD,
1547	WMI_TAG_OCB_STOP_TIMING_ADVERT_CMD,
1548	WMI_TAG_OCB_GET_TSF_TIMER_CMD,
1549	WMI_TAG_OCB_GET_TSF_TIMER_RESP_EVENT,
1550	WMI_TAG_DCC_GET_STATS_CMD,
1551	WMI_TAG_DCC_CHANNEL_STATS_REQUEST,
1552	WMI_TAG_DCC_GET_STATS_RESP_EVENT,
1553	WMI_TAG_DCC_CLEAR_STATS_CMD,
1554	WMI_TAG_DCC_UPDATE_NDL_CMD,
1555	WMI_TAG_DCC_UPDATE_NDL_RESP_EVENT,
1556	WMI_TAG_DCC_STATS_EVENT,
1557	WMI_TAG_OCB_CHANNEL,
1558	WMI_TAG_OCB_SCHEDULE_ELEMENT,
1559	WMI_TAG_DCC_NDL_STATS_PER_CHANNEL,
1560	WMI_TAG_DCC_NDL_CHAN,
1561	WMI_TAG_QOS_PARAMETER,
1562	WMI_TAG_DCC_NDL_ACTIVE_STATE_CONFIG,
1563	WMI_TAG_ROAM_SCAN_EXTENDED_THRESHOLD_PARAM,
1564	WMI_TAG_ROAM_FILTER,
1565	WMI_TAG_PASSPOINT_CONFIG_CMD,
1566	WMI_TAG_PASSPOINT_EVENT_HDR,
1567	WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMD,
1568	WMI_TAG_EXTSCAN_HOTLIST_SSID_MATCH_EVENT,
1569	WMI_TAG_VDEV_TSF_TSTAMP_ACTION_CMD,
1570	WMI_TAG_VDEV_TSF_REPORT_EVENT,
1571	WMI_TAG_GET_FW_MEM_DUMP,
1572	WMI_TAG_UPDATE_FW_MEM_DUMP,
1573	WMI_TAG_FW_MEM_DUMP_PARAMS,
1574	WMI_TAG_DEBUG_MESG_FLUSH,
1575	WMI_TAG_DEBUG_MESG_FLUSH_COMPLETE,
1576	WMI_TAG_PEER_SET_RATE_REPORT_CONDITION,
1577	WMI_TAG_ROAM_SUBNET_CHANGE_CONFIG,
1578	WMI_TAG_VDEV_SET_IE_CMD,
1579	WMI_TAG_RSSI_BREACH_MONITOR_CONFIG,
1580	WMI_TAG_RSSI_BREACH_EVENT,
1581	WMI_TAG_WOW_EVENT_INITIAL_WAKEUP,
1582	WMI_TAG_SOC_SET_PCL_CMD,
1583	WMI_TAG_SOC_SET_HW_MODE_CMD,
1584	WMI_TAG_SOC_SET_HW_MODE_RESPONSE_EVENT,
1585	WMI_TAG_SOC_HW_MODE_TRANSITION_EVENT,
1586	WMI_TAG_VDEV_TXRX_STREAMS,
1587	WMI_TAG_SOC_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY,
1588	WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_CMD,
1589	WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_RESPONSE_EVENT,
1590	WMI_TAG_WOW_IOAC_SOCK_PATTERN_T,
1591	WMI_TAG_WOW_ENABLE_ICMPV6_NA_FLT_CMD,
1592	WMI_TAG_DIAG_EVENT_LOG_CONFIG,
1593	WMI_TAG_DIAG_EVENT_LOG_SUPPORTED_EVENT_FIXED_PARAMS,
1594	WMI_TAG_PACKET_FILTER_CONFIG,
1595	WMI_TAG_PACKET_FILTER_ENABLE,
1596	WMI_TAG_SAP_SET_BLACKLIST_PARAM_CMD,
1597	WMI_TAG_MGMT_TX_SEND_CMD,
1598	WMI_TAG_MGMT_TX_COMPL_EVENT,
1599	WMI_TAG_SOC_SET_ANTENNA_MODE_CMD,
1600	WMI_TAG_WOW_UDP_SVC_OFLD_CMD,
1601	WMI_TAG_LRO_INFO_CMD,
1602	WMI_TAG_ROAM_EARLYSTOP_RSSI_THRES_PARAM,
1603	WMI_TAG_SERVICE_READY_EXT_EVENT,
1604	WMI_TAG_MAWC_SENSOR_REPORT_IND_CMD,
1605	WMI_TAG_MAWC_ENABLE_SENSOR_EVENT,
1606	WMI_TAG_ROAM_CONFIGURE_MAWC_CMD,
1607	WMI_TAG_NLO_CONFIGURE_MAWC_CMD,
1608	WMI_TAG_EXTSCAN_CONFIGURE_MAWC_CMD,
1609	WMI_TAG_PEER_ASSOC_CONF_EVENT,
1610	WMI_TAG_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD,
1611	WMI_TAG_AP_PS_EGAP_PARAM_CMD,
1612	WMI_TAG_AP_PS_EGAP_INFO_EVENT,
1613	WMI_TAG_PMF_OFFLOAD_SET_SA_QUERY_CMD,
1614	WMI_TAG_TRANSFER_DATA_TO_FLASH_CMD,
1615	WMI_TAG_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT,
1616	WMI_TAG_SCPC_EVENT,
1617	WMI_TAG_AP_PS_EGAP_INFO_CHAINMASK_LIST,
1618	WMI_TAG_STA_SMPS_FORCE_MODE_COMPLETE_EVENT,
1619	WMI_TAG_BPF_GET_CAPABILITY_CMD,
1620	WMI_TAG_BPF_CAPABILITY_INFO_EVT,
1621	WMI_TAG_BPF_GET_VDEV_STATS_CMD,
1622	WMI_TAG_BPF_VDEV_STATS_INFO_EVT,
1623	WMI_TAG_BPF_SET_VDEV_INSTRUCTIONS_CMD,
1624	WMI_TAG_BPF_DEL_VDEV_INSTRUCTIONS_CMD,
1625	WMI_TAG_VDEV_DELETE_RESP_EVENT,
1626	WMI_TAG_PEER_DELETE_RESP_EVENT,
1627	WMI_TAG_ROAM_DENSE_THRES_PARAM,
1628	WMI_TAG_ENLO_CANDIDATE_SCORE_PARAM,
1629	WMI_TAG_PEER_UPDATE_WDS_ENTRY_CMD,
1630	WMI_TAG_VDEV_CONFIG_RATEMASK,
1631	WMI_TAG_PDEV_FIPS_CMD,
1632	WMI_TAG_PDEV_SMART_ANT_ENABLE_CMD,
1633	WMI_TAG_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD,
1634	WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_CMD,
1635	WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD,
1636	WMI_TAG_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD,
1637	WMI_TAG_PDEV_SET_ANT_SWITCH_TBL_CMD,
1638	WMI_TAG_PDEV_SET_CTL_TABLE_CMD,
1639	WMI_TAG_PDEV_SET_MIMOGAIN_TABLE_CMD,
1640	WMI_TAG_FWTEST_SET_PARAM_CMD,
1641	WMI_TAG_PEER_ATF_REQUEST,
1642	WMI_TAG_VDEV_ATF_REQUEST,
1643	WMI_TAG_PDEV_GET_ANI_CCK_CONFIG_CMD,
1644	WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD,
1645	WMI_TAG_INST_RSSI_STATS_RESP,
1646	WMI_TAG_MED_UTIL_REPORT_EVENT,
1647	WMI_TAG_PEER_STA_PS_STATECHANGE_EVENT,
1648	WMI_TAG_WDS_ADDR_EVENT,
1649	WMI_TAG_PEER_RATECODE_LIST_EVENT,
1650	WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT,
1651	WMI_TAG_PDEV_TPC_EVENT,
1652	WMI_TAG_ANI_OFDM_EVENT,
1653	WMI_TAG_ANI_CCK_EVENT,
1654	WMI_TAG_PDEV_CHANNEL_HOPPING_EVENT,
1655	WMI_TAG_PDEV_FIPS_EVENT,
1656	WMI_TAG_ATF_PEER_INFO,
1657	WMI_TAG_PDEV_GET_TPC_CMD,
1658	WMI_TAG_VDEV_FILTER_NRP_CONFIG_CMD,
1659	WMI_TAG_QBOOST_CFG_CMD,
1660	WMI_TAG_PDEV_SMART_ANT_GPIO_HANDLE,
1661	WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES,
1662	WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM,
1663	WMI_TAG_PDEV_SET_ANT_CTRL_CHAIN,
1664	WMI_TAG_PEER_CCK_OFDM_RATE_INFO,
1665	WMI_TAG_PEER_MCS_RATE_INFO,
1666	WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR,
1667	WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM,
1668	WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM,
1669	WMI_TAG_MU_REPORT_TOTAL_MU,
1670	WMI_TAG_VDEV_SET_DSCP_TID_MAP_CMD,
1671	WMI_TAG_ROAM_SET_MBO,
1672	WMI_TAG_MIB_STATS_ENABLE_CMD,
1673	WMI_TAG_NAN_DISC_IFACE_CREATED_EVENT,
1674	WMI_TAG_NAN_DISC_IFACE_DELETED_EVENT,
1675	WMI_TAG_NAN_STARTED_CLUSTER_EVENT,
1676	WMI_TAG_NAN_JOINED_CLUSTER_EVENT,
1677	WMI_TAG_NDI_GET_CAP_REQ,
1678	WMI_TAG_NDP_INITIATOR_REQ,
1679	WMI_TAG_NDP_RESPONDER_REQ,
1680	WMI_TAG_NDP_END_REQ,
1681	WMI_TAG_NDI_CAP_RSP_EVENT,
1682	WMI_TAG_NDP_INITIATOR_RSP_EVENT,
1683	WMI_TAG_NDP_RESPONDER_RSP_EVENT,
1684	WMI_TAG_NDP_END_RSP_EVENT,
1685	WMI_TAG_NDP_INDICATION_EVENT,
1686	WMI_TAG_NDP_CONFIRM_EVENT,
1687	WMI_TAG_NDP_END_INDICATION_EVENT,
1688	WMI_TAG_VDEV_SET_QUIET_CMD,
1689	WMI_TAG_PDEV_SET_PCL_CMD,
1690	WMI_TAG_PDEV_SET_HW_MODE_CMD,
1691	WMI_TAG_PDEV_SET_MAC_CONFIG_CMD,
1692	WMI_TAG_PDEV_SET_ANTENNA_MODE_CMD,
1693	WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_EVENT,
1694	WMI_TAG_PDEV_HW_MODE_TRANSITION_EVENT,
1695	WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY,
1696	WMI_TAG_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT,
1697	WMI_TAG_COEX_CONFIG_CMD,
1698	WMI_TAG_CONFIG_ENHANCED_MCAST_FILTER,
1699	WMI_TAG_CHAN_AVOID_RPT_ALLOW_CMD,
1700	WMI_TAG_SET_PERIODIC_CHANNEL_STATS_CONFIG,
1701	WMI_TAG_VDEV_SET_CUSTOM_AGGR_SIZE_CMD,
1702	WMI_TAG_PDEV_WAL_POWER_DEBUG_CMD,
1703	WMI_TAG_MAC_PHY_CAPABILITIES,
1704	WMI_TAG_HW_MODE_CAPABILITIES,
1705	WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS,
1706	WMI_TAG_HAL_REG_CAPABILITIES_EXT,
1707	WMI_TAG_SOC_HAL_REG_CAPABILITIES,
1708	WMI_TAG_VDEV_WISA_CMD,
1709	WMI_TAG_TX_POWER_LEVEL_STATS_EVT,
1710	WMI_TAG_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV,
1711	WMI_TAG_SCAN_ADAPTIVE_DWELL_CONFIG,
1712	WMI_TAG_WOW_SET_ACTION_WAKE_UP_CMD,
1713	WMI_TAG_NDP_END_RSP_PER_NDI,
1714	WMI_TAG_PEER_BWF_REQUEST,
1715	WMI_TAG_BWF_PEER_INFO,
1716	WMI_TAG_DBGLOG_TIME_STAMP_SYNC_CMD,
1717	WMI_TAG_RMC_SET_LEADER_CMD,
1718	WMI_TAG_RMC_MANUAL_LEADER_EVENT,
1719	WMI_TAG_PER_CHAIN_RSSI_STATS,
1720	WMI_TAG_RSSI_STATS,
1721	WMI_TAG_P2P_LO_START_CMD,
1722	WMI_TAG_P2P_LO_STOP_CMD,
1723	WMI_TAG_P2P_LO_STOPPED_EVENT,
1724	WMI_TAG_REORDER_QUEUE_SETUP_CMD,
1725	WMI_TAG_REORDER_QUEUE_REMOVE_CMD,
1726	WMI_TAG_SET_MULTIPLE_MCAST_FILTER_CMD,
1727	WMI_TAG_MGMT_TX_COMPL_BUNDLE_EVENT,
1728	WMI_TAG_READ_DATA_FROM_FLASH_CMD,
1729	WMI_TAG_READ_DATA_FROM_FLASH_EVENT,
1730	WMI_TAG_PDEV_SET_REORDER_TIMEOUT_VAL_CMD,
1731	WMI_TAG_PEER_SET_RX_BLOCKSIZE_CMD,
1732	WMI_TAG_PDEV_SET_WAKEUP_CONFIG_CMDID,
1733	WMI_TAG_TLV_BUF_LEN_PARAM,
1734	WMI_TAG_SERVICE_AVAILABLE_EVENT,
1735	WMI_TAG_PEER_ANTDIV_INFO_REQ_CMD,
1736	WMI_TAG_PEER_ANTDIV_INFO_EVENT,
1737	WMI_TAG_PEER_ANTDIV_INFO,
1738	WMI_TAG_PDEV_GET_ANTDIV_STATUS_CMD,
1739	WMI_TAG_PDEV_ANTDIV_STATUS_EVENT,
1740	WMI_TAG_MNT_FILTER_CMD,
1741	WMI_TAG_GET_CHIP_POWER_STATS_CMD,
1742	WMI_TAG_PDEV_CHIP_POWER_STATS_EVENT,
1743	WMI_TAG_COEX_GET_ANTENNA_ISOLATION_CMD,
1744	WMI_TAG_COEX_REPORT_ISOLATION_EVENT,
1745	WMI_TAG_CHAN_CCA_STATS,
1746	WMI_TAG_PEER_SIGNAL_STATS,
1747	WMI_TAG_TX_STATS,
1748	WMI_TAG_PEER_AC_TX_STATS,
1749	WMI_TAG_RX_STATS,
1750	WMI_TAG_PEER_AC_RX_STATS,
1751	WMI_TAG_REPORT_STATS_EVENT,
1752	WMI_TAG_CHAN_CCA_STATS_THRESH,
1753	WMI_TAG_PEER_SIGNAL_STATS_THRESH,
1754	WMI_TAG_TX_STATS_THRESH,
1755	WMI_TAG_RX_STATS_THRESH,
1756	WMI_TAG_PDEV_SET_STATS_THRESHOLD_CMD,
1757	WMI_TAG_REQUEST_WLAN_STATS_CMD,
1758	WMI_TAG_RX_AGGR_FAILURE_EVENT,
1759	WMI_TAG_RX_AGGR_FAILURE_INFO,
1760	WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD,
1761	WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT,
1762	WMI_TAG_PDEV_BAND_TO_MAC,
1763	WMI_TAG_TBTT_OFFSET_INFO,
1764	WMI_TAG_TBTT_OFFSET_EXT_EVENT,
1765	WMI_TAG_SAR_LIMITS_CMD,
1766	WMI_TAG_SAR_LIMIT_CMD_ROW,
1767	WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD,
1768	WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD,
1769	WMI_TAG_VDEV_ADFS_CH_CFG_CMD,
1770	WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD,
1771	WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT,
1772	WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT,
1773	WMI_TAG_VDEV_DFS_CAC_COMPLETE_EVENT,
1774	WMI_TAG_VENDOR_OUI,
1775	WMI_TAG_REQUEST_RCPI_CMD,
1776	WMI_TAG_UPDATE_RCPI_EVENT,
1777	WMI_TAG_REQUEST_PEER_STATS_INFO_CMD,
1778	WMI_TAG_PEER_STATS_INFO,
1779	WMI_TAG_PEER_STATS_INFO_EVENT,
1780	WMI_TAG_PKGID_EVENT,
1781	WMI_TAG_CONNECTED_NLO_RSSI_PARAMS,
1782	WMI_TAG_SET_CURRENT_COUNTRY_CMD,
1783	WMI_TAG_REGULATORY_RULE_STRUCT,
1784	WMI_TAG_REG_CHAN_LIST_CC_EVENT,
1785	WMI_TAG_11D_SCAN_START_CMD,
1786	WMI_TAG_11D_SCAN_STOP_CMD,
1787	WMI_TAG_11D_NEW_COUNTRY_EVENT,
1788	WMI_TAG_REQUEST_RADIO_CHAN_STATS_CMD,
1789	WMI_TAG_RADIO_CHAN_STATS,
1790	WMI_TAG_RADIO_CHAN_STATS_EVENT,
1791	WMI_TAG_ROAM_PER_CONFIG,
1792	WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD,
1793	WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT,
1794	WMI_TAG_BPF_SET_VDEV_ACTIVE_MODE_CMD,
1795	WMI_TAG_HW_DATA_FILTER_CMD,
1796	WMI_TAG_CONNECTED_NLO_BSS_BAND_RSSI_PREF,
1797	WMI_TAG_PEER_OPER_MODE_CHANGE_EVENT,
1798	WMI_TAG_CHIP_POWER_SAVE_FAILURE_DETECTED,
1799	WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD,
1800	WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT,
1801	WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD,
1802	WMI_TAG_PDEV_CHECK_CAL_VERSION_CMD,
1803	WMI_TAG_PDEV_CHECK_CAL_VERSION_EVENT,
1804	WMI_TAG_PDEV_SET_DIVERSITY_GAIN_CMD,
1805	WMI_TAG_MAC_PHY_CHAINMASK_COMBO,
1806	WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY,
1807	WMI_TAG_VDEV_SET_ARP_STATS_CMD,
1808	WMI_TAG_VDEV_GET_ARP_STATS_CMD,
1809	WMI_TAG_VDEV_GET_ARP_STATS_EVENT,
1810	WMI_TAG_IFACE_OFFLOAD_STATS,
1811	WMI_TAG_REQUEST_STATS_CMD_SUB_STRUCT_PARAM,
1812	WMI_TAG_RSSI_CTL_EXT,
1813	WMI_TAG_SINGLE_PHYERR_EXT_RX_HDR,
1814	WMI_TAG_COEX_BT_ACTIVITY_EVENT,
1815	WMI_TAG_VDEV_GET_TX_POWER_CMD,
1816	WMI_TAG_VDEV_TX_POWER_EVENT,
1817	WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT,
1818	WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD,
1819	WMI_TAG_TX_SEND_PARAMS,
1820	WMI_TAG_HE_RATE_SET,
1821	WMI_TAG_CONGESTION_STATS,
1822	WMI_TAG_SET_INIT_COUNTRY_CMD,
1823	WMI_TAG_SCAN_DBS_DUTY_CYCLE,
1824	WMI_TAG_SCAN_DBS_DUTY_CYCLE_PARAM_TLV,
1825	WMI_TAG_PDEV_DIV_GET_RSSI_ANTID,
1826	WMI_TAG_THERM_THROT_CONFIG_REQUEST,
1827	WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO,
1828	WMI_TAG_THERM_THROT_STATS_EVENT,
1829	WMI_TAG_THERM_THROT_LEVEL_STATS_INFO,
1830	WMI_TAG_PDEV_DIV_RSSI_ANTID_EVENT,
1831	WMI_TAG_OEM_DMA_RING_CAPABILITIES,
1832	WMI_TAG_OEM_DMA_RING_CFG_REQ,
1833	WMI_TAG_OEM_DMA_RING_CFG_RSP,
1834	WMI_TAG_OEM_INDIRECT_DATA,
1835	WMI_TAG_OEM_DMA_BUF_RELEASE,
1836	WMI_TAG_OEM_DMA_BUF_RELEASE_ENTRY,
1837	WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST,
1838	WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT,
1839	WMI_TAG_ROAM_LCA_DISALLOW_CONFIG,
1840	WMI_TAG_VDEV_LIMIT_OFFCHAN_CMD,
1841	WMI_TAG_ROAM_RSSI_REJECTION_OCE_CONFIG,
1842	WMI_TAG_UNIT_TEST_EVENT,
1843	WMI_TAG_ROAM_FILS_OFFLOAD,
1844	WMI_TAG_PDEV_UPDATE_PMK_CACHE_CMD,
1845	WMI_TAG_PMK_CACHE,
1846	WMI_TAG_PDEV_UPDATE_FILS_HLP_PKT_CMD,
1847	WMI_TAG_ROAM_FILS_SYNCH,
1848	WMI_TAG_GTK_OFFLOAD_EXTENDED,
1849	WMI_TAG_ROAM_BG_SCAN_ROAMING,
1850	WMI_TAG_OIC_PING_OFFLOAD_PARAMS_CMD,
1851	WMI_TAG_OIC_PING_OFFLOAD_SET_ENABLE_CMD,
1852	WMI_TAG_OIC_PING_HANDOFF_EVENT,
1853	WMI_TAG_DHCP_LEASE_RENEW_OFFLOAD_CMD,
1854	WMI_TAG_DHCP_LEASE_RENEW_EVENT,
1855	WMI_TAG_BTM_CONFIG,
1856	WMI_TAG_DEBUG_MESG_FW_DATA_STALL,
1857	WMI_TAG_WLM_CONFIG_CMD,
1858	WMI_TAG_PDEV_UPDATE_CTLTABLE_REQUEST,
1859	WMI_TAG_PDEV_UPDATE_CTLTABLE_EVENT,
1860	WMI_TAG_ROAM_CND_SCORING_PARAM,
1861	WMI_TAG_PDEV_CONFIG_VENDOR_OUI_ACTION,
1862	WMI_TAG_VENDOR_OUI_EXT,
1863	WMI_TAG_ROAM_SYNCH_FRAME_EVENT,
1864	WMI_TAG_FD_SEND_FROM_HOST_CMD,
1865	WMI_TAG_ENABLE_FILS_CMD,
1866	WMI_TAG_HOST_SWFDA_EVENT,
1867	WMI_TAG_BCN_OFFLOAD_CTRL_CMD,
1868	WMI_TAG_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMD,
1869	WMI_TAG_STATS_PERIOD,
1870	WMI_TAG_NDL_SCHEDULE_UPDATE,
1871	WMI_TAG_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMD,
1872	WMI_TAG_MSDUQ_QDEPTH_THRESH_UPDATE,
1873	WMI_TAG_PDEV_SET_RX_FILTER_PROMISCUOUS_CMD,
1874	WMI_TAG_SAR2_RESULT_EVENT,
1875	WMI_TAG_SAR_CAPABILITIES,
1876	WMI_TAG_SAP_OBSS_DETECTION_CFG_CMD,
1877	WMI_TAG_SAP_OBSS_DETECTION_INFO_EVT,
1878	WMI_TAG_DMA_RING_CAPABILITIES,
1879	WMI_TAG_DMA_RING_CFG_REQ,
1880	WMI_TAG_DMA_RING_CFG_RSP,
1881	WMI_TAG_DMA_BUF_RELEASE,
1882	WMI_TAG_DMA_BUF_RELEASE_ENTRY,
1883	WMI_TAG_SAR_GET_LIMITS_CMD,
1884	WMI_TAG_SAR_GET_LIMITS_EVENT,
1885	WMI_TAG_SAR_GET_LIMITS_EVENT_ROW,
1886	WMI_TAG_OFFLOAD_11K_REPORT,
1887	WMI_TAG_INVOKE_NEIGHBOR_REPORT,
1888	WMI_TAG_NEIGHBOR_REPORT_OFFLOAD,
1889	WMI_TAG_VDEV_SET_CONNECTIVITY_CHECK_STATS,
1890	WMI_TAG_VDEV_GET_CONNECTIVITY_CHECK_STATS,
1891	WMI_TAG_BPF_SET_VDEV_ENABLE_CMD,
1892	WMI_TAG_BPF_SET_VDEV_WORK_MEMORY_CMD,
1893	WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_CMD,
1894	WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_RESP_EVT,
1895	WMI_TAG_PDEV_GET_NFCAL_POWER,
1896	WMI_TAG_BSS_COLOR_CHANGE_ENABLE,
1897	WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG,
1898	WMI_TAG_OBSS_COLOR_COLLISION_EVT,
1899	WMI_TAG_RUNTIME_DPD_RECAL_CMD,
1900	WMI_TAG_TWT_ENABLE_CMD,
1901	WMI_TAG_TWT_DISABLE_CMD,
1902	WMI_TAG_TWT_ADD_DIALOG_CMD,
1903	WMI_TAG_TWT_DEL_DIALOG_CMD,
1904	WMI_TAG_TWT_PAUSE_DIALOG_CMD,
1905	WMI_TAG_TWT_RESUME_DIALOG_CMD,
1906	WMI_TAG_TWT_ENABLE_COMPLETE_EVENT,
1907	WMI_TAG_TWT_DISABLE_COMPLETE_EVENT,
1908	WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT,
1909	WMI_TAG_TWT_DEL_DIALOG_COMPLETE_EVENT,
1910	WMI_TAG_TWT_PAUSE_DIALOG_COMPLETE_EVENT,
1911	WMI_TAG_TWT_RESUME_DIALOG_COMPLETE_EVENT,
1912	WMI_TAG_REQUEST_ROAM_SCAN_STATS_CMD,
1913	WMI_TAG_ROAM_SCAN_STATS_EVENT,
1914	WMI_TAG_PEER_TID_CONFIGURATIONS_CMD,
1915	WMI_TAG_VDEV_SET_CUSTOM_SW_RETRY_TH_CMD,
1916	WMI_TAG_GET_TPC_POWER_CMD,
1917	WMI_TAG_GET_TPC_POWER_EVENT,
1918	WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA,
1919	WMI_TAG_MOTION_DET_CONFIG_PARAMS_CMD,
1920	WMI_TAG_MOTION_DET_BASE_LINE_CONFIG_PARAMS_CMD,
1921	WMI_TAG_MOTION_DET_START_STOP_CMD,
1922	WMI_TAG_MOTION_DET_BASE_LINE_START_STOP_CMD,
1923	WMI_TAG_MOTION_DET_EVENT,
1924	WMI_TAG_MOTION_DET_BASE_LINE_EVENT,
1925	WMI_TAG_NDP_TRANSPORT_IP,
1926	WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD,
1927	WMI_TAG_ESP_ESTIMATE_EVENT,
1928	WMI_TAG_NAN_HOST_CONFIG,
1929	WMI_TAG_SPECTRAL_BIN_SCALING_PARAMS,
1930	WMI_TAG_PEER_CFR_CAPTURE_CMD,
1931	WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD,
1932	WMI_TAG_CHAN_WIDTH_PEER_LIST,
1933	WMI_TAG_OBSS_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMD,
1934	WMI_TAG_PDEV_HE_TB_ACTION_FRM_CMD,
1935	WMI_TAG_PEER_EXTD2_STATS,
1936	WMI_TAG_HPCS_PULSE_START_CMD,
1937	WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT,
1938	WMI_TAG_VDEV_CHAINMASK_CONFIG_CMD,
1939	WMI_TAG_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMD,
1940	WMI_TAG_NAN_EVENT_INFO,
1941	WMI_TAG_NDP_CHANNEL_INFO,
1942	WMI_TAG_NDP_CMD,
1943	WMI_TAG_NDP_EVENT,
1944	WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301,
1945	WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO,
1946	WMI_TAG_FILS_DISCOVERY_TMPL_CMD = 0x344,
1947	WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD = 0x37b,
1948	WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD,
1949	WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD = 0x381,
1950	WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD,
1951	WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD,
1952	WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD,
1953	WMI_TAG_REGULATORY_RULE_EXT_STRUCT = 0x3A9,
1954	WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT,
1955	WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD = 0x3D8,
1956	WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD,
1957	WMI_TAG_MAX
1958};
1959
1960enum wmi_tlv_service {
1961	WMI_TLV_SERVICE_BEACON_OFFLOAD = 0,
1962	WMI_TLV_SERVICE_SCAN_OFFLOAD = 1,
1963	WMI_TLV_SERVICE_ROAM_SCAN_OFFLOAD = 2,
1964	WMI_TLV_SERVICE_BCN_MISS_OFFLOAD = 3,
1965	WMI_TLV_SERVICE_STA_PWRSAVE = 4,
1966	WMI_TLV_SERVICE_STA_ADVANCED_PWRSAVE = 5,
1967	WMI_TLV_SERVICE_AP_UAPSD = 6,
1968	WMI_TLV_SERVICE_AP_DFS = 7,
1969	WMI_TLV_SERVICE_11AC = 8,
1970	WMI_TLV_SERVICE_BLOCKACK = 9,
1971	WMI_TLV_SERVICE_PHYERR = 10,
1972	WMI_TLV_SERVICE_BCN_FILTER = 11,
1973	WMI_TLV_SERVICE_RTT = 12,
1974	WMI_TLV_SERVICE_WOW = 13,
1975	WMI_TLV_SERVICE_RATECTRL_CACHE = 14,
1976	WMI_TLV_SERVICE_IRAM_TIDS = 15,
1977	WMI_TLV_SERVICE_ARPNS_OFFLOAD = 16,
1978	WMI_TLV_SERVICE_NLO = 17,
1979	WMI_TLV_SERVICE_GTK_OFFLOAD = 18,
1980	WMI_TLV_SERVICE_SCAN_SCH = 19,
1981	WMI_TLV_SERVICE_CSA_OFFLOAD = 20,
1982	WMI_TLV_SERVICE_CHATTER = 21,
1983	WMI_TLV_SERVICE_COEX_FREQAVOID = 22,
1984	WMI_TLV_SERVICE_PACKET_POWER_SAVE = 23,
1985	WMI_TLV_SERVICE_FORCE_FW_HANG = 24,
1986	WMI_TLV_SERVICE_GPIO = 25,
1987	WMI_TLV_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26,
1988	WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27,
1989	WMI_STA_UAPSD_VAR_AUTO_TRIG = 28,
1990	WMI_TLV_SERVICE_STA_KEEP_ALIVE = 29,
1991	WMI_TLV_SERVICE_TX_ENCAP = 30,
1992	WMI_TLV_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31,
1993	WMI_TLV_SERVICE_EARLY_RX = 32,
1994	WMI_TLV_SERVICE_STA_SMPS = 33,
1995	WMI_TLV_SERVICE_FWTEST = 34,
1996	WMI_TLV_SERVICE_STA_WMMAC = 35,
1997	WMI_TLV_SERVICE_TDLS = 36,
1998	WMI_TLV_SERVICE_BURST = 37,
1999	WMI_TLV_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38,
2000	WMI_TLV_SERVICE_ADAPTIVE_OCS = 39,
2001	WMI_TLV_SERVICE_BA_SSN_SUPPORT = 40,
2002	WMI_TLV_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41,
2003	WMI_TLV_SERVICE_WLAN_HB = 42,
2004	WMI_TLV_SERVICE_LTE_ANT_SHARE_SUPPORT = 43,
2005	WMI_TLV_SERVICE_BATCH_SCAN = 44,
2006	WMI_TLV_SERVICE_QPOWER = 45,
2007	WMI_TLV_SERVICE_PLMREQ = 46,
2008	WMI_TLV_SERVICE_THERMAL_MGMT = 47,
2009	WMI_TLV_SERVICE_RMC = 48,
2010	WMI_TLV_SERVICE_MHF_OFFLOAD = 49,
2011	WMI_TLV_SERVICE_COEX_SAR = 50,
2012	WMI_TLV_SERVICE_BCN_TXRATE_OVERRIDE = 51,
2013	WMI_TLV_SERVICE_NAN = 52,
2014	WMI_TLV_SERVICE_L1SS_STAT = 53,
2015	WMI_TLV_SERVICE_ESTIMATE_LINKSPEED = 54,
2016	WMI_TLV_SERVICE_OBSS_SCAN = 55,
2017	WMI_TLV_SERVICE_TDLS_OFFCHAN = 56,
2018	WMI_TLV_SERVICE_TDLS_UAPSD_BUFFER_STA = 57,
2019	WMI_TLV_SERVICE_TDLS_UAPSD_SLEEP_STA = 58,
2020	WMI_TLV_SERVICE_IBSS_PWRSAVE = 59,
2021	WMI_TLV_SERVICE_LPASS = 60,
2022	WMI_TLV_SERVICE_EXTSCAN = 61,
2023	WMI_TLV_SERVICE_D0WOW = 62,
2024	WMI_TLV_SERVICE_HSOFFLOAD = 63,
2025	WMI_TLV_SERVICE_ROAM_HO_OFFLOAD = 64,
2026	WMI_TLV_SERVICE_RX_FULL_REORDER = 65,
2027	WMI_TLV_SERVICE_DHCP_OFFLOAD = 66,
2028	WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67,
2029	WMI_TLV_SERVICE_MDNS_OFFLOAD = 68,
2030	WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD = 69,
2031	WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70,
2032	WMI_TLV_SERVICE_OCB = 71,
2033	WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD = 72,
2034	WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73,
2035	WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD = 74,
2036	WMI_TLV_SERVICE_MGMT_TX_HTT = 75,
2037	WMI_TLV_SERVICE_MGMT_TX_WMI = 76,
2038	WMI_TLV_SERVICE_EXT_MSG = 77,
2039	WMI_TLV_SERVICE_MAWC = 78,
2040	WMI_TLV_SERVICE_PEER_ASSOC_CONF = 79,
2041	WMI_TLV_SERVICE_EGAP = 80,
2042	WMI_TLV_SERVICE_STA_PMF_OFFLOAD = 81,
2043	WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY = 82,
2044	WMI_TLV_SERVICE_ENHANCED_PROXY_STA = 83,
2045	WMI_TLV_SERVICE_ATF = 84,
2046	WMI_TLV_SERVICE_COEX_GPIO = 85,
2047	WMI_TLV_SERVICE_AUX_SPECTRAL_INTF = 86,
2048	WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF = 87,
2049	WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64 = 88,
2050	WMI_TLV_SERVICE_ENTERPRISE_MESH = 89,
2051	WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT = 90,
2052	WMI_TLV_SERVICE_BPF_OFFLOAD = 91,
2053	WMI_TLV_SERVICE_SYNC_DELETE_CMDS = 92,
2054	WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93,
2055	WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94,
2056	WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95,
2057	WMI_TLV_SERVICE_NAN_DATA = 96,
2058	WMI_TLV_SERVICE_NAN_RTT = 97,
2059	WMI_TLV_SERVICE_11AX = 98,
2060	WMI_TLV_SERVICE_DEPRECATED_REPLACE = 99,
2061	WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100,
2062	WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER = 101,
2063	WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102,
2064	WMI_TLV_SERVICE_MESH_11S = 103,
2065	WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104,
2066	WMI_TLV_SERVICE_VDEV_RX_FILTER = 105,
2067	WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106,
2068	WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107,
2069	WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108,
2070	WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER = 109,
2071	WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT = 110,
2072	WMI_TLV_SERVICE_WLAN_STATS_REPORT = 111,
2073	WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112,
2074	WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD = 113,
2075	WMI_TLV_SERVICE_RCPI_SUPPORT = 114,
2076	WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT = 115,
2077	WMI_TLV_SERVICE_PEER_STATS_INFO = 116,
2078	WMI_TLV_SERVICE_REGULATORY_DB = 117,
2079	WMI_TLV_SERVICE_11D_OFFLOAD = 118,
2080	WMI_TLV_SERVICE_HW_DATA_FILTERING = 119,
2081	WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART = 120,
2082	WMI_TLV_SERVICE_PKT_ROUTING = 121,
2083	WMI_TLV_SERVICE_CHECK_CAL_VERSION = 122,
2084	WMI_TLV_SERVICE_OFFCHAN_TX_WMI = 123,
2085	WMI_TLV_SERVICE_8SS_TX_BFEE  =  124,
2086	WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT = 125,
2087	WMI_TLV_SERVICE_ACK_TIMEOUT = 126,
2088	WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127,
2089
2090	/* The first 128 bits */
2091	WMI_MAX_SERVICE = 128,
2092
2093	WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128,
2094	WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT = 129,
2095	WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT = 130,
2096	WMI_TLV_SERVICE_FILS_SUPPORT = 131,
2097	WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD = 132,
2098	WMI_TLV_SERVICE_WLAN_DHCP_RENEW = 133,
2099	WMI_TLV_SERVICE_MAWC_SUPPORT = 134,
2100	WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG = 135,
2101	WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT = 136,
2102	WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT = 137,
2103	WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT = 138,
2104	WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT = 139,
2105	WMI_TLV_SERVICE_THERM_THROT = 140,
2106	WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT = 141,
2107	WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN = 142,
2108	WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143,
2109	WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144,
2110	WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145,
2111	WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146,
2112	WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147,
2113	WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148,
2114	WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149,
2115	WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150,
2116	WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151,
2117	WMI_TLV_SERVICE_STA_TWT = 152,
2118	WMI_TLV_SERVICE_AP_TWT = 153,
2119	WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154,
2120	WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155,
2121	WMI_TLV_SERVICE_PEER_TID_CONFIGS_SUPPORT = 156,
2122	WMI_TLV_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT = 157,
2123	WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT = 158,
2124	WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT = 159,
2125	WMI_TLV_SERVICE_MOTION_DET = 160,
2126	WMI_TLV_SERVICE_INFRA_MBSSID = 161,
2127	WMI_TLV_SERVICE_OBSS_SPATIAL_REUSE = 162,
2128	WMI_TLV_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT = 163,
2129	WMI_TLV_SERVICE_NAN_DBS_SUPPORT = 164,
2130	WMI_TLV_SERVICE_NDI_DBS_SUPPORT = 165,
2131	WMI_TLV_SERVICE_NAN_SAP_SUPPORT = 166,
2132	WMI_TLV_SERVICE_NDI_SAP_SUPPORT = 167,
2133	WMI_TLV_SERVICE_CFR_CAPTURE_SUPPORT = 168,
2134	WMI_TLV_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1 = 169,
2135	WMI_TLV_SERVICE_ESP_SUPPORT = 170,
2136	WMI_TLV_SERVICE_PEER_CHWIDTH_CHANGE = 171,
2137	WMI_TLV_SERVICE_WLAN_HPCS_PULSE = 172,
2138	WMI_TLV_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT = 173,
2139	WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI = 174,
2140	WMI_TLV_SERVICE_NAN_DISABLE_SUPPORT = 175,
2141	WMI_TLV_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN = 176,
2142	WMI_TLV_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION = 177,
2143	WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178,
2144	WMI_TLV_SERVICE_SUPPORT_EXTEND_ADDRESS = 179,
2145	WMI_TLV_SERVICE_BEACON_RECEPTION_STATS = 180,
2146	WMI_TLV_SERVICE_FETCH_TX_PN = 181,
2147	WMI_TLV_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182,
2148	WMI_TLV_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183,
2149	WMI_TLV_SERVICE_BSS_COLOR_SWITCH_COUNT = 184,
2150	WMI_TLV_SERVICE_HTT_PEER_STATS_SUPPORT = 185,
2151	WMI_TLV_SERVICE_UL_RU26_ALLOWED = 186,
2152	WMI_TLV_SERVICE_GET_MWS_COEX_STATE = 187,
2153	WMI_TLV_SERVICE_GET_MWS_DPWB_STATE = 188,
2154	WMI_TLV_SERVICE_GET_MWS_TDM_STATE = 189,
2155	WMI_TLV_SERVICE_GET_MWS_IDRX_STATE = 190,
2156	WMI_TLV_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191,
2157	WMI_TLV_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192,
2158	WMI_TLV_SERVICE_WLM_STATS_REQUEST = 193,
2159	WMI_TLV_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194,
2160	WMI_TLV_SERVICE_WPA3_FT_SAE_SUPPORT = 195,
2161	WMI_TLV_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196,
2162	WMI_TLV_SERVICE_VOW_ENABLE = 197,
2163	WMI_TLV_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198,
2164	WMI_TLV_SERVICE_BROADCAST_TWT = 199,
2165	WMI_TLV_SERVICE_RAP_DETECTION_SUPPORT = 200,
2166	WMI_TLV_SERVICE_PS_TDCC = 201,
2167	WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY   = 202,
2168	WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203,
2169	WMI_TLV_SERVICE_TX_PWR_PER_PEER = 204,
2170	WMI_TLV_SERVICE_STA_PLUS_STA_SUPPORT = 205,
2171	WMI_TLV_SERVICE_WPA3_FT_FILS = 206,
2172	WMI_TLV_SERVICE_ADAPTIVE_11R_ROAM = 207,
2173	WMI_TLV_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208,
2174	WMI_TLV_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209,
2175	WMI_TLV_SERVICE_TX_COMPL_TSF64 = 210,
2176	WMI_TLV_SERVICE_DSM_ROAM_FILTER = 211,
2177	WMI_TLV_SERVICE_PACKET_CAPTURE_SUPPORT = 212,
2178	WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213,
2179	WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219,
2180	WMI_TLV_SERVICE_EXT2_MSG = 220,
2181	WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246,
2182	WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249,
2183	WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253,
2184	WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263,
2185
2186	/* The second 128 bits */
2187	WMI_MAX_EXT_SERVICE = 256,
2188	WMI_TLV_SERVICE_SCAN_CONFIG_PER_CHANNEL = 265,
2189	WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281,
2190	WMI_TLV_SERVICE_BIOS_SAR_SUPPORT = 326,
2191	WMI_TLV_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357,
2192
2193	/* The third 128 bits */
2194	WMI_MAX_EXT2_SERVICE = 384
2195};
2196
2197enum {
2198	WMI_SMPS_FORCED_MODE_NONE = 0,
2199	WMI_SMPS_FORCED_MODE_DISABLED,
2200	WMI_SMPS_FORCED_MODE_STATIC,
2201	WMI_SMPS_FORCED_MODE_DYNAMIC
2202};
2203
2204#define WMI_TPC_CHAINMASK_CONFIG_BAND_2G      0
2205#define WMI_TPC_CHAINMASK_CONFIG_BAND_5G      1
2206#define WMI_NUM_SUPPORTED_BAND_MAX 2
2207
2208#define WMI_PEER_MIMO_PS_STATE                          0x1
2209#define WMI_PEER_AMPDU                                  0x2
2210#define WMI_PEER_AUTHORIZE                              0x3
2211#define WMI_PEER_CHWIDTH                                0x4
2212#define WMI_PEER_NSS                                    0x5
2213#define WMI_PEER_USE_4ADDR                              0x6
2214#define WMI_PEER_MEMBERSHIP                             0x7
2215#define WMI_PEER_USERPOS                                0x8
2216#define WMI_PEER_CRIT_PROTO_HINT_ENABLED                0x9
2217#define WMI_PEER_TX_FAIL_CNT_THR                        0xA
2218#define WMI_PEER_SET_HW_RETRY_CTS2S                     0xB
2219#define WMI_PEER_IBSS_ATIM_WINDOW_LENGTH                0xC
2220#define WMI_PEER_PHYMODE                                0xD
2221#define WMI_PEER_USE_FIXED_PWR                          0xE
2222#define WMI_PEER_PARAM_FIXED_RATE                       0xF
2223#define WMI_PEER_SET_MU_WHITELIST                       0x10
2224#define WMI_PEER_SET_MAX_TX_RATE                        0x11
2225#define WMI_PEER_SET_MIN_TX_RATE                        0x12
2226#define WMI_PEER_SET_DEFAULT_ROUTING                    0x13
2227
2228/* slot time long */
2229#define WMI_VDEV_SLOT_TIME_LONG         0x1
2230/* slot time short */
2231#define WMI_VDEV_SLOT_TIME_SHORT        0x2
2232/* preamble long */
2233#define WMI_VDEV_PREAMBLE_LONG          0x1
2234/* preamble short */
2235#define WMI_VDEV_PREAMBLE_SHORT         0x2
2236
2237enum wmi_peer_smps_state {
2238	WMI_PEER_SMPS_PS_NONE = 0x0,
2239	WMI_PEER_SMPS_STATIC  = 0x1,
2240	WMI_PEER_SMPS_DYNAMIC = 0x2
2241};
2242
2243enum wmi_peer_chwidth {
2244	WMI_PEER_CHWIDTH_20MHZ = 0,
2245	WMI_PEER_CHWIDTH_40MHZ = 1,
2246	WMI_PEER_CHWIDTH_80MHZ = 2,
2247	WMI_PEER_CHWIDTH_160MHZ = 3,
2248};
2249
2250enum wmi_beacon_gen_mode {
2251	WMI_BEACON_STAGGERED_MODE = 0,
2252	WMI_BEACON_BURST_MODE = 1
2253};
2254
2255enum wmi_direct_buffer_module {
2256	WMI_DIRECT_BUF_SPECTRAL = 0,
2257	WMI_DIRECT_BUF_CFR = 1,
2258
2259	/* keep it last */
2260	WMI_DIRECT_BUF_MAX
2261};
2262
2263/* enum wmi_nss_ratio - NSS ratio received from FW during service ready ext
2264 *			event
2265 * WMI_NSS_RATIO_1BY2_NSS -Max nss of 160MHz is equals to half of the max nss
2266 *			   of 80MHz
2267 * WMI_NSS_RATIO_3BY4_NSS - Max nss of 160MHz is equals to 3/4 of the max nss
2268 *			    of 80MHz
2269 * WMI_NSS_RATIO_1_NSS - Max nss of 160MHz is equals to the max nss of 80MHz
2270 * WMI_NSS_RATIO_2_NSS - Max nss of 160MHz is equals to two times the max
2271 *			 nss of 80MHz
2272 */
2273
2274enum wmi_nss_ratio {
2275	WMI_NSS_RATIO_1BY2_NSS = 0x0,
2276	WMI_NSS_RATIO_3BY4_NSS = 0x1,
2277	WMI_NSS_RATIO_1_NSS = 0x2,
2278	WMI_NSS_RATIO_2_NSS = 0x3,
2279};
2280
2281enum wmi_dtim_policy {
2282	WMI_DTIM_POLICY_IGNORE = 1,
2283	WMI_DTIM_POLICY_NORMAL = 2,
2284	WMI_DTIM_POLICY_STICK  = 3,
2285	WMI_DTIM_POLICY_AUTO   = 4,
2286};
2287
2288struct wmi_host_pdev_band_to_mac {
2289	uint32_t pdev_id;
2290	uint32_t start_freq;
2291	uint32_t end_freq;
2292};
2293
2294struct ath12k_ppe_threshold {
2295	uint32_t numss_m1;
2296	uint32_t ru_bit_mask;
2297	uint32_t ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS];
2298};
2299
2300struct ath12k_service_ext_param {
2301	uint32_t default_conc_scan_config_bits;
2302	uint32_t default_fw_config_bits;
2303	struct ath12k_ppe_threshold ppet;
2304	uint32_t he_cap_info;
2305	uint32_t mpdu_density;
2306	uint32_t max_bssid_rx_filters;
2307	uint32_t num_hw_modes;
2308	uint32_t num_phy;
2309};
2310
2311struct ath12k_hw_mode_caps {
2312	uint32_t hw_mode_id;
2313	uint32_t phy_id_map;
2314	uint32_t hw_mode_config_type;
2315};
2316
2317#define PSOC_HOST_MAX_PHY_SIZE (3)
2318#define ATH12K_11B_SUPPORT                 BIT(0)
2319#define ATH12K_11G_SUPPORT                 BIT(1)
2320#define ATH12K_11A_SUPPORT                 BIT(2)
2321#define ATH12K_11N_SUPPORT                 BIT(3)
2322#define ATH12K_11AC_SUPPORT                BIT(4)
2323#define ATH12K_11AX_SUPPORT                BIT(5)
2324
2325struct ath12k_hal_reg_capabilities_ext {
2326	uint32_t phy_id;
2327	uint32_t eeprom_reg_domain;
2328	uint32_t eeprom_reg_domain_ext;
2329	uint32_t regcap1;
2330	uint32_t regcap2;
2331	uint32_t wireless_modes;
2332	uint32_t low_2ghz_chan;
2333	uint32_t high_2ghz_chan;
2334	uint32_t low_5ghz_chan;
2335	uint32_t high_5ghz_chan;
2336};
2337
2338#define WMI_HOST_MAX_PDEV 3
2339
2340struct wlan_host_mem_chunk {
2341	uint32_t tlv_header;
2342	uint32_t req_id;
2343	uint32_t ptr;
2344	uint32_t size;
2345} __packed;
2346
2347struct wmi_host_mem_chunk {
2348	void *vaddr;
2349	bus_addr_t paddr;
2350	uint32_t len;
2351	uint32_t req_id;
2352};
2353
2354struct wmi_init_cmd_param {
2355	uint32_t tlv_header;
2356	struct target_resource_config *res_cfg;
2357	uint8_t num_mem_chunks;
2358	struct wmi_host_mem_chunk *mem_chunks;
2359	uint32_t hw_mode_id;
2360	uint32_t num_band_to_mac;
2361	struct wmi_host_pdev_band_to_mac band_to_mac[WMI_HOST_MAX_PDEV];
2362};
2363
2364struct wmi_pdev_band_to_mac {
2365	uint32_t tlv_header;
2366	uint32_t pdev_id;
2367	uint32_t start_freq;
2368	uint32_t end_freq;
2369} __packed;
2370
2371struct wmi_pdev_set_hw_mode_cmd_param {
2372	uint32_t tlv_header;
2373	uint32_t pdev_id;
2374	uint32_t hw_mode_index;
2375	uint32_t num_band_to_mac;
2376} __packed;
2377
2378struct wmi_ppe_threshold {
2379	uint32_t numss_m1; /** NSS - 1*/
2380	union {
2381		uint32_t ru_count;
2382		uint32_t ru_mask;
2383	} __packed;
2384	uint32_t ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS];
2385} __packed;
2386
2387#define HW_BD_INFO_SIZE       5
2388
2389struct wmi_abi_version {
2390	uint32_t abi_version_0;
2391	uint32_t abi_version_1;
2392	uint32_t abi_version_ns_0;
2393	uint32_t abi_version_ns_1;
2394	uint32_t abi_version_ns_2;
2395	uint32_t abi_version_ns_3;
2396} __packed;
2397
2398struct wmi_init_cmd {
2399	uint32_t tlv_header;
2400	struct wmi_abi_version host_abi_vers;
2401	uint32_t num_host_mem_chunks;
2402} __packed;
2403
2404#define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5)
2405#define WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET BIT(9)
2406#define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18)
2407
2408#define WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT 4
2409
2410struct wmi_resource_config {
2411	uint32_t tlv_header;
2412	uint32_t num_vdevs;
2413	uint32_t num_peers;
2414	uint32_t num_offload_peers;
2415	uint32_t num_offload_reorder_buffs;
2416	uint32_t num_peer_keys;
2417	uint32_t num_tids;
2418	uint32_t ast_skid_limit;
2419	uint32_t tx_chain_mask;
2420	uint32_t rx_chain_mask;
2421	uint32_t rx_timeout_pri[4];
2422	uint32_t rx_decap_mode;
2423	uint32_t scan_max_pending_req;
2424	uint32_t bmiss_offload_max_vdev;
2425	uint32_t roam_offload_max_vdev;
2426	uint32_t roam_offload_max_ap_profiles;
2427	uint32_t num_mcast_groups;
2428	uint32_t num_mcast_table_elems;
2429	uint32_t mcast2ucast_mode;
2430	uint32_t tx_dbg_log_size;
2431	uint32_t num_wds_entries;
2432	uint32_t dma_burst_size;
2433	uint32_t mac_aggr_delim;
2434	uint32_t rx_skip_defrag_timeout_dup_detection_check;
2435	uint32_t vow_config;
2436	uint32_t gtk_offload_max_vdev;
2437	uint32_t num_msdu_desc;
2438	uint32_t max_frag_entries;
2439	uint32_t num_tdls_vdevs;
2440	uint32_t num_tdls_conn_table_entries;
2441	uint32_t beacon_tx_offload_max_vdev;
2442	uint32_t num_multicast_filter_entries;
2443	uint32_t num_wow_filters;
2444	uint32_t num_keep_alive_pattern;
2445	uint32_t keep_alive_pattern_size;
2446	uint32_t max_tdls_concurrent_sleep_sta;
2447	uint32_t max_tdls_concurrent_buffer_sta;
2448	uint32_t wmi_send_separate;
2449	uint32_t num_ocb_vdevs;
2450	uint32_t num_ocb_channels;
2451	uint32_t num_ocb_schedules;
2452	uint32_t flag1;
2453	uint32_t smart_ant_cap;
2454	uint32_t bk_minfree;
2455	uint32_t be_minfree;
2456	uint32_t vi_minfree;
2457	uint32_t vo_minfree;
2458	uint32_t alloc_frag_desc_for_data_pkt;
2459	uint32_t num_ns_ext_tuples_cfg;
2460	uint32_t bpf_instruction_size;
2461	uint32_t max_bssid_rx_filters;
2462	uint32_t use_pdev_id;
2463	uint32_t max_num_dbs_scan_duty_cycle;
2464	uint32_t max_num_group_keys;
2465	uint32_t peer_map_unmap_v2_support;
2466	uint32_t sched_params;
2467	uint32_t twt_ap_pdev_count;
2468	uint32_t twt_ap_sta_count;
2469#ifdef notyet /* 6 GHz support */
2470	uint32_t max_nlo_ssids;
2471	uint32_t num_pkt_filters;
2472	uint32_t num_max_sta_vdevs;
2473	uint32_t max_bssid_indicator;
2474	uint32_t ul_resp_config;
2475	uint32_t msdu_flow_override_config0;
2476	uint32_t msdu_flow_override_config1;
2477	uint32_t flags2;
2478	uint32_t host_service_flags;
2479	uint32_t max_rnr_neighbours;
2480	uint32_t ema_max_vap_cnt;
2481	uint32_t ema_max_profile_period;
2482#endif
2483} __packed;
2484
2485struct wmi_service_ready_event {
2486	uint32_t fw_build_vers;
2487	struct wmi_abi_version fw_abi_vers;
2488	uint32_t phy_capability;
2489	uint32_t max_frag_entry;
2490	uint32_t num_rf_chains;
2491	uint32_t ht_cap_info;
2492	uint32_t vht_cap_info;
2493	uint32_t vht_supp_mcs;
2494	uint32_t hw_min_tx_power;
2495	uint32_t hw_max_tx_power;
2496	uint32_t sys_cap_info;
2497	uint32_t min_pkt_size_enable;
2498	uint32_t max_bcn_ie_size;
2499	uint32_t num_mem_reqs;
2500	uint32_t max_num_scan_channels;
2501	uint32_t hw_bd_id;
2502	uint32_t hw_bd_info[HW_BD_INFO_SIZE];
2503	uint32_t max_supported_macs;
2504	uint32_t wmi_fw_sub_feat_caps;
2505	uint32_t num_dbs_hw_modes;
2506	/* txrx_chainmask
2507	 *    [7:0]   - 2G band tx chain mask
2508	 *    [15:8]  - 2G band rx chain mask
2509	 *    [23:16] - 5G band tx chain mask
2510	 *    [31:24] - 5G band rx chain mask
2511	 */
2512	uint32_t txrx_chainmask;
2513	uint32_t default_dbs_hw_mode_index;
2514	uint32_t num_msdu_desc;
2515} __packed;
2516
2517#define WMI_SERVICE_BM_SIZE	((WMI_MAX_SERVICE + sizeof(uint32_t) - 1) / sizeof(uint32_t))
2518
2519#define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x uint32_t = 128 bits */
2520#define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(uint32_t))
2521#define WMI_AVAIL_SERVICE_BITS_IN_SIZE32 32
2522#define WMI_SERVICE_BITS_IN_SIZE32 4
2523
2524struct wmi_service_ready_ext_event {
2525	uint32_t default_conc_scan_config_bits;
2526	uint32_t default_fw_config_bits;
2527	struct wmi_ppe_threshold ppet;
2528	uint32_t he_cap_info;
2529	uint32_t mpdu_density;
2530	uint32_t max_bssid_rx_filters;
2531	uint32_t fw_build_vers_ext;
2532	uint32_t max_nlo_ssids;
2533	uint32_t max_bssid_indicator;
2534	uint32_t he_cap_info_ext;
2535} __packed;
2536
2537struct wmi_soc_mac_phy_hw_mode_caps {
2538	uint32_t num_hw_modes;
2539	uint32_t num_chainmask_tables;
2540} __packed;
2541
2542struct wmi_hw_mode_capabilities {
2543	uint32_t tlv_header;
2544	uint32_t hw_mode_id;
2545	uint32_t phy_id_map;
2546	uint32_t hw_mode_config_type;
2547} __packed;
2548
2549#define WMI_MAX_HECAP_PHY_SIZE                 (3)
2550#define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS    BIT(0)
2551#define WMI_NSS_RATIO_ENABLE_DISABLE_GET(_val) \
2552	FIELD_GET(WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, _val)
2553#define WMI_NSS_RATIO_INFO_BITPOS              GENMASK(4, 1)
2554#define WMI_NSS_RATIO_INFO_GET(_val) \
2555	FIELD_GET(WMI_NSS_RATIO_INFO_BITPOS, _val)
2556
2557struct wmi_mac_phy_capabilities {
2558	uint32_t hw_mode_id;
2559	uint32_t pdev_id;
2560	uint32_t phy_id;
2561	uint32_t supported_flags;
2562	uint32_t supported_bands;
2563	uint32_t ampdu_density;
2564	uint32_t max_bw_supported_2g;
2565	uint32_t ht_cap_info_2g;
2566	uint32_t vht_cap_info_2g;
2567	uint32_t vht_supp_mcs_2g;
2568	uint32_t he_cap_info_2g;
2569	uint32_t he_supp_mcs_2g;
2570	uint32_t tx_chain_mask_2g;
2571	uint32_t rx_chain_mask_2g;
2572	uint32_t max_bw_supported_5g;
2573	uint32_t ht_cap_info_5g;
2574	uint32_t vht_cap_info_5g;
2575	uint32_t vht_supp_mcs_5g;
2576	uint32_t he_cap_info_5g;
2577	uint32_t he_supp_mcs_5g;
2578	uint32_t tx_chain_mask_5g;
2579	uint32_t rx_chain_mask_5g;
2580	uint32_t he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE];
2581	uint32_t he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE];
2582	struct wmi_ppe_threshold he_ppet2g;
2583	struct wmi_ppe_threshold he_ppet5g;
2584	uint32_t chainmask_table_id;
2585	uint32_t lmac_id;
2586	uint32_t he_cap_info_2g_ext;
2587	uint32_t he_cap_info_5g_ext;
2588	uint32_t he_cap_info_internal;
2589	uint32_t wireless_modes;
2590	uint32_t low_2ghz_chan_freq;
2591	uint32_t high_2ghz_chan_freq;
2592	uint32_t low_5ghz_chan_freq;
2593	uint32_t high_5ghz_chan_freq;
2594	uint32_t nss_ratio;
2595} __packed;
2596
2597struct wmi_hal_reg_capabilities_ext {
2598	uint32_t tlv_header;
2599	uint32_t phy_id;
2600	uint32_t eeprom_reg_domain;
2601	uint32_t eeprom_reg_domain_ext;
2602	uint32_t regcap1;
2603	uint32_t regcap2;
2604	uint32_t wireless_modes;
2605	uint32_t low_2ghz_chan;
2606	uint32_t high_2ghz_chan;
2607	uint32_t low_5ghz_chan;
2608	uint32_t high_5ghz_chan;
2609} __packed;
2610
2611struct wmi_soc_hal_reg_capabilities {
2612	uint32_t num_phy;
2613} __packed;
2614
2615/* 2 word representation of MAC addr */
2616struct wmi_mac_addr {
2617	union {
2618		uint8_t addr[6];
2619		struct {
2620			uint32_t word0;
2621			uint32_t word1;
2622		} __packed;
2623	} __packed;
2624} __packed;
2625
2626struct wmi_dma_ring_capabilities {
2627	uint32_t tlv_header;
2628	uint32_t pdev_id;
2629	uint32_t module_id;
2630	uint32_t min_elem;
2631	uint32_t min_buf_sz;
2632	uint32_t min_buf_align;
2633} __packed;
2634
2635struct wmi_ready_event_min {
2636	struct wmi_abi_version fw_abi_vers;
2637	struct wmi_mac_addr mac_addr;
2638	uint32_t status;
2639	uint32_t num_dscp_table;
2640	uint32_t num_extra_mac_addr;
2641	uint32_t num_total_peers;
2642	uint32_t num_extra_peers;
2643} __packed;
2644
2645struct wmi_ready_event {
2646	struct wmi_ready_event_min ready_event_min;
2647	uint32_t max_ast_index;
2648	uint32_t pktlog_defs_checksum;
2649} __packed;
2650
2651struct wmi_service_available_event {
2652	uint32_t wmi_service_segment_offset;
2653	uint32_t wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32];
2654} __packed;
2655
2656struct vdev_create_params {
2657	uint8_t if_id;
2658	uint32_t type;
2659	uint32_t subtype;
2660	struct {
2661		uint8_t tx;
2662		uint8_t rx;
2663	} chains[2];
2664	uint32_t pdev_id;
2665	uint32_t mbssid_flags;
2666	uint32_t mbssid_tx_vdev_id;
2667};
2668
2669struct wmi_vdev_create_cmd {
2670	uint32_t tlv_header;
2671	uint32_t vdev_id;
2672	uint32_t vdev_type;
2673	uint32_t vdev_subtype;
2674	struct wmi_mac_addr vdev_macaddr;
2675	uint32_t num_cfg_txrx_streams;
2676	uint32_t pdev_id;
2677	uint32_t mbssid_flags;
2678	uint32_t mbssid_tx_vdev_id;
2679} __packed;
2680
2681struct wmi_vdev_txrx_streams {
2682	uint32_t tlv_header;
2683	uint32_t band;
2684	uint32_t supported_tx_streams;
2685	uint32_t supported_rx_streams;
2686} __packed;
2687
2688struct wmi_vdev_delete_cmd {
2689	uint32_t tlv_header;
2690	uint32_t vdev_id;
2691} __packed;
2692
2693struct wmi_vdev_up_cmd {
2694	uint32_t tlv_header;
2695	uint32_t vdev_id;
2696	uint32_t vdev_assoc_id;
2697	struct wmi_mac_addr vdev_bssid;
2698	struct wmi_mac_addr tx_vdev_bssid;
2699	uint32_t nontx_profile_idx;
2700	uint32_t nontx_profile_cnt;
2701} __packed;
2702
2703struct wmi_vdev_stop_cmd {
2704	uint32_t tlv_header;
2705	uint32_t vdev_id;
2706} __packed;
2707
2708struct wmi_vdev_down_cmd {
2709	uint32_t tlv_header;
2710	uint32_t vdev_id;
2711} __packed;
2712
2713#define WMI_VDEV_START_HIDDEN_SSID  BIT(0)
2714#define WMI_VDEV_START_PMF_ENABLED  BIT(1)
2715#define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3)
2716#define WMI_VDEV_START_HW_ENCRYPTION_DISABLED BIT(4)
2717
2718struct wmi_ssid {
2719	uint32_t ssid_len;
2720	uint32_t ssid[8];
2721} __packed;
2722
2723#define ATH12K_VDEV_SETUP_TIMEOUT_HZ (1 * HZ)
2724
2725struct wmi_vdev_start_request_cmd {
2726	uint32_t tlv_header;
2727	uint32_t vdev_id;
2728	uint32_t requestor_id;
2729	uint32_t beacon_interval;
2730	uint32_t dtim_period;
2731	uint32_t flags;
2732	struct wmi_ssid ssid;
2733	uint32_t bcn_tx_rate;
2734	uint32_t bcn_txpower;
2735	uint32_t num_noa_descriptors;
2736	uint32_t disable_hw_ack;
2737	uint32_t preferred_tx_streams;
2738	uint32_t preferred_rx_streams;
2739	uint32_t he_ops;
2740	uint32_t cac_duration_ms;
2741	uint32_t regdomain;
2742	uint32_t min_data_rate;
2743	uint32_t mbssid_flags;
2744	uint32_t mbssid_tx_vdev_id;
2745} __packed;
2746
2747#define MGMT_TX_DL_FRM_LEN		     64
2748#define WMI_MAC_MAX_SSID_LENGTH              32
2749struct mac_ssid {
2750	uint8_t length;
2751	uint8_t mac_ssid[WMI_MAC_MAX_SSID_LENGTH];
2752} __packed;
2753
2754struct wmi_p2p_noa_descriptor {
2755	uint32_t type_count;
2756	uint32_t duration;
2757	uint32_t interval;
2758	uint32_t start_time;
2759};
2760
2761struct channel_param {
2762	uint8_t chan_id;
2763	uint8_t pwr;
2764	uint32_t mhz;
2765	uint32_t half_rate:1,
2766	    quarter_rate:1,
2767	    dfs_set:1,
2768	    dfs_set_cfreq2:1,
2769	    is_chan_passive:1,
2770	    allow_ht:1,
2771	    allow_vht:1,
2772	    allow_he:1,
2773	    set_agile:1,
2774	    psc_channel:1;
2775	uint32_t phy_mode;
2776	uint32_t cfreq1;
2777	uint32_t cfreq2;
2778	char   maxpower;
2779	char   minpower;
2780	char   maxregpower;
2781	uint8_t  antennamax;
2782	uint8_t  reg_class_id;
2783} __packed;
2784
2785enum wmi_phy_mode {
2786	MODE_11A        = 0,
2787	MODE_11G        = 1,   /* 11b/g Mode */
2788	MODE_11B        = 2,   /* 11b Mode */
2789	MODE_11GONLY    = 3,   /* 11g only Mode */
2790	MODE_11NA_HT20   = 4,
2791	MODE_11NG_HT20   = 5,
2792	MODE_11NA_HT40   = 6,
2793	MODE_11NG_HT40   = 7,
2794	MODE_11AC_VHT20 = 8,
2795	MODE_11AC_VHT40 = 9,
2796	MODE_11AC_VHT80 = 10,
2797	MODE_11AC_VHT20_2G = 11,
2798	MODE_11AC_VHT40_2G = 12,
2799	MODE_11AC_VHT80_2G = 13,
2800	MODE_11AC_VHT80_80 = 14,
2801	MODE_11AC_VHT160 = 15,
2802	MODE_11AX_HE20 = 16,
2803	MODE_11AX_HE40 = 17,
2804	MODE_11AX_HE80 = 18,
2805	MODE_11AX_HE80_80 = 19,
2806	MODE_11AX_HE160 = 20,
2807	MODE_11AX_HE20_2G = 21,
2808	MODE_11AX_HE40_2G = 22,
2809	MODE_11AX_HE80_2G = 23,
2810	MODE_UNKNOWN = 24,
2811	MODE_MAX = 24
2812};
2813
2814static inline const char *qwz_wmi_phymode_str(enum wmi_phy_mode mode)
2815{
2816	switch (mode) {
2817	case MODE_11A:
2818		return "11a";
2819	case MODE_11G:
2820		return "11g";
2821	case MODE_11B:
2822		return "11b";
2823	case MODE_11GONLY:
2824		return "11gonly";
2825	case MODE_11NA_HT20:
2826		return "11na-ht20";
2827	case MODE_11NG_HT20:
2828		return "11ng-ht20";
2829	case MODE_11NA_HT40:
2830		return "11na-ht40";
2831	case MODE_11NG_HT40:
2832		return "11ng-ht40";
2833	case MODE_11AC_VHT20:
2834		return "11ac-vht20";
2835	case MODE_11AC_VHT40:
2836		return "11ac-vht40";
2837	case MODE_11AC_VHT80:
2838		return "11ac-vht80";
2839	case MODE_11AC_VHT160:
2840		return "11ac-vht160";
2841	case MODE_11AC_VHT80_80:
2842		return "11ac-vht80+80";
2843	case MODE_11AC_VHT20_2G:
2844		return "11ac-vht20-2g";
2845	case MODE_11AC_VHT40_2G:
2846		return "11ac-vht40-2g";
2847	case MODE_11AC_VHT80_2G:
2848		return "11ac-vht80-2g";
2849	case MODE_11AX_HE20:
2850		return "11ax-he20";
2851	case MODE_11AX_HE40:
2852		return "11ax-he40";
2853	case MODE_11AX_HE80:
2854		return "11ax-he80";
2855	case MODE_11AX_HE80_80:
2856		return "11ax-he80+80";
2857	case MODE_11AX_HE160:
2858		return "11ax-he160";
2859	case MODE_11AX_HE20_2G:
2860		return "11ax-he20-2g";
2861	case MODE_11AX_HE40_2G:
2862		return "11ax-he40-2g";
2863	case MODE_11AX_HE80_2G:
2864		return "11ax-he80-2g";
2865	case MODE_UNKNOWN:
2866		/* skip */
2867		break;
2868
2869		/* no default handler to allow compiler to check that the
2870		 * enum is fully handled
2871		 */
2872	}
2873
2874	return "<unknown>";
2875}
2876
2877struct wmi_channel_arg {
2878	uint32_t freq;
2879	uint32_t band_center_freq1;
2880	uint32_t band_center_freq2;
2881	bool passive;
2882	bool allow_ibss;
2883	bool allow_ht;
2884	bool allow_vht;
2885	bool ht40plus;
2886	bool chan_radar;
2887	bool freq2_radar;
2888	bool allow_he;
2889	uint32_t min_power;
2890	uint32_t max_power;
2891	uint32_t max_reg_power;
2892	uint32_t max_antenna_gain;
2893	enum wmi_phy_mode mode;
2894};
2895
2896struct wmi_vdev_start_req_arg {
2897	uint32_t vdev_id;
2898	struct wmi_channel_arg channel;
2899	uint32_t bcn_intval;
2900	uint32_t dtim_period;
2901	uint8_t *ssid;
2902	uint32_t ssid_len;
2903	uint32_t bcn_tx_rate;
2904	uint32_t bcn_tx_power;
2905	bool disable_hw_ack;
2906	bool hidden_ssid;
2907	bool pmf_enabled;
2908	uint32_t he_ops;
2909	uint32_t cac_duration_ms;
2910	uint32_t regdomain;
2911	uint32_t pref_rx_streams;
2912	uint32_t pref_tx_streams;
2913	uint32_t num_noa_descriptors;
2914	uint32_t min_data_rate;
2915	uint32_t mbssid_flags;
2916	uint32_t mbssid_tx_vdev_id;
2917};
2918
2919struct peer_create_params {
2920	uint8_t *peer_addr;
2921	uint32_t peer_type;
2922	uint32_t vdev_id;
2923};
2924
2925struct peer_delete_params {
2926	uint8_t vdev_id;
2927};
2928
2929struct peer_flush_params {
2930	uint32_t peer_tid_bitmap;
2931	uint8_t vdev_id;
2932};
2933
2934struct pdev_set_regdomain_params {
2935	uint16_t current_rd_in_use;
2936	uint16_t current_rd_2g;
2937	uint16_t current_rd_5g;
2938	uint32_t ctl_2g;
2939	uint32_t ctl_5g;
2940	uint8_t dfs_domain;
2941	uint32_t pdev_id;
2942};
2943
2944struct rx_reorder_queue_remove_params {
2945	uint8_t *peer_macaddr;
2946	uint16_t vdev_id;
2947	uint32_t peer_tid_bitmap;
2948};
2949
2950#define WMI_HOST_PDEV_ID_SOC 0xFF
2951#define WMI_HOST_PDEV_ID_0   0
2952#define WMI_HOST_PDEV_ID_1   1
2953#define WMI_HOST_PDEV_ID_2   2
2954
2955#define WMI_PDEV_ID_SOC         0
2956#define WMI_PDEV_ID_1ST         1
2957#define WMI_PDEV_ID_2ND         2
2958#define WMI_PDEV_ID_3RD         3
2959
2960/* Freq units in MHz */
2961#define REG_RULE_START_FREQ			0x0000ffff
2962#define REG_RULE_END_FREQ			0xffff0000
2963#define REG_RULE_FLAGS				0x0000ffff
2964#define REG_RULE_MAX_BW				0x0000ffff
2965#define REG_RULE_REG_PWR			0x00ff0000
2966#define REG_RULE_ANT_GAIN			0xff000000
2967#define REG_RULE_PSD_INFO			BIT(0)
2968#define REG_RULE_PSD_EIRP			0xff0000
2969
2970#define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0)
2971#define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1)
2972#define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2)
2973#define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3)
2974
2975#define HE_PHYCAP_BYTE_0	0
2976#define HE_PHYCAP_BYTE_1	1
2977#define HE_PHYCAP_BYTE_2	2
2978#define HE_PHYCAP_BYTE_3	3
2979#define HE_PHYCAP_BYTE_4	4
2980
2981#define HECAP_PHY_SU_BFER		BIT(7)
2982#define HECAP_PHY_SU_BFEE		BIT(0)
2983#define HECAP_PHY_MU_BFER		BIT(1)
2984#define HECAP_PHY_UL_MUMIMO		BIT(6)
2985#define HECAP_PHY_UL_MUOFDMA		BIT(7)
2986
2987#define HECAP_PHY_SUBFMR_GET(hecap_phy) \
2988	FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HE_PHYCAP_BYTE_3])
2989
2990#define HECAP_PHY_SUBFME_GET(hecap_phy) \
2991	FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HE_PHYCAP_BYTE_4])
2992
2993#define HECAP_PHY_MUBFMR_GET(hecap_phy) \
2994	FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HE_PHYCAP_BYTE_4])
2995
2996#define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \
2997	FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HE_PHYCAP_BYTE_2])
2998
2999#define HECAP_PHY_ULOFDMA_GET(hecap_phy) \
3000	FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HE_PHYCAP_BYTE_2])
3001
3002#define HE_MODE_SU_TX_BFEE	BIT(0)
3003#define HE_MODE_SU_TX_BFER	BIT(1)
3004#define HE_MODE_MU_TX_BFEE	BIT(2)
3005#define HE_MODE_MU_TX_BFER	BIT(3)
3006#define HE_MODE_DL_OFDMA	BIT(4)
3007#define HE_MODE_UL_OFDMA	BIT(5)
3008#define HE_MODE_UL_MUMIMO	BIT(6)
3009
3010#define HE_DL_MUOFDMA_ENABLE	1
3011#define HE_UL_MUOFDMA_ENABLE	1
3012#define HE_DL_MUMIMO_ENABLE	1
3013#define HE_UL_MUMIMO_ENABLE	1
3014#define HE_MU_BFEE_ENABLE	1
3015#define HE_SU_BFEE_ENABLE	1
3016#define HE_MU_BFER_ENABLE	1
3017#define HE_SU_BFER_ENABLE	1
3018
3019#define HE_VHT_SOUNDING_MODE_ENABLE		1
3020#define HE_SU_MU_SOUNDING_MODE_ENABLE		1
3021#define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE	1
3022
3023/* HE or VHT Sounding */
3024#define HE_VHT_SOUNDING_MODE		BIT(0)
3025/* SU or MU Sounding */
3026#define HE_SU_MU_SOUNDING_MODE		BIT(2)
3027/* Trig or Non-Trig Sounding */
3028#define HE_TRIG_NONTRIG_SOUNDING_MODE	BIT(3)
3029
3030#define WMI_TXBF_STS_CAP_OFFSET_LSB	4
3031#define WMI_TXBF_STS_CAP_OFFSET_MASK	0x70
3032#define WMI_BF_SOUND_DIM_OFFSET_LSB	8
3033#define WMI_BF_SOUND_DIM_OFFSET_MASK	0x700
3034
3035struct pdev_params {
3036	uint32_t param_id;
3037	uint32_t param_value;
3038};
3039
3040enum wmi_peer_type {
3041	WMI_PEER_TYPE_DEFAULT = 0,
3042	WMI_PEER_TYPE_BSS = 1,
3043	WMI_PEER_TYPE_TDLS = 2,
3044};
3045
3046struct wmi_peer_create_cmd {
3047	uint32_t tlv_header;
3048	uint32_t vdev_id;
3049	struct wmi_mac_addr peer_macaddr;
3050	uint32_t peer_type;
3051} __packed;
3052
3053struct wmi_peer_delete_cmd {
3054	uint32_t tlv_header;
3055	uint32_t vdev_id;
3056	struct wmi_mac_addr peer_macaddr;
3057} __packed;
3058
3059struct wmi_peer_reorder_queue_setup_cmd {
3060	uint32_t tlv_header;
3061	uint32_t vdev_id;
3062	struct wmi_mac_addr peer_macaddr;
3063	uint32_t tid;
3064	uint32_t queue_ptr_lo;
3065	uint32_t queue_ptr_hi;
3066	uint32_t queue_no;
3067	uint32_t ba_window_size_valid;
3068	uint32_t ba_window_size;
3069} __packed;
3070
3071struct wmi_peer_reorder_queue_remove_cmd {
3072	uint32_t tlv_header;
3073	uint32_t vdev_id;
3074	struct wmi_mac_addr peer_macaddr;
3075	uint32_t tid_mask;
3076} __packed;
3077
3078struct gpio_config_params {
3079	uint32_t gpio_num;
3080	uint32_t input;
3081	uint32_t pull_type;
3082	uint32_t intr_mode;
3083};
3084
3085enum wmi_gpio_type {
3086	WMI_GPIO_PULL_NONE,
3087	WMI_GPIO_PULL_UP,
3088	WMI_GPIO_PULL_DOWN
3089};
3090
3091enum wmi_gpio_intr_type {
3092	WMI_GPIO_INTTYPE_DISABLE,
3093	WMI_GPIO_INTTYPE_RISING_EDGE,
3094	WMI_GPIO_INTTYPE_FALLING_EDGE,
3095	WMI_GPIO_INTTYPE_BOTH_EDGE,
3096	WMI_GPIO_INTTYPE_LEVEL_LOW,
3097	WMI_GPIO_INTTYPE_LEVEL_HIGH
3098};
3099
3100enum wmi_bss_chan_info_req_type {
3101	WMI_BSS_SURVEY_REQ_TYPE_READ = 1,
3102	WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR,
3103};
3104
3105struct wmi_gpio_config_cmd_param {
3106	uint32_t tlv_header;
3107	uint32_t gpio_num;
3108	uint32_t input;
3109	uint32_t pull_type;
3110	uint32_t intr_mode;
3111};
3112
3113struct gpio_output_params {
3114	uint32_t gpio_num;
3115	uint32_t set;
3116};
3117
3118struct wmi_gpio_output_cmd_param {
3119	uint32_t tlv_header;
3120	uint32_t gpio_num;
3121	uint32_t set;
3122};
3123
3124struct set_fwtest_params {
3125	uint32_t arg;
3126	uint32_t value;
3127};
3128
3129struct wmi_fwtest_set_param_cmd_param {
3130	uint32_t tlv_header;
3131	uint32_t param_id;
3132	uint32_t param_value;
3133};
3134
3135struct wmi_pdev_set_param_cmd {
3136	uint32_t tlv_header;
3137	uint32_t pdev_id;
3138	uint32_t param_id;
3139	uint32_t param_value;
3140} __packed;
3141
3142struct wmi_pdev_set_ps_mode_cmd {
3143	uint32_t tlv_header;
3144	uint32_t vdev_id;
3145	uint32_t sta_ps_mode;
3146} __packed;
3147
3148struct wmi_pdev_suspend_cmd {
3149	uint32_t tlv_header;
3150	uint32_t pdev_id;
3151	uint32_t suspend_opt;
3152} __packed;
3153
3154struct wmi_pdev_resume_cmd {
3155	uint32_t tlv_header;
3156	uint32_t pdev_id;
3157} __packed;
3158
3159struct wmi_pdev_bss_chan_info_req_cmd {
3160	uint32_t tlv_header;
3161	/* ref wmi_bss_chan_info_req_type */
3162	uint32_t req_type;
3163	uint32_t pdev_id;
3164} __packed;
3165
3166struct wmi_ap_ps_peer_cmd {
3167	uint32_t tlv_header;
3168	uint32_t vdev_id;
3169	struct wmi_mac_addr peer_macaddr;
3170	uint32_t param;
3171	uint32_t value;
3172} __packed;
3173
3174struct wmi_sta_powersave_param_cmd {
3175	uint32_t tlv_header;
3176	uint32_t vdev_id;
3177	uint32_t param;
3178	uint32_t value;
3179} __packed;
3180
3181struct wmi_pdev_set_regdomain_cmd {
3182	uint32_t tlv_header;
3183	uint32_t pdev_id;
3184	uint32_t reg_domain;
3185	uint32_t reg_domain_2g;
3186	uint32_t reg_domain_5g;
3187	uint32_t conformance_test_limit_2g;
3188	uint32_t conformance_test_limit_5g;
3189	uint32_t dfs_domain;
3190} __packed;
3191
3192struct wmi_peer_set_param_cmd {
3193	uint32_t tlv_header;
3194	uint32_t vdev_id;
3195	struct wmi_mac_addr peer_macaddr;
3196	uint32_t param_id;
3197	uint32_t param_value;
3198} __packed;
3199
3200struct wmi_peer_flush_tids_cmd {
3201	uint32_t tlv_header;
3202	uint32_t vdev_id;
3203	struct wmi_mac_addr peer_macaddr;
3204	uint32_t peer_tid_bitmap;
3205} __packed;
3206
3207struct wmi_dfs_phyerr_offload_cmd {
3208	uint32_t tlv_header;
3209	uint32_t pdev_id;
3210} __packed;
3211
3212struct wmi_bcn_offload_ctrl_cmd {
3213	uint32_t tlv_header;
3214	uint32_t vdev_id;
3215	uint32_t bcn_ctrl_op;
3216} __packed;
3217
3218enum scan_dwelltime_adaptive_mode {
3219	SCAN_DWELL_MODE_DEFAULT = 0,
3220	SCAN_DWELL_MODE_CONSERVATIVE = 1,
3221	SCAN_DWELL_MODE_MODERATE = 2,
3222	SCAN_DWELL_MODE_AGGRESSIVE = 3,
3223	SCAN_DWELL_MODE_STATIC = 4
3224};
3225
3226#define WLAN_SSID_MAX_LEN 32
3227
3228struct element_info {
3229	uint32_t len;
3230	uint8_t *ptr;
3231};
3232
3233struct wlan_ssid {
3234	uint8_t length;
3235	uint8_t ssid[WLAN_SSID_MAX_LEN];
3236};
3237
3238#define WMI_IE_BITMAP_SIZE             8
3239
3240/* prefix used by scan requestor ids on the host */
3241#define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000
3242
3243/* prefix used by scan request ids generated on the host */
3244/* host cycles through the lower 12 bits to generate ids */
3245#define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000
3246
3247/* Values lower than this may be refused by some firmware revisions with a scan
3248 * completion with a timedout reason.
3249 */
3250#define WMI_SCAN_CHAN_MIN_TIME_MSEC 40
3251
3252/* Scan priority numbers must be sequential, starting with 0 */
3253enum wmi_scan_priority {
3254	WMI_SCAN_PRIORITY_VERY_LOW = 0,
3255	WMI_SCAN_PRIORITY_LOW,
3256	WMI_SCAN_PRIORITY_MEDIUM,
3257	WMI_SCAN_PRIORITY_HIGH,
3258	WMI_SCAN_PRIORITY_VERY_HIGH,
3259	WMI_SCAN_PRIORITY_COUNT   /* number of priorities supported */
3260};
3261
3262enum wmi_scan_event_type {
3263	WMI_SCAN_EVENT_STARTED              = BIT(0),
3264	WMI_SCAN_EVENT_COMPLETED            = BIT(1),
3265	WMI_SCAN_EVENT_BSS_CHANNEL          = BIT(2),
3266	WMI_SCAN_EVENT_FOREIGN_CHAN         = BIT(3),
3267	WMI_SCAN_EVENT_DEQUEUED             = BIT(4),
3268	/* possibly by high-prio scan */
3269	WMI_SCAN_EVENT_PREEMPTED            = BIT(5),
3270	WMI_SCAN_EVENT_START_FAILED         = BIT(6),
3271	WMI_SCAN_EVENT_RESTARTED            = BIT(7),
3272	WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT    = BIT(8),
3273	WMI_SCAN_EVENT_SUSPENDED            = BIT(9),
3274	WMI_SCAN_EVENT_RESUMED              = BIT(10),
3275	WMI_SCAN_EVENT_MAX                  = BIT(15),
3276};
3277
3278enum wmi_scan_completion_reason {
3279	WMI_SCAN_REASON_COMPLETED,
3280	WMI_SCAN_REASON_CANCELLED,
3281	WMI_SCAN_REASON_PREEMPTED,
3282	WMI_SCAN_REASON_TIMEDOUT,
3283	WMI_SCAN_REASON_INTERNAL_FAILURE,
3284	WMI_SCAN_REASON_MAX,
3285};
3286
3287struct  wmi_start_scan_cmd {
3288	uint32_t tlv_header;
3289	uint32_t scan_id;
3290	uint32_t scan_req_id;
3291	uint32_t vdev_id;
3292	uint32_t scan_priority;
3293	uint32_t notify_scan_events;
3294	uint32_t dwell_time_active;
3295	uint32_t dwell_time_passive;
3296	uint32_t min_rest_time;
3297	uint32_t max_rest_time;
3298	uint32_t repeat_probe_time;
3299	uint32_t probe_spacing_time;
3300	uint32_t idle_time;
3301	uint32_t max_scan_time;
3302	uint32_t probe_delay;
3303	uint32_t scan_ctrl_flags;
3304	uint32_t burst_duration;
3305	uint32_t num_chan;
3306	uint32_t num_bssid;
3307	uint32_t num_ssids;
3308	uint32_t ie_len;
3309	uint32_t n_probes;
3310	struct wmi_mac_addr mac_addr;
3311	struct wmi_mac_addr mac_mask;
3312	uint32_t ie_bitmap[WMI_IE_BITMAP_SIZE];
3313	uint32_t num_vendor_oui;
3314	uint32_t scan_ctrl_flags_ext;
3315	uint32_t dwell_time_active_2g;
3316	uint32_t dwell_time_active_6g;
3317	uint32_t dwell_time_passive_6g;
3318	uint32_t scan_start_offset;
3319} __packed;
3320
3321#define WMI_SCAN_FLAG_PASSIVE        0x1
3322#define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2
3323#define WMI_SCAN_ADD_CCK_RATES       0x4
3324#define WMI_SCAN_ADD_OFDM_RATES      0x8
3325#define WMI_SCAN_CHAN_STAT_EVENT     0x10
3326#define WMI_SCAN_FILTER_PROBE_REQ    0x20
3327#define WMI_SCAN_BYPASS_DFS_CHN      0x40
3328#define WMI_SCAN_CONTINUE_ON_ERROR   0x80
3329#define WMI_SCAN_FILTER_PROMISCUOS   0x100
3330#define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200
3331#define WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ  0x400
3332#define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ   0x800
3333#define WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ   0x1000
3334#define WMI_SCAN_OFFCHAN_MGMT_TX    0x2000
3335#define WMI_SCAN_OFFCHAN_DATA_TX    0x4000
3336#define WMI_SCAN_CAPTURE_PHY_ERROR  0x8000
3337#define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000
3338#define WMI_SCAN_FLAG_HALF_RATE_SUPPORT      0x20000
3339#define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT   0x40000
3340#define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000
3341#define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000
3342
3343#define WMI_SCAN_DWELL_MODE_MASK 0x00E00000
3344#define WMI_SCAN_DWELL_MODE_SHIFT        21
3345#define WMI_SCAN_FLAG_EXT_PASSIVE_SCAN_START_TIME_ENHANCE   0x00000800
3346
3347#define WMI_SCAN_CONFIG_PER_CHANNEL_MASK	GENMASK(19, 0)
3348#define WMI_SCAN_CH_FLAG_SCAN_ONLY_IF_RNR_FOUND	BIT(20)
3349
3350enum {
3351	WMI_SCAN_DWELL_MODE_DEFAULT      = 0,
3352	WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1,
3353	WMI_SCAN_DWELL_MODE_MODERATE     = 2,
3354	WMI_SCAN_DWELL_MODE_AGGRESSIVE   = 3,
3355	WMI_SCAN_DWELL_MODE_STATIC       = 4,
3356};
3357
3358#define WMI_SCAN_SET_DWELL_MODE(flag, mode) \
3359	((flag) |= (((mode) << WMI_SCAN_DWELL_MODE_SHIFT) & \
3360		    WMI_SCAN_DWELL_MODE_MASK))
3361
3362struct hint_short_ssid {
3363	uint32_t freq_flags;
3364	uint32_t short_ssid;
3365};
3366
3367struct hint_bssid {
3368	uint32_t freq_flags;
3369	struct wmi_mac_addr bssid;
3370};
3371
3372struct scan_req_params {
3373	uint32_t scan_id;
3374	uint32_t scan_req_id;
3375	uint32_t vdev_id;
3376	uint32_t pdev_id;
3377	enum wmi_scan_priority scan_priority;
3378	union {
3379		struct {
3380			uint32_t scan_ev_started:1,
3381			    scan_ev_completed:1,
3382			    scan_ev_bss_chan:1,
3383			    scan_ev_foreign_chan:1,
3384			    scan_ev_dequeued:1,
3385			    scan_ev_preempted:1,
3386			    scan_ev_start_failed:1,
3387			    scan_ev_restarted:1,
3388			    scan_ev_foreign_chn_exit:1,
3389			    scan_ev_invalid:1,
3390			    scan_ev_gpio_timeout:1,
3391			    scan_ev_suspended:1,
3392			    scan_ev_resumed:1;
3393		};
3394		uint32_t scan_events;
3395	};
3396	uint32_t scan_ctrl_flags_ext;
3397	uint32_t dwell_time_active;
3398	uint32_t dwell_time_active_2g;
3399	uint32_t dwell_time_passive;
3400	uint32_t dwell_time_active_6g;
3401	uint32_t dwell_time_passive_6g;
3402	uint32_t min_rest_time;
3403	uint32_t max_rest_time;
3404	uint32_t repeat_probe_time;
3405	uint32_t probe_spacing_time;
3406	uint32_t idle_time;
3407	uint32_t max_scan_time;
3408	uint32_t probe_delay;
3409	union {
3410		struct {
3411			uint32_t scan_f_passive:1,
3412			    scan_f_bcast_probe:1,
3413			    scan_f_cck_rates:1,
3414			    scan_f_ofdm_rates:1,
3415			    scan_f_chan_stat_evnt:1,
3416			    scan_f_filter_prb_req:1,
3417			    scan_f_bypass_dfs_chn:1,
3418			    scan_f_continue_on_err:1,
3419			    scan_f_offchan_mgmt_tx:1,
3420			    scan_f_offchan_data_tx:1,
3421			    scan_f_promisc_mode:1,
3422			    scan_f_capture_phy_err:1,
3423			    scan_f_strict_passive_pch:1,
3424			    scan_f_half_rate:1,
3425			    scan_f_quarter_rate:1,
3426			    scan_f_force_active_dfs_chn:1,
3427			    scan_f_add_tpc_ie_in_probe:1,
3428			    scan_f_add_ds_ie_in_probe:1,
3429			    scan_f_add_spoofed_mac_in_probe:1,
3430			    scan_f_add_rand_seq_in_probe:1,
3431			    scan_f_en_ie_whitelist_in_probe:1,
3432			    scan_f_forced:1,
3433			    scan_f_2ghz:1,
3434			    scan_f_5ghz:1,
3435			    scan_f_80mhz:1;
3436		};
3437		uint32_t scan_flags;
3438	};
3439	enum scan_dwelltime_adaptive_mode adaptive_dwell_time_mode;
3440	uint32_t burst_duration;
3441	uint32_t num_chan;
3442	uint32_t num_bssid;
3443	uint32_t num_ssids;
3444	uint32_t n_probes;
3445	uint32_t *chan_list;
3446	uint32_t notify_scan_events;
3447	struct wlan_ssid ssid[WLAN_SCAN_PARAMS_MAX_SSID];
3448	struct wmi_mac_addr bssid_list[WLAN_SCAN_PARAMS_MAX_BSSID];
3449	struct element_info extraie;
3450	struct element_info htcap;
3451	struct element_info vhtcap;
3452	uint32_t num_hint_s_ssid;
3453	uint32_t num_hint_bssid;
3454	struct hint_short_ssid hint_s_ssid[WLAN_SCAN_MAX_HINT_S_SSID];
3455	struct hint_bssid hint_bssid[WLAN_SCAN_MAX_HINT_BSSID];
3456	struct wmi_mac_addr mac_addr;
3457	struct wmi_mac_addr mac_mask;
3458};
3459
3460struct wmi_ssid_arg {
3461	int len;
3462	const uint8_t *ssid;
3463};
3464
3465struct wmi_bssid_arg {
3466	const uint8_t *bssid;
3467};
3468
3469struct wmi_start_scan_arg {
3470	uint32_t scan_id;
3471	uint32_t scan_req_id;
3472	uint32_t vdev_id;
3473	uint32_t scan_priority;
3474	uint32_t notify_scan_events;
3475	uint32_t dwell_time_active;
3476	uint32_t dwell_time_passive;
3477	uint32_t min_rest_time;
3478	uint32_t max_rest_time;
3479	uint32_t repeat_probe_time;
3480	uint32_t probe_spacing_time;
3481	uint32_t idle_time;
3482	uint32_t max_scan_time;
3483	uint32_t probe_delay;
3484	uint32_t scan_ctrl_flags;
3485
3486	uint32_t ie_len;
3487	uint32_t n_channels;
3488	uint32_t n_ssids;
3489	uint32_t n_bssids;
3490
3491	uint8_t ie[WLAN_SCAN_PARAMS_MAX_IE_LEN];
3492	uint32_t channels[64];
3493	struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID];
3494	struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID];
3495};
3496
3497#define WMI_SCAN_STOP_ONE       0x00000000
3498#define WMI_SCN_STOP_VAP_ALL    0x01000000
3499#define WMI_SCAN_STOP_ALL       0x04000000
3500
3501/* Prefix 0xA000 indicates that the scan request
3502 * is trigger by HOST
3503 */
3504#define ATH12K_SCAN_ID          0xA000
3505
3506enum scan_cancel_req_type {
3507	WLAN_SCAN_CANCEL_SINGLE = 1,
3508	WLAN_SCAN_CANCEL_VDEV_ALL,
3509	WLAN_SCAN_CANCEL_PDEV_ALL,
3510};
3511
3512struct scan_cancel_param {
3513	uint32_t requester;
3514	uint32_t scan_id;
3515	enum scan_cancel_req_type req_type;
3516	uint32_t vdev_id;
3517	uint32_t pdev_id;
3518};
3519
3520struct  wmi_bcn_send_from_host_cmd {
3521	uint32_t tlv_header;
3522	uint32_t vdev_id;
3523	uint32_t data_len;
3524	union {
3525		uint32_t frag_ptr;
3526		uint32_t frag_ptr_lo;
3527	};
3528	uint32_t frame_ctrl;
3529	uint32_t dtim_flag;
3530	uint32_t bcn_antenna;
3531	uint32_t frag_ptr_hi;
3532};
3533
3534#define WMI_CHAN_INFO_MODE		GENMASK(5, 0)
3535#define WMI_CHAN_INFO_HT40_PLUS		BIT(6)
3536#define WMI_CHAN_INFO_PASSIVE		BIT(7)
3537#define WMI_CHAN_INFO_ADHOC_ALLOWED	BIT(8)
3538#define WMI_CHAN_INFO_AP_DISABLED	BIT(9)
3539#define WMI_CHAN_INFO_DFS		BIT(10)
3540#define WMI_CHAN_INFO_ALLOW_HT		BIT(11)
3541#define WMI_CHAN_INFO_ALLOW_VHT		BIT(12)
3542#define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA	BIT(13)
3543#define WMI_CHAN_INFO_HALF_RATE		BIT(14)
3544#define WMI_CHAN_INFO_QUARTER_RATE	BIT(15)
3545#define WMI_CHAN_INFO_DFS_FREQ2		BIT(16)
3546#define WMI_CHAN_INFO_ALLOW_HE		BIT(17)
3547#define WMI_CHAN_INFO_PSC		BIT(18)
3548
3549#define WMI_CHAN_REG_INFO1_MIN_PWR	GENMASK(7, 0)
3550#define WMI_CHAN_REG_INFO1_MAX_PWR	GENMASK(15, 8)
3551#define WMI_CHAN_REG_INFO1_MAX_REG_PWR	GENMASK(23, 16)
3552#define WMI_CHAN_REG_INFO1_REG_CLS	GENMASK(31, 24)
3553
3554#define WMI_CHAN_REG_INFO2_ANT_MAX	GENMASK(7, 0)
3555#define WMI_CHAN_REG_INFO2_MAX_TX_PWR	GENMASK(15, 8)
3556
3557struct wmi_channel {
3558	uint32_t tlv_header;
3559	uint32_t mhz;
3560	uint32_t band_center_freq1;
3561	uint32_t band_center_freq2;
3562	uint32_t info;
3563	uint32_t reg_info_1;
3564	uint32_t reg_info_2;
3565} __packed;
3566
3567struct wmi_mgmt_params {
3568	void *tx_frame;
3569	uint16_t frm_len;
3570	uint8_t vdev_id;
3571	uint16_t chanfreq;
3572	void *pdata;
3573	uint16_t desc_id;
3574	uint8_t *macaddr;
3575};
3576
3577enum wmi_sta_ps_mode {
3578	WMI_STA_PS_MODE_DISABLED = 0,
3579	WMI_STA_PS_MODE_ENABLED = 1,
3580};
3581
3582#define WMI_SMPS_MASK_LOWER_16BITS 0xFF
3583#define WMI_SMPS_MASK_UPPER_3BITS 0x7
3584#define WMI_SMPS_PARAM_VALUE_SHIFT 29
3585
3586#define ATH12K_WMI_FW_HANG_ASSERT_TYPE 1
3587#define ATH12K_WMI_FW_HANG_DELAY 0
3588
3589/* type, 0:unused 1: ASSERT 2: not respond detect command
3590 * delay_time_ms, the simulate will delay time
3591 */
3592
3593struct wmi_force_fw_hang_cmd {
3594	uint32_t tlv_header;
3595	uint32_t type;
3596	uint32_t delay_time_ms;
3597};
3598
3599struct wmi_vdev_set_param_cmd {
3600	uint32_t tlv_header;
3601	uint32_t vdev_id;
3602	uint32_t param_id;
3603	uint32_t param_value;
3604} __packed;
3605
3606enum wmi_stats_id {
3607	WMI_REQUEST_PEER_STAT			= BIT(0),
3608	WMI_REQUEST_AP_STAT			= BIT(1),
3609	WMI_REQUEST_PDEV_STAT			= BIT(2),
3610	WMI_REQUEST_VDEV_STAT			= BIT(3),
3611	WMI_REQUEST_BCNFLT_STAT			= BIT(4),
3612	WMI_REQUEST_VDEV_RATE_STAT		= BIT(5),
3613	WMI_REQUEST_INST_STAT			= BIT(6),
3614	WMI_REQUEST_MIB_STAT			= BIT(7),
3615	WMI_REQUEST_RSSI_PER_CHAIN_STAT		= BIT(8),
3616	WMI_REQUEST_CONGESTION_STAT		= BIT(9),
3617	WMI_REQUEST_PEER_EXTD_STAT		= BIT(10),
3618	WMI_REQUEST_BCN_STAT			= BIT(11),
3619	WMI_REQUEST_BCN_STAT_RESET		= BIT(12),
3620	WMI_REQUEST_PEER_EXTD2_STAT		= BIT(13),
3621};
3622
3623struct wmi_request_stats_cmd {
3624	uint32_t tlv_header;
3625	enum wmi_stats_id stats_id;
3626	uint32_t vdev_id;
3627	struct wmi_mac_addr peer_macaddr;
3628	uint32_t pdev_id;
3629} __packed;
3630
3631struct wmi_get_pdev_temperature_cmd {
3632	uint32_t tlv_header;
3633	uint32_t param;
3634	uint32_t pdev_id;
3635} __packed;
3636
3637struct wmi_ftm_seg_hdr {
3638	uint32_t len;
3639	uint32_t msgref;
3640	uint32_t segmentinfo;
3641	uint32_t pdev_id;
3642} __packed;
3643
3644struct wmi_ftm_cmd {
3645	uint32_t tlv_header;
3646	struct wmi_ftm_seg_hdr seg_hdr;
3647	uint8_t data[];
3648} __packed;
3649
3650struct wmi_ftm_event_msg {
3651	struct wmi_ftm_seg_hdr seg_hdr;
3652	uint8_t data[];
3653} __packed;
3654
3655#define WMI_BEACON_TX_BUFFER_SIZE	512
3656
3657#define WMI_EMA_TMPL_IDX_SHIFT            8
3658#define WMI_EMA_FIRST_TMPL_SHIFT          16
3659#define WMI_EMA_LAST_TMPL_SHIFT           24
3660
3661struct wmi_bcn_tmpl_cmd {
3662	uint32_t tlv_header;
3663	uint32_t vdev_id;
3664	uint32_t tim_ie_offset;
3665	uint32_t buf_len;
3666	uint32_t csa_switch_count_offset;
3667	uint32_t ext_csa_switch_count_offset;
3668	uint32_t csa_event_bitmap;
3669	uint32_t mbssid_ie_offset;
3670	uint32_t esp_ie_offset;
3671	uint32_t csc_switch_count_offset;
3672	uint32_t csc_event_bitmap;
3673	uint32_t mu_edca_ie_offset;
3674	uint32_t feature_enable_bitmap;
3675	uint32_t ema_params;
3676} __packed;
3677
3678struct wmi_key_seq_counter {
3679	uint32_t key_seq_counter_l;
3680	uint32_t key_seq_counter_h;
3681} __packed;
3682
3683struct wmi_vdev_install_key_cmd {
3684	uint32_t tlv_header;
3685	uint32_t vdev_id;
3686	struct wmi_mac_addr peer_macaddr;
3687	uint32_t key_idx;
3688	uint32_t key_flags;
3689	uint32_t key_cipher;
3690	struct wmi_key_seq_counter key_rsc_counter;
3691	struct wmi_key_seq_counter key_global_rsc_counter;
3692	struct wmi_key_seq_counter key_tsc_counter;
3693	uint8_t wpi_key_rsc_counter[16];
3694	uint8_t wpi_key_tsc_counter[16];
3695	uint32_t key_len;
3696	uint32_t key_txmic_len;
3697	uint32_t key_rxmic_len;
3698	uint32_t is_group_key_id_valid;
3699	uint32_t group_key_id;
3700
3701	/* Followed by key_data containing key followed by
3702	 * tx mic and then rx mic
3703	 */
3704} __packed;
3705
3706struct wmi_vdev_install_key_arg {
3707	uint32_t vdev_id;
3708	const uint8_t *macaddr;
3709	uint32_t key_idx;
3710	uint32_t key_flags;
3711	uint32_t key_cipher;
3712	uint32_t key_len;
3713	uint32_t key_txmic_len;
3714	uint32_t key_rxmic_len;
3715	uint64_t key_rsc_counter;
3716	const void *key_data;
3717};
3718
3719#define WMI_MAX_SUPPORTED_RATES			128
3720#define WMI_HOST_MAX_HECAP_PHY_SIZE		3
3721#define WMI_HOST_MAX_HE_RATE_SET		3
3722#define WMI_HECAP_TXRX_MCS_NSS_IDX_80		0
3723#define WMI_HECAP_TXRX_MCS_NSS_IDX_160		1
3724#define WMI_HECAP_TXRX_MCS_NSS_IDX_80_80	2
3725
3726struct wmi_rate_set_arg {
3727	uint32_t num_rates;
3728	uint8_t rates[WMI_MAX_SUPPORTED_RATES];
3729};
3730
3731struct peer_assoc_params {
3732	struct wmi_mac_addr peer_macaddr;
3733	uint32_t vdev_id;
3734	uint32_t peer_new_assoc;
3735	uint32_t peer_associd;
3736	uint32_t peer_flags;
3737	uint32_t peer_caps;
3738	uint32_t peer_listen_intval;
3739	uint32_t peer_ht_caps;
3740	uint32_t peer_max_mpdu;
3741	uint32_t peer_mpdu_density;
3742	uint32_t peer_rate_caps;
3743	uint32_t peer_nss;
3744	uint32_t peer_vht_caps;
3745	uint32_t peer_phymode;
3746	uint32_t peer_ht_info[2];
3747	struct wmi_rate_set_arg peer_legacy_rates;
3748	struct wmi_rate_set_arg peer_ht_rates;
3749	uint32_t rx_max_rate;
3750	uint32_t rx_mcs_set;
3751	uint32_t tx_max_rate;
3752	uint32_t tx_mcs_set;
3753	uint8_t vht_capable;
3754	uint8_t min_data_rate;
3755	uint32_t tx_max_mcs_nss;
3756	uint32_t peer_bw_rxnss_override;
3757	bool is_pmf_enabled;
3758	bool is_wme_set;
3759	bool qos_flag;
3760	bool apsd_flag;
3761	bool ht_flag;
3762	bool bw_40;
3763	bool bw_80;
3764	bool bw_160;
3765	bool stbc_flag;
3766	bool ldpc_flag;
3767	bool static_mimops_flag;
3768	bool dynamic_mimops_flag;
3769	bool spatial_mux_flag;
3770	bool vht_flag;
3771	bool vht_ng_flag;
3772	bool need_ptk_4_way;
3773	bool need_gtk_2_way;
3774	bool auth_flag;
3775	bool safe_mode_enabled;
3776	bool amsdu_disable;
3777	/* Use common structure */
3778	uint8_t peer_mac[IEEE80211_ADDR_LEN];
3779
3780	bool he_flag;
3781	uint32_t peer_he_cap_macinfo[2];
3782	uint32_t peer_he_cap_macinfo_internal;
3783	uint32_t peer_he_caps_6ghz;
3784	uint32_t peer_he_ops;
3785	uint32_t peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE];
3786	uint32_t peer_he_mcs_count;
3787	uint32_t peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3788	uint32_t peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3789	bool twt_responder;
3790	bool twt_requester;
3791	bool is_assoc;
3792	struct ath12k_ppe_threshold peer_ppet;
3793};
3794
3795struct  wmi_peer_assoc_complete_cmd {
3796	uint32_t tlv_header;
3797	struct wmi_mac_addr peer_macaddr;
3798	uint32_t vdev_id;
3799	uint32_t peer_new_assoc;
3800	uint32_t peer_associd;
3801	uint32_t peer_flags;
3802	uint32_t peer_caps;
3803	uint32_t peer_listen_intval;
3804	uint32_t peer_ht_caps;
3805	uint32_t peer_max_mpdu;
3806	uint32_t peer_mpdu_density;
3807	uint32_t peer_rate_caps;
3808	uint32_t peer_nss;
3809	uint32_t peer_vht_caps;
3810	uint32_t peer_phymode;
3811	uint32_t peer_ht_info[2];
3812	uint32_t num_peer_legacy_rates;
3813	uint32_t num_peer_ht_rates;
3814	uint32_t peer_bw_rxnss_override;
3815	struct  wmi_ppe_threshold peer_ppet;
3816	uint32_t peer_he_cap_info;
3817	uint32_t peer_he_ops;
3818	uint32_t peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE];
3819	uint32_t peer_he_mcs;
3820	uint32_t peer_he_cap_info_ext;
3821	uint32_t peer_he_cap_info_internal;
3822	uint32_t min_data_rate;
3823	uint32_t peer_he_caps_6ghz;
3824} __packed;
3825
3826struct wmi_stop_scan_cmd {
3827	uint32_t tlv_header;
3828	uint32_t requestor;
3829	uint32_t scan_id;
3830	uint32_t req_type;
3831	uint32_t vdev_id;
3832	uint32_t pdev_id;
3833};
3834
3835struct scan_chan_list_params {
3836	uint32_t pdev_id;
3837	uint16_t nallchans;
3838	struct channel_param ch_param[];
3839};
3840
3841struct wmi_scan_chan_list_cmd {
3842	uint32_t tlv_header;
3843	uint32_t num_scan_chans;
3844	uint32_t flags;
3845	uint32_t pdev_id;
3846} __packed;
3847
3848struct wmi_scan_prob_req_oui_cmd {
3849	uint32_t tlv_header;
3850	uint32_t prob_req_oui;
3851}  __packed;
3852
3853#define WMI_MGMT_SEND_DOWNLD_LEN	64
3854
3855#define WMI_TX_PARAMS_DWORD0_POWER		GENMASK(7, 0)
3856#define WMI_TX_PARAMS_DWORD0_MCS_MASK		GENMASK(19, 8)
3857#define WMI_TX_PARAMS_DWORD0_NSS_MASK		GENMASK(27, 20)
3858#define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT	GENMASK(31, 28)
3859
3860#define WMI_TX_PARAMS_DWORD1_CHAIN_MASK		GENMASK(7, 0)
3861#define WMI_TX_PARAMS_DWORD1_BW_MASK		GENMASK(14, 8)
3862#define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE	GENMASK(19, 15)
3863#define WMI_TX_PARAMS_DWORD1_FRAME_TYPE		BIT(20)
3864#define WMI_TX_PARAMS_DWORD1_RSVD		GENMASK(31, 21)
3865
3866struct wmi_mgmt_send_cmd {
3867	uint32_t tlv_header;
3868	uint32_t vdev_id;
3869	uint32_t desc_id;
3870	uint32_t chanfreq;
3871	uint32_t paddr_lo;
3872	uint32_t paddr_hi;
3873	uint32_t frame_len;
3874	uint32_t buf_len;
3875	uint32_t tx_params_valid;
3876
3877	/*
3878	 * Followed by struct wmi_tlv and buf_len bytes of frame data with
3879	 * buf_len <= WMI_MGMT_SEND_DOWNLD_LEN, which may be exceeded by
3880	 * frame_len. The full frame is mapped at paddr_lo/hi.
3881	 * Presumably the idea is that small frames can skip the extra DMA
3882	 * transfer of frame data after the command has been transferred.
3883	 */
3884} __packed;
3885
3886struct wmi_sta_powersave_mode_cmd {
3887	uint32_t tlv_header;
3888	uint32_t vdev_id;
3889	uint32_t sta_ps_mode;
3890};
3891
3892struct wmi_sta_smps_force_mode_cmd {
3893	uint32_t tlv_header;
3894	uint32_t vdev_id;
3895	uint32_t forced_mode;
3896};
3897
3898struct wmi_sta_smps_param_cmd {
3899	uint32_t tlv_header;
3900	uint32_t vdev_id;
3901	uint32_t param;
3902	uint32_t value;
3903};
3904
3905struct wmi_bcn_prb_info {
3906	uint32_t tlv_header;
3907	uint32_t caps;
3908	uint32_t erp;
3909} __packed;
3910
3911enum {
3912	WMI_PDEV_SUSPEND,
3913	WMI_PDEV_SUSPEND_AND_DISABLE_INTR,
3914};
3915
3916struct green_ap_ps_params {
3917	uint32_t value;
3918};
3919
3920struct wmi_pdev_green_ap_ps_enable_cmd_param {
3921	uint32_t tlv_header;
3922	uint32_t pdev_id;
3923	uint32_t enable;
3924};
3925
3926struct ap_ps_params {
3927	uint32_t vdev_id;
3928	uint32_t param;
3929	uint32_t value;
3930};
3931
3932struct vdev_set_params {
3933	uint32_t if_id;
3934	uint32_t param_id;
3935	uint32_t param_value;
3936};
3937
3938struct stats_request_params {
3939	uint32_t stats_id;
3940	uint32_t vdev_id;
3941	uint32_t pdev_id;
3942};
3943
3944struct wmi_set_current_country_params {
3945	uint8_t alpha2[3];
3946};
3947
3948struct wmi_set_current_country_cmd {
3949	uint32_t tlv_header;
3950	uint32_t pdev_id;
3951	uint32_t new_alpha2;
3952} __packed;
3953
3954enum set_init_cc_type {
3955	WMI_COUNTRY_INFO_TYPE_ALPHA,
3956	WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE,
3957	WMI_COUNTRY_INFO_TYPE_REGDOMAIN,
3958};
3959
3960enum set_init_cc_flags {
3961	INVALID_CC,
3962	CC_IS_SET,
3963	REGDMN_IS_SET,
3964	ALPHA_IS_SET,
3965};
3966
3967struct wmi_init_country_params {
3968	union {
3969		uint16_t country_code;
3970		uint16_t regdom_id;
3971		uint8_t alpha2[3];
3972	} cc_info;
3973	enum set_init_cc_flags flags;
3974};
3975
3976struct wmi_init_country_cmd {
3977	uint32_t tlv_header;
3978	uint32_t pdev_id;
3979	uint32_t init_cc_type;
3980	union {
3981		uint32_t country_code;
3982		uint32_t regdom_id;
3983		uint32_t alpha2;
3984	} cc_info;
3985} __packed;
3986
3987struct wmi_11d_scan_start_params {
3988	uint32_t vdev_id;
3989	uint32_t scan_period_msec;
3990	uint32_t start_interval_msec;
3991};
3992
3993struct wmi_11d_scan_start_cmd {
3994	uint32_t tlv_header;
3995	uint32_t vdev_id;
3996	uint32_t scan_period_msec;
3997	uint32_t start_interval_msec;
3998} __packed;
3999
4000struct wmi_11d_scan_stop_cmd {
4001	uint32_t tlv_header;
4002	uint32_t vdev_id;
4003} __packed;
4004
4005struct wmi_11d_new_cc_ev {
4006	uint32_t new_alpha2;
4007} __packed;
4008
4009#define THERMAL_LEVELS  1
4010struct tt_level_config {
4011	uint32_t tmplwm;
4012	uint32_t tmphwm;
4013	uint32_t dcoffpercent;
4014	uint32_t priority;
4015};
4016
4017struct thermal_mitigation_params {
4018	uint32_t pdev_id;
4019	uint32_t enable;
4020	uint32_t dc;
4021	uint32_t dc_per_event;
4022	struct tt_level_config levelconf[THERMAL_LEVELS];
4023};
4024
4025struct wmi_therm_throt_config_request_cmd {
4026	uint32_t tlv_header;
4027	uint32_t pdev_id;
4028	uint32_t enable;
4029	uint32_t dc;
4030	uint32_t dc_per_event;
4031	uint32_t therm_throt_levels;
4032} __packed;
4033
4034struct wmi_therm_throt_level_config_info {
4035	uint32_t tlv_header;
4036	uint32_t temp_lwm;
4037	uint32_t temp_hwm;
4038	uint32_t dc_off_percent;
4039	uint32_t prio;
4040} __packed;
4041
4042struct wmi_delba_send_cmd {
4043	uint32_t tlv_header;
4044	uint32_t vdev_id;
4045	struct wmi_mac_addr peer_macaddr;
4046	uint32_t tid;
4047	uint32_t initiator;
4048	uint32_t reasoncode;
4049} __packed;
4050
4051struct wmi_addba_setresponse_cmd {
4052	uint32_t tlv_header;
4053	uint32_t vdev_id;
4054	struct wmi_mac_addr peer_macaddr;
4055	uint32_t tid;
4056	uint32_t statuscode;
4057} __packed;
4058
4059struct wmi_addba_send_cmd {
4060	uint32_t tlv_header;
4061	uint32_t vdev_id;
4062	struct wmi_mac_addr peer_macaddr;
4063	uint32_t tid;
4064	uint32_t buffersize;
4065} __packed;
4066
4067struct wmi_addba_clear_resp_cmd {
4068	uint32_t tlv_header;
4069	uint32_t vdev_id;
4070	struct wmi_mac_addr peer_macaddr;
4071} __packed;
4072
4073struct wmi_pdev_pktlog_filter_info {
4074	uint32_t tlv_header;
4075	struct wmi_mac_addr peer_macaddr;
4076} __packed;
4077
4078struct wmi_pdev_pktlog_filter_cmd {
4079	uint32_t tlv_header;
4080	uint32_t pdev_id;
4081	uint32_t enable;
4082	uint32_t filter_type;
4083	uint32_t num_mac;
4084} __packed;
4085
4086enum ath12k_wmi_pktlog_enable {
4087	ATH12K_WMI_PKTLOG_ENABLE_AUTO  = 0,
4088	ATH12K_WMI_PKTLOG_ENABLE_FORCE = 1,
4089};
4090
4091struct wmi_pktlog_enable_cmd {
4092	uint32_t tlv_header;
4093	uint32_t pdev_id;
4094	uint32_t evlist; /* WMI_PKTLOG_EVENT */
4095	uint32_t enable;
4096} __packed;
4097
4098struct wmi_pktlog_disable_cmd {
4099	uint32_t tlv_header;
4100	uint32_t pdev_id;
4101} __packed;
4102
4103#define DFS_PHYERR_UNIT_TEST_CMD 0
4104#define DFS_UNIT_TEST_MODULE	0x2b
4105#define DFS_UNIT_TEST_TOKEN	0xAA
4106
4107enum dfs_test_args_idx {
4108	DFS_TEST_CMDID = 0,
4109	DFS_TEST_PDEV_ID,
4110	DFS_TEST_RADAR_PARAM,
4111	DFS_MAX_TEST_ARGS,
4112};
4113
4114struct wmi_dfs_unit_test_arg {
4115	uint32_t cmd_id;
4116	uint32_t pdev_id;
4117	uint32_t radar_param;
4118};
4119
4120struct wmi_unit_test_cmd {
4121	uint32_t tlv_header;
4122	uint32_t vdev_id;
4123	uint32_t module_id;
4124	uint32_t num_args;
4125	uint32_t diag_token;
4126	/* Followed by test args*/
4127} __packed;
4128
4129#define MAX_SUPPORTED_RATES 128
4130
4131#define WMI_PEER_AUTH		0x00000001
4132#define WMI_PEER_QOS		0x00000002
4133#define WMI_PEER_NEED_PTK_4_WAY	0x00000004
4134#define WMI_PEER_NEED_GTK_2_WAY	0x00000010
4135#define WMI_PEER_HE		0x00000400
4136#define WMI_PEER_APSD		0x00000800
4137#define WMI_PEER_HT		0x00001000
4138#define WMI_PEER_40MHZ		0x00002000
4139#define WMI_PEER_STBC		0x00008000
4140#define WMI_PEER_LDPC		0x00010000
4141#define WMI_PEER_DYN_MIMOPS	0x00020000
4142#define WMI_PEER_STATIC_MIMOPS	0x00040000
4143#define WMI_PEER_SPATIAL_MUX	0x00200000
4144#define WMI_PEER_TWT_REQ	0x00400000
4145#define WMI_PEER_TWT_RESP	0x00800000
4146#define WMI_PEER_VHT		0x02000000
4147#define WMI_PEER_80MHZ		0x04000000
4148#define WMI_PEER_PMF		0x08000000
4149/* TODO: Place holder for WLAN_PEER_F_PS_PRESEND_REQUIRED = 0x10000000.
4150 * Need to be cleaned up
4151 */
4152#define WMI_PEER_IS_P2P_CAPABLE	0x20000000
4153#define WMI_PEER_160MHZ		0x40000000
4154#define WMI_PEER_SAFEMODE_EN	0x80000000
4155
4156struct beacon_tmpl_params {
4157	uint8_t vdev_id;
4158	uint32_t tim_ie_offset;
4159	uint32_t tmpl_len;
4160	uint32_t tmpl_len_aligned;
4161	uint32_t csa_switch_count_offset;
4162	uint32_t ext_csa_switch_count_offset;
4163	uint8_t *frm;
4164};
4165
4166struct wmi_rate_set {
4167	uint32_t num_rates;
4168	uint32_t rates[(MAX_SUPPORTED_RATES / 4) + 1];
4169};
4170
4171struct wmi_vht_rate_set {
4172	uint32_t tlv_header;
4173	uint32_t rx_max_rate;
4174	uint32_t rx_mcs_set;
4175	uint32_t tx_max_rate;
4176	uint32_t tx_mcs_set;
4177	uint32_t tx_max_mcs_nss;
4178} __packed;
4179
4180struct wmi_he_rate_set {
4181	uint32_t tlv_header;
4182
4183	/* MCS at which the peer can receive */
4184	uint32_t rx_mcs_set;
4185
4186	/* MCS at which the peer can transmit */
4187	uint32_t tx_mcs_set;
4188} __packed;
4189
4190#define MAX_REG_RULES 10
4191#define REG_ALPHA2_LEN 2
4192#define MAX_6GHZ_REG_RULES 5
4193
4194enum wmi_start_event_param {
4195	WMI_VDEV_START_RESP_EVENT = 0,
4196	WMI_VDEV_RESTART_RESP_EVENT,
4197};
4198
4199struct wmi_vdev_start_resp_event {
4200	uint32_t vdev_id;
4201	uint32_t requestor_id;
4202	enum wmi_start_event_param resp_type;
4203	uint32_t status;
4204	uint32_t chain_mask;
4205	uint32_t smps_mode;
4206	union {
4207		uint32_t mac_id;
4208		uint32_t pdev_id;
4209	};
4210	uint32_t cfgd_tx_streams;
4211	uint32_t cfgd_rx_streams;
4212} __packed;
4213
4214/* VDEV start response status codes */
4215enum wmi_vdev_start_resp_status_code {
4216	WMI_VDEV_START_RESPONSE_STATUS_SUCCESS = 0,
4217	WMI_VDEV_START_RESPONSE_INVALID_VDEVID = 1,
4218	WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2,
4219	WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3,
4220	WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4,
4221};
4222
4223/* Regulatory Rule Flags Passed by FW */
4224#define REGULATORY_CHAN_DISABLED     BIT(0)
4225#define REGULATORY_CHAN_NO_IR        BIT(1)
4226#define REGULATORY_CHAN_RADAR        BIT(3)
4227#define REGULATORY_CHAN_NO_OFDM      BIT(6)
4228#define REGULATORY_CHAN_INDOOR_ONLY  BIT(9)
4229
4230#define REGULATORY_CHAN_NO_HT40      BIT(4)
4231#define REGULATORY_CHAN_NO_80MHZ     BIT(7)
4232#define REGULATORY_CHAN_NO_160MHZ    BIT(8)
4233#define REGULATORY_CHAN_NO_20MHZ     BIT(11)
4234#define REGULATORY_CHAN_NO_10MHZ     BIT(12)
4235
4236enum wmi_reg_chan_list_cmd_type {
4237	WMI_REG_CHAN_LIST_CC_ID = 0,
4238	WMI_REG_CHAN_LIST_CC_EXT_ID = 1,
4239};
4240
4241enum wmi_reg_cc_setting_code {
4242	WMI_REG_SET_CC_STATUS_PASS = 0,
4243	WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1,
4244	WMI_REG_INIT_ALPHA2_NOT_FOUND = 2,
4245	WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3,
4246	WMI_REG_SET_CC_STATUS_NO_MEMORY = 4,
4247	WMI_REG_SET_CC_STATUS_FAIL = 5,
4248
4249	/* add new setting code above, update in
4250	 * @enum cc_setting_code as well.
4251	 * Also handle it in ath12k_wmi_cc_setting_code_to_reg()
4252	 */
4253};
4254
4255enum cc_setting_code {
4256	REG_SET_CC_STATUS_PASS = 0,
4257	REG_CURRENT_ALPHA2_NOT_FOUND = 1,
4258	REG_INIT_ALPHA2_NOT_FOUND = 2,
4259	REG_SET_CC_CHANGE_NOT_ALLOWED = 3,
4260	REG_SET_CC_STATUS_NO_MEMORY = 4,
4261	REG_SET_CC_STATUS_FAIL = 5,
4262
4263	/* add new setting code above, update in
4264	 * @enum wmi_reg_cc_setting_code as well.
4265	 * Also handle it in ath12k_cc_status_to_str()
4266	 */
4267};
4268
4269static inline enum cc_setting_code
4270qwz_wmi_cc_setting_code_to_reg(enum wmi_reg_cc_setting_code status_code)
4271{
4272	switch (status_code) {
4273	case WMI_REG_SET_CC_STATUS_PASS:
4274		return REG_SET_CC_STATUS_PASS;
4275	case WMI_REG_CURRENT_ALPHA2_NOT_FOUND:
4276		return REG_CURRENT_ALPHA2_NOT_FOUND;
4277	case WMI_REG_INIT_ALPHA2_NOT_FOUND:
4278		return REG_INIT_ALPHA2_NOT_FOUND;
4279	case WMI_REG_SET_CC_CHANGE_NOT_ALLOWED:
4280		return REG_SET_CC_CHANGE_NOT_ALLOWED;
4281	case WMI_REG_SET_CC_STATUS_NO_MEMORY:
4282		return REG_SET_CC_STATUS_NO_MEMORY;
4283	case WMI_REG_SET_CC_STATUS_FAIL:
4284		return REG_SET_CC_STATUS_FAIL;
4285	}
4286
4287	return REG_SET_CC_STATUS_FAIL;
4288}
4289
4290static inline const char *
4291qwz_cc_status_to_str(enum cc_setting_code code)
4292{
4293	switch (code) {
4294	case REG_SET_CC_STATUS_PASS:
4295		return "REG_SET_CC_STATUS_PASS";
4296	case REG_CURRENT_ALPHA2_NOT_FOUND:
4297		return "REG_CURRENT_ALPHA2_NOT_FOUND";
4298	case REG_INIT_ALPHA2_NOT_FOUND:
4299		return "REG_INIT_ALPHA2_NOT_FOUND";
4300	case REG_SET_CC_CHANGE_NOT_ALLOWED:
4301		return "REG_SET_CC_CHANGE_NOT_ALLOWED";
4302	case REG_SET_CC_STATUS_NO_MEMORY:
4303		return "REG_SET_CC_STATUS_NO_MEMORY";
4304	case REG_SET_CC_STATUS_FAIL:
4305		return "REG_SET_CC_STATUS_FAIL";
4306	}
4307
4308	return "Unknown CC status";
4309}
4310
4311enum wmi_reg_6ghz_ap_type {
4312	WMI_REG_INDOOR_AP = 0,
4313	WMI_REG_STANDARD_POWER_AP = 1,
4314	WMI_REG_VERY_LOW_POWER_AP = 2,
4315
4316	/* add AP type above, handle in ath12k_6ghz_ap_type_to_str()
4317	 */
4318	WMI_REG_CURRENT_MAX_AP_TYPE,
4319	WMI_REG_MAX_AP_TYPE = 7,
4320};
4321
4322static inline const char *
4323qwz_6ghz_ap_type_to_str(enum wmi_reg_6ghz_ap_type type)
4324{
4325	switch (type) {
4326	case WMI_REG_INDOOR_AP:
4327		return "INDOOR AP";
4328	case WMI_REG_STANDARD_POWER_AP:
4329		return "STANDARD POWER AP";
4330	case WMI_REG_VERY_LOW_POWER_AP:
4331		return "VERY LOW POWER AP";
4332	case WMI_REG_CURRENT_MAX_AP_TYPE:
4333		return "CURRENT_MAX_AP_TYPE";
4334	case WMI_REG_MAX_AP_TYPE:
4335		return "MAX_AP_TYPE";
4336	}
4337
4338	return "unknown 6 GHz AP type";
4339}
4340
4341enum wmi_reg_6ghz_client_type {
4342	WMI_REG_DEFAULT_CLIENT = 0,
4343	WMI_REG_SUBORDINATE_CLIENT = 1,
4344	WMI_REG_MAX_CLIENT_TYPE = 2,
4345
4346	/* add client type above, handle it in
4347	 * ath12k_6ghz_client_type_to_str()
4348	 */
4349};
4350
4351static inline const char *
4352qwz_6ghz_client_type_to_str(enum wmi_reg_6ghz_client_type type)
4353{
4354	switch (type) {
4355	case WMI_REG_DEFAULT_CLIENT:
4356		return "DEFAULT CLIENT";
4357	case WMI_REG_SUBORDINATE_CLIENT:
4358		return "SUBORDINATE CLIENT";
4359	case WMI_REG_MAX_CLIENT_TYPE:
4360		return "MAX_CLIENT_TYPE";
4361	}
4362
4363	return "unknown 6 GHz client type";
4364}
4365
4366enum reg_subdomains_6ghz {
4367	EMPTY_6GHZ = 0x0,
4368	FCC1_CLIENT_LPI_REGULAR_6GHZ = 0x01,
4369	FCC1_CLIENT_SP_6GHZ = 0x02,
4370	FCC1_AP_LPI_6GHZ = 0x03,
4371	FCC1_CLIENT_LPI_SUBORDINATE = FCC1_AP_LPI_6GHZ,
4372	FCC1_AP_SP_6GHZ = 0x04,
4373	ETSI1_LPI_6GHZ = 0x10,
4374	ETSI1_VLP_6GHZ = 0x11,
4375	ETSI2_LPI_6GHZ = 0x12,
4376	ETSI2_VLP_6GHZ = 0x13,
4377	APL1_LPI_6GHZ = 0x20,
4378	APL1_VLP_6GHZ = 0x21,
4379
4380	/* add sub-domain above, handle it in
4381	 * ath12k_sub_reg_6ghz_to_str()
4382	 */
4383};
4384
4385static inline const char *
4386qwz_sub_reg_6ghz_to_str(enum reg_subdomains_6ghz sub_id)
4387{
4388	switch (sub_id) {
4389	case EMPTY_6GHZ:
4390		return "N/A";
4391	case FCC1_CLIENT_LPI_REGULAR_6GHZ:
4392		return "FCC1_CLIENT_LPI_REGULAR_6GHZ";
4393	case FCC1_CLIENT_SP_6GHZ:
4394		return "FCC1_CLIENT_SP_6GHZ";
4395	case FCC1_AP_LPI_6GHZ:
4396		return "FCC1_AP_LPI_6GHZ/FCC1_CLIENT_LPI_SUBORDINATE";
4397	case FCC1_AP_SP_6GHZ:
4398		return "FCC1_AP_SP_6GHZ";
4399	case ETSI1_LPI_6GHZ:
4400		return "ETSI1_LPI_6GHZ";
4401	case ETSI1_VLP_6GHZ:
4402		return "ETSI1_VLP_6GHZ";
4403	case ETSI2_LPI_6GHZ:
4404		return "ETSI2_LPI_6GHZ";
4405	case ETSI2_VLP_6GHZ:
4406		return "ETSI2_VLP_6GHZ";
4407	case APL1_LPI_6GHZ:
4408		return "APL1_LPI_6GHZ";
4409	case APL1_VLP_6GHZ:
4410		return "APL1_VLP_6GHZ";
4411	}
4412
4413	return "unknown sub reg id";
4414}
4415
4416enum reg_super_domain_6ghz {
4417	FCC1_6GHZ = 0x01,
4418	ETSI1_6GHZ = 0x02,
4419	ETSI2_6GHZ = 0x03,
4420	APL1_6GHZ = 0x04,
4421	FCC1_6GHZ_CL = 0x05,
4422
4423	/* add super domain above, handle it in
4424	 * ath12k_super_reg_6ghz_to_str()
4425	 */
4426};
4427
4428static inline const char *
4429qwz_super_reg_6ghz_to_str(enum reg_super_domain_6ghz domain_id)
4430{
4431	switch (domain_id) {
4432	case FCC1_6GHZ:
4433		return "FCC1_6GHZ";
4434	case ETSI1_6GHZ:
4435		return "ETSI1_6GHZ";
4436	case ETSI2_6GHZ:
4437		return "ETSI2_6GHZ";
4438	case APL1_6GHZ:
4439		return "APL1_6GHZ";
4440	case FCC1_6GHZ_CL:
4441		return "FCC1_6GHZ_CL";
4442	}
4443
4444	return "unknown domain id";
4445}
4446
4447struct cur_reg_rule {
4448	uint16_t start_freq;
4449	uint16_t end_freq;
4450	uint16_t max_bw;
4451	uint8_t reg_power;
4452	uint8_t ant_gain;
4453	uint16_t flags;
4454	bool psd_flag;
4455	int8_t psd_eirp;
4456};
4457
4458struct cur_regulatory_info {
4459	enum cc_setting_code status_code;
4460	uint8_t num_phy;
4461	uint8_t phy_id;
4462	uint16_t reg_dmn_pair;
4463	uint16_t ctry_code;
4464	uint8_t alpha2[REG_ALPHA2_LEN + 1];
4465	uint32_t dfs_region;
4466	uint32_t phybitmap;
4467	uint32_t min_bw_2ghz;
4468	uint32_t max_bw_2ghz;
4469	uint32_t min_bw_5ghz;
4470	uint32_t max_bw_5ghz;
4471	uint32_t num_2ghz_reg_rules;
4472	uint32_t num_5ghz_reg_rules;
4473	struct cur_reg_rule *reg_rules_2ghz_ptr;
4474	struct cur_reg_rule *reg_rules_5ghz_ptr;
4475	bool is_ext_reg_event;
4476	enum wmi_reg_6ghz_client_type client_type;
4477	bool rnr_tpe_usable;
4478	bool unspecified_ap_usable;
4479	uint8_t domain_code_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4480	uint8_t domain_code_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4481	uint32_t domain_code_6ghz_super_id;
4482	uint32_t min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4483	uint32_t max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4484	uint32_t min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4485	uint32_t max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4486	uint32_t num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4487	uint32_t num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4488	struct cur_reg_rule *reg_rules_6ghz_ap_ptr[WMI_REG_CURRENT_MAX_AP_TYPE];
4489	struct cur_reg_rule *reg_rules_6ghz_client_ptr
4490		[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4491};
4492
4493struct wmi_reg_chan_list_cc_event {
4494	uint32_t status_code;
4495	uint32_t phy_id;
4496	uint32_t alpha2;
4497	uint32_t num_phy;
4498	uint32_t country_id;
4499	uint32_t domain_code;
4500	uint32_t dfs_region;
4501	uint32_t phybitmap;
4502	uint32_t min_bw_2ghz;
4503	uint32_t max_bw_2ghz;
4504	uint32_t min_bw_5ghz;
4505	uint32_t max_bw_5ghz;
4506	uint32_t num_2ghz_reg_rules;
4507	uint32_t num_5ghz_reg_rules;
4508} __packed;
4509
4510struct wmi_regulatory_rule_struct {
4511	uint32_t  tlv_header;
4512	uint32_t  freq_info;
4513	uint32_t  bw_pwr_info;
4514	uint32_t  flag_info;
4515};
4516
4517#define WMI_REG_CLIENT_MAX 4
4518
4519struct wmi_reg_chan_list_cc_ext_event {
4520	uint32_t status_code;
4521	uint32_t phy_id;
4522	uint32_t alpha2;
4523	uint32_t num_phy;
4524	uint32_t country_id;
4525	uint32_t domain_code;
4526	uint32_t dfs_region;
4527	uint32_t phybitmap;
4528	uint32_t min_bw_2ghz;
4529	uint32_t max_bw_2ghz;
4530	uint32_t min_bw_5ghz;
4531	uint32_t max_bw_5ghz;
4532	uint32_t num_2ghz_reg_rules;
4533	uint32_t num_5ghz_reg_rules;
4534	uint32_t client_type;
4535	uint32_t rnr_tpe_usable;
4536	uint32_t unspecified_ap_usable;
4537	uint32_t domain_code_6ghz_ap_lpi;
4538	uint32_t domain_code_6ghz_ap_sp;
4539	uint32_t domain_code_6ghz_ap_vlp;
4540	uint32_t domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4541	uint32_t domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4542	uint32_t domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4543	uint32_t domain_code_6ghz_super_id;
4544	uint32_t min_bw_6ghz_ap_sp;
4545	uint32_t max_bw_6ghz_ap_sp;
4546	uint32_t min_bw_6ghz_ap_lpi;
4547	uint32_t max_bw_6ghz_ap_lpi;
4548	uint32_t min_bw_6ghz_ap_vlp;
4549	uint32_t max_bw_6ghz_ap_vlp;
4550	uint32_t min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4551	uint32_t max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4552	uint32_t min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4553	uint32_t max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4554	uint32_t min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4555	uint32_t max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4556	uint32_t num_6ghz_reg_rules_ap_sp;
4557	uint32_t num_6ghz_reg_rules_ap_lpi;
4558	uint32_t num_6ghz_reg_rules_ap_vlp;
4559	uint32_t num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX];
4560	uint32_t num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX];
4561	uint32_t num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX];
4562} __packed;
4563
4564struct wmi_regulatory_ext_rule {
4565	uint32_t tlv_header;
4566	uint32_t freq_info;
4567	uint32_t bw_pwr_info;
4568	uint32_t flag_info;
4569	uint32_t psd_power_info;
4570} __packed;
4571
4572struct wmi_vdev_delete_resp_event {
4573	uint32_t vdev_id;
4574} __packed;
4575
4576struct wmi_peer_delete_resp_event {
4577	uint32_t vdev_id;
4578	struct wmi_mac_addr peer_macaddr;
4579} __packed;
4580
4581struct wmi_bcn_tx_status_event {
4582	uint32_t vdev_id;
4583	uint32_t tx_status;
4584} __packed;
4585
4586struct wmi_vdev_stopped_event {
4587	uint32_t vdev_id;
4588} __packed;
4589
4590struct wmi_pdev_bss_chan_info_event {
4591	uint32_t freq;	/* Units in MHz */
4592	uint32_t noise_floor;	/* units are dBm */
4593	/* rx clear - how often the channel was unused */
4594	uint32_t rx_clear_count_low;
4595	uint32_t rx_clear_count_high;
4596	/* cycle count - elapsed time during measured period, in clock ticks */
4597	uint32_t cycle_count_low;
4598	uint32_t cycle_count_high;
4599	/* tx cycle count - elapsed time spent in tx, in clock ticks */
4600	uint32_t tx_cycle_count_low;
4601	uint32_t tx_cycle_count_high;
4602	/* rx cycle count - elapsed time spent in rx, in clock ticks */
4603	uint32_t rx_cycle_count_low;
4604	uint32_t rx_cycle_count_high;
4605	/*rx_cycle cnt for my bss in 64bits format */
4606	uint32_t rx_bss_cycle_count_low;
4607	uint32_t rx_bss_cycle_count_high;
4608	uint32_t pdev_id;
4609} __packed;
4610
4611#define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0
4612
4613struct wmi_vdev_install_key_compl_event {
4614	uint32_t vdev_id;
4615	struct wmi_mac_addr peer_macaddr;
4616	uint32_t key_idx;
4617	uint32_t key_flags;
4618	uint32_t status;
4619} __packed;
4620
4621struct wmi_vdev_install_key_complete_arg {
4622	uint32_t vdev_id;
4623	const uint8_t *macaddr;
4624	uint32_t key_idx;
4625	uint32_t key_flags;
4626	uint32_t status;
4627};
4628
4629struct wmi_peer_assoc_conf_event {
4630	uint32_t vdev_id;
4631	struct wmi_mac_addr peer_macaddr;
4632} __packed;
4633
4634struct wmi_peer_assoc_conf_arg {
4635	uint32_t vdev_id;
4636	const uint8_t *macaddr;
4637};
4638
4639struct wmi_fils_discovery_event {
4640	uint32_t vdev_id;
4641	uint32_t fils_tt;
4642	uint32_t tbtt;
4643} __packed;
4644
4645struct wmi_probe_resp_tx_status_event {
4646	uint32_t vdev_id;
4647	uint32_t tx_status;
4648} __packed;
4649
4650/*
4651 * PDEV statistics
4652 */
4653struct wmi_pdev_stats_base {
4654	int32_t chan_nf;
4655	uint32_t tx_frame_count; /* Cycles spent transmitting frames */
4656	uint32_t rx_frame_count; /* Cycles spent receiving frames */
4657	uint32_t rx_clear_count; /* Total channel busy time, evidently */
4658	uint32_t cycle_count; /* Total on-channel time */
4659	uint32_t phy_err_count;
4660	uint32_t chan_tx_pwr;
4661} __packed;
4662
4663struct wmi_pdev_stats_extra {
4664	uint32_t ack_rx_bad;
4665	uint32_t rts_bad;
4666	uint32_t rts_good;
4667	uint32_t fcs_bad;
4668	uint32_t no_beacons;
4669	uint32_t mib_int_count;
4670} __packed;
4671
4672struct wmi_pdev_stats_tx {
4673	/* Num HTT cookies queued to dispatch list */
4674	int32_t comp_queued;
4675
4676	/* Num HTT cookies dispatched */
4677	int32_t comp_delivered;
4678
4679	/* Num MSDU queued to WAL */
4680	int32_t msdu_enqued;
4681
4682	/* Num MPDU queue to WAL */
4683	int32_t mpdu_enqued;
4684
4685	/* Num MSDUs dropped by WMM limit */
4686	int32_t wmm_drop;
4687
4688	/* Num Local frames queued */
4689	int32_t local_enqued;
4690
4691	/* Num Local frames done */
4692	int32_t local_freed;
4693
4694	/* Num queued to HW */
4695	int32_t hw_queued;
4696
4697	/* Num PPDU reaped from HW */
4698	int32_t hw_reaped;
4699
4700	/* Num underruns */
4701	int32_t underrun;
4702
4703	/* Num hw paused */
4704	uint32_t hw_paused;
4705
4706	/* Num PPDUs cleaned up in TX abort */
4707	int32_t tx_abort;
4708
4709	/* Num MPDUs requeued by SW */
4710	int32_t mpdus_requeued;
4711
4712	/* excessive retries */
4713	uint32_t tx_ko;
4714
4715	uint32_t tx_xretry;
4716
4717	/* data hw rate code */
4718	uint32_t data_rc;
4719
4720	/* Scheduler self triggers */
4721	uint32_t self_triggers;
4722
4723	/* frames dropped due to excessive sw retries */
4724	uint32_t sw_retry_failure;
4725
4726	/* illegal rate phy errors  */
4727	uint32_t illgl_rate_phy_err;
4728
4729	/* wal pdev continuous xretry */
4730	uint32_t pdev_cont_xretry;
4731
4732	/* wal pdev tx timeouts */
4733	uint32_t pdev_tx_timeout;
4734
4735	/* wal pdev resets  */
4736	uint32_t pdev_resets;
4737
4738	/* frames dropped due to non-availability of stateless TIDs */
4739	uint32_t stateless_tid_alloc_failure;
4740
4741	/* PhY/BB underrun */
4742	uint32_t phy_underrun;
4743
4744	/* MPDU is more than txop limit */
4745	uint32_t txop_ovf;
4746
4747	/* Num sequences posted */
4748	uint32_t seq_posted;
4749
4750	/* Num sequences failed in queueing */
4751	uint32_t seq_failed_queueing;
4752
4753	/* Num sequences completed */
4754	uint32_t seq_completed;
4755
4756	/* Num sequences restarted */
4757	uint32_t seq_restarted;
4758
4759	/* Num of MU sequences posted */
4760	uint32_t mu_seq_posted;
4761
4762	/* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT
4763	 * (Reset,channel change)
4764	 */
4765	int32_t mpdus_sw_flush;
4766
4767	/* Num MPDUs filtered by HW, all filter condition (TTL expired) */
4768	int32_t mpdus_hw_filter;
4769
4770	/* Num MPDUs truncated by PDG (TXOP, TBTT,
4771	 * PPDU_duration based on rate, dyn_bw)
4772	 */
4773	int32_t mpdus_truncated;
4774
4775	/* Num MPDUs that was tried but didn't receive ACK or BA */
4776	int32_t mpdus_ack_failed;
4777
4778	/* Num MPDUs that was dropped du to expiry. */
4779	int32_t mpdus_expired;
4780} __packed;
4781
4782struct wmi_pdev_stats_rx {
4783	/* Cnts any change in ring routing mid-ppdu */
4784	int32_t mid_ppdu_route_change;
4785
4786	/* Total number of statuses processed */
4787	int32_t status_rcvd;
4788
4789	/* Extra frags on rings 0-3 */
4790	int32_t r0_frags;
4791	int32_t r1_frags;
4792	int32_t r2_frags;
4793	int32_t r3_frags;
4794
4795	/* MSDUs / MPDUs delivered to HTT */
4796	int32_t htt_msdus;
4797	int32_t htt_mpdus;
4798
4799	/* MSDUs / MPDUs delivered to local stack */
4800	int32_t loc_msdus;
4801	int32_t loc_mpdus;
4802
4803	/* AMSDUs that have more MSDUs than the status ring size */
4804	int32_t oversize_amsdu;
4805
4806	/* Number of PHY errors */
4807	int32_t phy_errs;
4808
4809	/* Number of PHY errors drops */
4810	int32_t phy_err_drop;
4811
4812	/* Number of mpdu errors - FCS, MIC, ENC etc. */
4813	int32_t mpdu_errs;
4814
4815	/* Num overflow errors */
4816	int32_t rx_ovfl_errs;
4817} __packed;
4818
4819struct wmi_pdev_stats {
4820	struct wmi_pdev_stats_base base;
4821	struct wmi_pdev_stats_tx tx;
4822	struct wmi_pdev_stats_rx rx;
4823} __packed;
4824
4825#define WLAN_MAX_AC 4
4826#define MAX_TX_RATE_VALUES 10
4827#define MAX_TX_RATE_VALUES 10
4828
4829struct wmi_vdev_stats {
4830	uint32_t vdev_id;
4831	uint32_t beacon_snr;
4832	uint32_t data_snr;
4833	uint32_t num_tx_frames[WLAN_MAX_AC];
4834	uint32_t num_rx_frames;
4835	uint32_t num_tx_frames_retries[WLAN_MAX_AC];
4836	uint32_t num_tx_frames_failures[WLAN_MAX_AC];
4837	uint32_t num_rts_fail;
4838	uint32_t num_rts_success;
4839	uint32_t num_rx_err;
4840	uint32_t num_rx_discard;
4841	uint32_t num_tx_not_acked;
4842	uint32_t tx_rate_history[MAX_TX_RATE_VALUES];
4843	uint32_t beacon_rssi_history[MAX_TX_RATE_VALUES];
4844} __packed;
4845
4846struct wmi_bcn_stats {
4847	uint32_t vdev_id;
4848	uint32_t tx_bcn_succ_cnt;
4849	uint32_t tx_bcn_outage_cnt;
4850} __packed;
4851
4852struct wmi_stats_event {
4853	uint32_t stats_id;
4854	uint32_t num_pdev_stats;
4855	uint32_t num_vdev_stats;
4856	uint32_t num_peer_stats;
4857	uint32_t num_bcnflt_stats;
4858	uint32_t num_chan_stats;
4859	uint32_t num_mib_stats;
4860	uint32_t pdev_id;
4861	uint32_t num_bcn_stats;
4862	uint32_t num_peer_extd_stats;
4863	uint32_t num_peer_extd2_stats;
4864} __packed;
4865
4866struct wmi_rssi_stats {
4867	uint32_t vdev_id;
4868	uint32_t rssi_avg_beacon[WMI_MAX_CHAINS];
4869	uint32_t rssi_avg_data[WMI_MAX_CHAINS];
4870	struct wmi_mac_addr peer_macaddr;
4871} __packed;
4872
4873struct wmi_per_chain_rssi_stats {
4874	uint32_t num_per_chain_rssi_stats;
4875} __packed;
4876
4877struct wmi_pdev_ctl_failsafe_chk_event {
4878	uint32_t pdev_id;
4879	uint32_t ctl_failsafe_status;
4880} __packed;
4881
4882struct wmi_pdev_csa_switch_ev {
4883	uint32_t pdev_id;
4884	uint32_t current_switch_count;
4885	uint32_t num_vdevs;
4886} __packed;
4887
4888struct wmi_pdev_radar_ev {
4889	uint32_t pdev_id;
4890	uint32_t detection_mode;
4891	uint32_t chan_freq;
4892	uint32_t chan_width;
4893	uint32_t detector_id;
4894	uint32_t segment_id;
4895	uint32_t timestamp;
4896	uint32_t is_chirp;
4897	int32_t freq_offset;
4898	int32_t sidx;
4899} __packed;
4900
4901struct wmi_pdev_temperature_event {
4902	/* temperature value in Celsius degree */
4903	int32_t temp;
4904	uint32_t pdev_id;
4905} __packed;
4906
4907#define WMI_RX_STATUS_OK			0x00
4908#define WMI_RX_STATUS_ERR_CRC			0x01
4909#define WMI_RX_STATUS_ERR_DECRYPT		0x08
4910#define WMI_RX_STATUS_ERR_MIC			0x10
4911#define WMI_RX_STATUS_ERR_KEY_CACHE_MISS	0x20
4912
4913#define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4
4914
4915struct mgmt_rx_event_params {
4916	uint32_t chan_freq;
4917	uint32_t channel;
4918	uint32_t snr;
4919	uint8_t rssi_ctl[WLAN_MGMT_TXRX_HOST_MAX_ANTENNA];
4920	uint32_t rate;
4921	enum wmi_phy_mode phy_mode;
4922	uint32_t buf_len;
4923	int status;
4924	uint32_t flags;
4925	int rssi;
4926	uint32_t tsf_delta;
4927	uint8_t pdev_id;
4928};
4929
4930#define ATH_MAX_ANTENNA 4
4931
4932struct wmi_mgmt_rx_hdr {
4933	uint32_t channel;
4934	uint32_t snr;
4935	uint32_t rate;
4936	uint32_t phy_mode;
4937	uint32_t buf_len;
4938	uint32_t status;
4939	uint32_t rssi_ctl[ATH_MAX_ANTENNA];
4940	uint32_t flags;
4941	int rssi;
4942	uint32_t tsf_delta;
4943	uint32_t rx_tsf_l32;
4944	uint32_t rx_tsf_u32;
4945	uint32_t pdev_id;
4946	uint32_t chan_freq;
4947} __packed;
4948
4949#define MAX_ANTENNA_EIGHT 8
4950
4951struct wmi_rssi_ctl_ext {
4952	uint32_t tlv_header;
4953	uint32_t rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA];
4954};
4955
4956struct wmi_mgmt_tx_compl_event {
4957	uint32_t desc_id;
4958	uint32_t status;
4959	uint32_t pdev_id;
4960	uint32_t ppdu_id;
4961	uint32_t ack_rssi;
4962} __packed;
4963
4964struct wmi_scan_event {
4965	uint32_t event_type; /* %WMI_SCAN_EVENT_ */
4966	uint32_t reason; /* %WMI_SCAN_REASON_ */
4967	uint32_t channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */
4968	uint32_t scan_req_id;
4969	uint32_t scan_id;
4970	uint32_t vdev_id;
4971	/* TSF Timestamp when the scan event (%WMI_SCAN_EVENT_) is completed
4972	 * In case of AP it is TSF of the AP vdev
4973	 * In case of STA connected state, this is the TSF of the AP
4974	 * In case of STA not connected, it will be the free running HW timer
4975	 */
4976	uint32_t tsf_timestamp;
4977} __packed;
4978
4979struct wmi_peer_sta_kickout_arg {
4980	const uint8_t *mac_addr;
4981};
4982
4983struct wmi_peer_sta_kickout_event {
4984	struct wmi_mac_addr peer_macaddr;
4985} __packed;
4986
4987enum wmi_roam_reason {
4988	WMI_ROAM_REASON_BETTER_AP = 1,
4989	WMI_ROAM_REASON_BEACON_MISS = 2,
4990	WMI_ROAM_REASON_LOW_RSSI = 3,
4991	WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4,
4992	WMI_ROAM_REASON_HO_FAILED = 5,
4993
4994	/* keep last */
4995	WMI_ROAM_REASON_MAX,
4996};
4997
4998struct wmi_roam_event {
4999	uint32_t vdev_id;
5000	uint32_t reason;
5001	uint32_t rssi;
5002} __packed;
5003
5004#define WMI_CHAN_INFO_START_RESP 0
5005#define WMI_CHAN_INFO_END_RESP 1
5006
5007struct wmi_chan_info_event {
5008	uint32_t err_code;
5009	uint32_t freq;
5010	uint32_t cmd_flags;
5011	uint32_t noise_floor;
5012	uint32_t rx_clear_count;
5013	uint32_t cycle_count;
5014	uint32_t chan_tx_pwr_range;
5015	uint32_t chan_tx_pwr_tp;
5016	uint32_t rx_frame_count;
5017	uint32_t my_bss_rx_cycle_count;
5018	uint32_t rx_11b_mode_data_duration;
5019	uint32_t tx_frame_cnt;
5020	uint32_t mac_clk_mhz;
5021	uint32_t vdev_id;
5022} __packed;
5023
5024struct ath12k_targ_cap {
5025	uint32_t phy_capability;
5026	uint32_t max_frag_entry;
5027	uint32_t num_rf_chains;
5028	uint32_t ht_cap_info;
5029	uint32_t vht_cap_info;
5030	uint32_t vht_supp_mcs;
5031	uint32_t hw_min_tx_power;
5032	uint32_t hw_max_tx_power;
5033	uint32_t sys_cap_info;
5034	uint32_t min_pkt_size_enable;
5035	uint32_t max_bcn_ie_size;
5036	uint32_t max_num_scan_channels;
5037	uint32_t max_supported_macs;
5038	uint32_t wmi_fw_sub_feat_caps;
5039	uint32_t txrx_chainmask;
5040	uint32_t default_dbs_hw_mode_index;
5041	uint32_t num_msdu_desc;
5042};
5043
5044enum wmi_vdev_type {
5045	WMI_VDEV_TYPE_AP      = 1,
5046	WMI_VDEV_TYPE_STA     = 2,
5047	WMI_VDEV_TYPE_IBSS    = 3,
5048	WMI_VDEV_TYPE_MONITOR = 4,
5049};
5050
5051enum wmi_vdev_subtype {
5052	WMI_VDEV_SUBTYPE_NONE,
5053	WMI_VDEV_SUBTYPE_P2P_DEVICE,
5054	WMI_VDEV_SUBTYPE_P2P_CLIENT,
5055	WMI_VDEV_SUBTYPE_P2P_GO,
5056	WMI_VDEV_SUBTYPE_PROXY_STA,
5057	WMI_VDEV_SUBTYPE_MESH_NON_11S,
5058	WMI_VDEV_SUBTYPE_MESH_11S,
5059};
5060
5061enum wmi_sta_powersave_param {
5062	WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0,
5063	WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1,
5064	WMI_STA_PS_PARAM_PSPOLL_COUNT = 2,
5065	WMI_STA_PS_PARAM_INACTIVITY_TIME = 3,
5066	WMI_STA_PS_PARAM_UAPSD = 4,
5067};
5068
5069#define WMI_UAPSD_AC_TYPE_DELI 0
5070#define WMI_UAPSD_AC_TYPE_TRIG 1
5071
5072#define WMI_UAPSD_AC_BIT_MASK(ac, type) \
5073	((type ==  WMI_UAPSD_AC_TYPE_DELI) ? \
5074	 (1 << (ac << 1)) : (1 << ((ac << 1) + 1)))
5075
5076enum wmi_sta_ps_param_uapsd {
5077	WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
5078	WMI_STA_PS_UAPSD_AC0_TRIGGER_EN  = (1 << 1),
5079	WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
5080	WMI_STA_PS_UAPSD_AC1_TRIGGER_EN  = (1 << 3),
5081	WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
5082	WMI_STA_PS_UAPSD_AC2_TRIGGER_EN  = (1 << 5),
5083	WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
5084	WMI_STA_PS_UAPSD_AC3_TRIGGER_EN  = (1 << 7),
5085};
5086
5087#define WMI_STA_UAPSD_MAX_INTERVAL_MSEC UINT_MAX
5088
5089struct wmi_sta_uapsd_auto_trig_param {
5090	uint32_t wmm_ac;
5091	uint32_t user_priority;
5092	uint32_t service_interval;
5093	uint32_t suspend_interval;
5094	uint32_t delay_interval;
5095};
5096
5097struct wmi_sta_uapsd_auto_trig_cmd_fixed_param {
5098	uint32_t vdev_id;
5099	struct wmi_mac_addr peer_macaddr;
5100	uint32_t num_ac;
5101};
5102
5103struct wmi_sta_uapsd_auto_trig_arg {
5104	uint32_t wmm_ac;
5105	uint32_t user_priority;
5106	uint32_t service_interval;
5107	uint32_t suspend_interval;
5108	uint32_t delay_interval;
5109};
5110
5111enum wmi_sta_ps_param_tx_wake_threshold {
5112	WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0,
5113	WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1,
5114
5115	/* Values greater than one indicate that many TX attempts per beacon
5116	 * interval before the STA will wake up
5117	 */
5118};
5119
5120/* The maximum number of PS-Poll frames the FW will send in response to
5121 * traffic advertised in TIM before waking up (by sending a null frame with PS
5122 * = 0). Value 0 has a special meaning: there is no maximum count and the FW
5123 * will send as many PS-Poll as are necessary to retrieve buffered BU. This
5124 * parameter is used when the RX wake policy is
5125 * WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD and ignored when the RX wake
5126 * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE.
5127 */
5128enum wmi_sta_ps_param_pspoll_count {
5129	WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0,
5130	/* Values greater than 0 indicate the maximum number of PS-Poll frames
5131	 * FW will send before waking up.
5132	 */
5133};
5134
5135/* U-APSD configuration of peer station from (re)assoc request and TSPECs */
5136enum wmi_ap_ps_param_uapsd {
5137	WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0),
5138	WMI_AP_PS_UAPSD_AC0_TRIGGER_EN  = (1 << 1),
5139	WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2),
5140	WMI_AP_PS_UAPSD_AC1_TRIGGER_EN  = (1 << 3),
5141	WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4),
5142	WMI_AP_PS_UAPSD_AC2_TRIGGER_EN  = (1 << 5),
5143	WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6),
5144	WMI_AP_PS_UAPSD_AC3_TRIGGER_EN  = (1 << 7),
5145};
5146
5147/* U-APSD maximum service period of peer station */
5148enum wmi_ap_ps_peer_param_max_sp {
5149	WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0,
5150	WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1,
5151	WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2,
5152	WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3,
5153	MAX_WMI_AP_PS_PEER_PARAM_MAX_SP,
5154};
5155
5156enum wmi_ap_ps_peer_param {
5157	/** Set uapsd configuration for a given peer.
5158	 *
5159	 * This include the delivery and trigger enabled state for each AC.
5160	 * The host MLME needs to set this based on AP capability and stations
5161	 * request Set in the association request  received from the station.
5162	 *
5163	 * Lower 8 bits of the value specify the UAPSD configuration.
5164	 *
5165	 * (see enum wmi_ap_ps_param_uapsd)
5166	 * The default value is 0.
5167	 */
5168	WMI_AP_PS_PEER_PARAM_UAPSD = 0,
5169
5170	/**
5171	 * Set the service period for a UAPSD capable station
5172	 *
5173	 * The service period from wme ie in the (re)assoc request frame.
5174	 *
5175	 * (see enum wmi_ap_ps_peer_param_max_sp)
5176	 */
5177	WMI_AP_PS_PEER_PARAM_MAX_SP = 1,
5178
5179	/** Time in seconds for aging out buffered frames
5180	 * for STA in power save
5181	 */
5182	WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2,
5183
5184	/** Specify frame types that are considered SIFS
5185	 * RESP trigger frame
5186	 */
5187	WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3,
5188
5189	/** Specifies the trigger state of TID.
5190	 * Valid only for UAPSD frame type
5191	 */
5192	WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4,
5193
5194	/* Specifies the WNM sleep state of a STA */
5195	WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5,
5196};
5197
5198#define DISABLE_SIFS_RESPONSE_TRIGGER 0
5199
5200#define WMI_MAX_KEY_INDEX   3
5201#define WMI_MAX_KEY_LEN     32
5202
5203#define WMI_KEY_PAIRWISE 0x00
5204#define WMI_KEY_GROUP    0x01
5205
5206#define WMI_CIPHER_NONE     0x0 /* clear key */
5207#define WMI_CIPHER_WEP      0x1
5208#define WMI_CIPHER_TKIP     0x2
5209#define WMI_CIPHER_AES_OCB  0x3
5210#define WMI_CIPHER_AES_CCM  0x4
5211#define WMI_CIPHER_WAPI     0x5
5212#define WMI_CIPHER_CKIP     0x6
5213#define WMI_CIPHER_AES_CMAC 0x7
5214#define WMI_CIPHER_ANY      0x8
5215#define WMI_CIPHER_AES_GCM  0x9
5216#define WMI_CIPHER_AES_GMAC 0xa
5217
5218/* Value to disable fixed rate setting */
5219#define WMI_FIXED_RATE_NONE	(0xffff)
5220
5221#define ATH12K_RC_VERSION_OFFSET	28
5222#define ATH12K_RC_PREAMBLE_OFFSET	8
5223#define ATH12K_RC_NSS_OFFSET		5
5224
5225#define ATH12K_HW_RATE_CODE(rate, nss, preamble)	\
5226	((1 << ATH12K_RC_VERSION_OFFSET) |		\
5227	 ((nss) << ATH12K_RC_NSS_OFFSET) |		\
5228	 ((preamble) << ATH12K_RC_PREAMBLE_OFFSET) |	\
5229	 (rate))
5230
5231/* Preamble types to be used with VDEV fixed rate configuration */
5232enum wmi_rate_preamble {
5233	WMI_RATE_PREAMBLE_OFDM,
5234	WMI_RATE_PREAMBLE_CCK,
5235	WMI_RATE_PREAMBLE_HT,
5236	WMI_RATE_PREAMBLE_VHT,
5237	WMI_RATE_PREAMBLE_HE,
5238};
5239
5240/**
5241 * enum wmi_rtscts_prot_mode - Enable/Disable RTS/CTS and CTS2Self Protection.
5242 * @WMI_RTS_CTS_DISABLED: RTS/CTS protection is disabled.
5243 * @WMI_USE_RTS_CTS: RTS/CTS Enabled.
5244 * @WMI_USE_CTS2SELF: CTS to self protection Enabled.
5245 */
5246enum wmi_rtscts_prot_mode {
5247	WMI_RTS_CTS_DISABLED = 0,
5248	WMI_USE_RTS_CTS = 1,
5249	WMI_USE_CTS2SELF = 2,
5250};
5251
5252/**
5253 * enum wmi_rtscts_profile - Selection of RTS CTS profile along with enabling
5254 *                           protection mode.
5255 * @WMI_RTSCTS_FOR_NO_RATESERIES: Neither of rate-series should use RTS-CTS
5256 * @WMI_RTSCTS_FOR_SECOND_RATESERIES: Only second rate-series will use RTS-CTS
5257 * @WMI_RTSCTS_ACROSS_SW_RETRIES: Only the second rate-series will use RTS-CTS,
5258 *                                but if there's a sw retry, both the rate
5259 *                                series will use RTS-CTS.
5260 * @WMI_RTSCTS_ERP: RTS/CTS used for ERP protection for every PPDU.
5261 * @WMI_RTSCTS_FOR_ALL_RATESERIES: Enable RTS-CTS for all rate series.
5262 */
5263enum wmi_rtscts_profile {
5264	WMI_RTSCTS_FOR_NO_RATESERIES = 0,
5265	WMI_RTSCTS_FOR_SECOND_RATESERIES = 1,
5266	WMI_RTSCTS_ACROSS_SW_RETRIES = 2,
5267	WMI_RTSCTS_ERP = 3,
5268	WMI_RTSCTS_FOR_ALL_RATESERIES = 4,
5269};
5270
5271struct ath12k_hal_reg_cap {
5272	uint32_t eeprom_rd;
5273	uint32_t eeprom_rd_ext;
5274	uint32_t regcap1;
5275	uint32_t regcap2;
5276	uint32_t wireless_modes;
5277	uint32_t low_2ghz_chan;
5278	uint32_t high_2ghz_chan;
5279	uint32_t low_5ghz_chan;
5280	uint32_t high_5ghz_chan;
5281};
5282
5283struct ath12k_mem_chunk {
5284	void *vaddr;
5285	bus_addr_t paddr;
5286	uint32_t len;
5287	uint32_t req_id;
5288};
5289
5290enum wmi_sta_ps_param_rx_wake_policy {
5291	WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0,
5292	WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1,
5293};
5294
5295/* Do not change existing values! Used by ath12k_frame_mode parameter
5296 * module parameter.
5297 */
5298enum ath12k_hw_txrx_mode {
5299	ATH12K_HW_TXRX_RAW = 0,
5300	ATH12K_HW_TXRX_NATIVE_WIFI = 1,
5301	ATH12K_HW_TXRX_ETHERNET = 2,
5302};
5303
5304struct wmi_wmm_params {
5305	uint32_t tlv_header;
5306	uint32_t cwmin;
5307	uint32_t cwmax;
5308	uint32_t aifs;
5309	uint32_t txoplimit;
5310	uint32_t acm;
5311	uint32_t no_ack;
5312} __packed;
5313
5314struct wmi_wmm_params_arg {
5315	uint8_t acm;
5316	uint8_t aifs;
5317	uint16_t cwmin;
5318	uint16_t cwmax;
5319	uint16_t txop;
5320	uint8_t no_ack;
5321};
5322
5323struct wmi_vdev_set_wmm_params_cmd {
5324	uint32_t tlv_header;
5325	uint32_t vdev_id;
5326	struct wmi_wmm_params wmm_params[4];
5327	uint32_t wmm_param_type;
5328} __packed;
5329
5330struct wmi_wmm_params_all_arg {
5331	struct wmi_wmm_params_arg ac_be;
5332	struct wmi_wmm_params_arg ac_bk;
5333	struct wmi_wmm_params_arg ac_vi;
5334	struct wmi_wmm_params_arg ac_vo;
5335};
5336
5337#define ATH12K_TWT_DEF_STA_CONG_TIMER_MS		5000
5338#define ATH12K_TWT_DEF_DEFAULT_SLOT_SIZE		10
5339#define ATH12K_TWT_DEF_CONGESTION_THRESH_SETUP		50
5340#define ATH12K_TWT_DEF_CONGESTION_THRESH_TEARDOWN	20
5341#define ATH12K_TWT_DEF_CONGESTION_THRESH_CRITICAL	100
5342#define ATH12K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN	80
5343#define ATH12K_TWT_DEF_INTERFERENCE_THRESH_SETUP	50
5344#define ATH12K_TWT_DEF_MIN_NO_STA_SETUP			10
5345#define ATH12K_TWT_DEF_MIN_NO_STA_TEARDOWN		2
5346#define ATH12K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS		2
5347#define ATH12K_TWT_DEF_MIN_NO_TWT_SLOTS			2
5348#define ATH12K_TWT_DEF_MAX_NO_STA_TWT			500
5349#define ATH12K_TWT_DEF_MODE_CHECK_INTERVAL		10000
5350#define ATH12K_TWT_DEF_ADD_STA_SLOT_INTERVAL		1000
5351#define ATH12K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL		5000
5352
5353struct wmi_twt_enable_params {
5354	uint32_t sta_cong_timer_ms;
5355	uint32_t mbss_support;
5356	uint32_t default_slot_size;
5357	uint32_t congestion_thresh_setup;
5358	uint32_t congestion_thresh_teardown;
5359	uint32_t congestion_thresh_critical;
5360	uint32_t interference_thresh_teardown;
5361	uint32_t interference_thresh_setup;
5362	uint32_t min_no_sta_setup;
5363	uint32_t min_no_sta_teardown;
5364	uint32_t no_of_bcast_mcast_slots;
5365	uint32_t min_no_twt_slots;
5366	uint32_t max_no_sta_twt;
5367	uint32_t mode_check_interval;
5368	uint32_t add_sta_slot_interval;
5369	uint32_t remove_sta_slot_interval;
5370};
5371
5372struct wmi_twt_enable_params_cmd {
5373	uint32_t tlv_header;
5374	uint32_t pdev_id;
5375	uint32_t sta_cong_timer_ms;
5376	uint32_t mbss_support;
5377	uint32_t default_slot_size;
5378	uint32_t congestion_thresh_setup;
5379	uint32_t congestion_thresh_teardown;
5380	uint32_t congestion_thresh_critical;
5381	uint32_t interference_thresh_teardown;
5382	uint32_t interference_thresh_setup;
5383	uint32_t min_no_sta_setup;
5384	uint32_t min_no_sta_teardown;
5385	uint32_t no_of_bcast_mcast_slots;
5386	uint32_t min_no_twt_slots;
5387	uint32_t max_no_sta_twt;
5388	uint32_t mode_check_interval;
5389	uint32_t add_sta_slot_interval;
5390	uint32_t remove_sta_slot_interval;
5391} __packed;
5392
5393struct wmi_twt_disable_params_cmd {
5394	uint32_t tlv_header;
5395	uint32_t pdev_id;
5396} __packed;
5397
5398enum WMI_HOST_TWT_COMMAND {
5399	WMI_HOST_TWT_COMMAND_REQUEST_TWT = 0,
5400	WMI_HOST_TWT_COMMAND_SUGGEST_TWT,
5401	WMI_HOST_TWT_COMMAND_DEMAND_TWT,
5402	WMI_HOST_TWT_COMMAND_TWT_GROUPING,
5403	WMI_HOST_TWT_COMMAND_ACCEPT_TWT,
5404	WMI_HOST_TWT_COMMAND_ALTERNATE_TWT,
5405	WMI_HOST_TWT_COMMAND_DICTATE_TWT,
5406	WMI_HOST_TWT_COMMAND_REJECT_TWT,
5407};
5408
5409#define WMI_TWT_ADD_DIALOG_FLAG_BCAST           BIT(8)
5410#define WMI_TWT_ADD_DIALOG_FLAG_TRIGGER         BIT(9)
5411#define WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE       BIT(10)
5412#define WMI_TWT_ADD_DIALOG_FLAG_PROTECTION      BIT(11)
5413
5414struct wmi_twt_add_dialog_params_cmd {
5415	uint32_t tlv_header;
5416	uint32_t vdev_id;
5417	struct wmi_mac_addr peer_macaddr;
5418	uint32_t dialog_id;
5419	uint32_t wake_intvl_us;
5420	uint32_t wake_intvl_mantis;
5421	uint32_t wake_dura_us;
5422	uint32_t sp_offset_us;
5423	uint32_t flags;
5424} __packed;
5425
5426struct wmi_twt_add_dialog_params {
5427	uint32_t vdev_id;
5428	uint8_t peer_macaddr[IEEE80211_ADDR_LEN];
5429	uint32_t dialog_id;
5430	uint32_t wake_intvl_us;
5431	uint32_t wake_intvl_mantis;
5432	uint32_t wake_dura_us;
5433	uint32_t sp_offset_us;
5434	uint8_t twt_cmd;
5435	uint8_t flag_bcast;
5436	uint8_t flag_trigger;
5437	uint8_t flag_flow_type;
5438	uint8_t flag_protection;
5439} __packed;
5440
5441enum  wmi_twt_add_dialog_status {
5442	WMI_ADD_TWT_STATUS_OK,
5443	WMI_ADD_TWT_STATUS_TWT_NOT_ENABLED,
5444	WMI_ADD_TWT_STATUS_USED_DIALOG_ID,
5445	WMI_ADD_TWT_STATUS_INVALID_PARAM,
5446	WMI_ADD_TWT_STATUS_NOT_READY,
5447	WMI_ADD_TWT_STATUS_NO_RESOURCE,
5448	WMI_ADD_TWT_STATUS_NO_ACK,
5449	WMI_ADD_TWT_STATUS_NO_RESPONSE,
5450	WMI_ADD_TWT_STATUS_DENIED,
5451	WMI_ADD_TWT_STATUS_UNKNOWN_ERROR,
5452};
5453
5454struct wmi_twt_add_dialog_event {
5455	uint32_t vdev_id;
5456	struct wmi_mac_addr peer_macaddr;
5457	uint32_t dialog_id;
5458	uint32_t status;
5459} __packed;
5460
5461struct wmi_twt_del_dialog_params {
5462	uint32_t vdev_id;
5463	uint8_t peer_macaddr[IEEE80211_ADDR_LEN];
5464	uint32_t dialog_id;
5465} __packed;
5466
5467struct wmi_twt_del_dialog_params_cmd {
5468	uint32_t tlv_header;
5469	uint32_t vdev_id;
5470	struct wmi_mac_addr peer_macaddr;
5471	uint32_t dialog_id;
5472} __packed;
5473
5474struct wmi_twt_pause_dialog_params {
5475	uint32_t vdev_id;
5476	uint8_t peer_macaddr[IEEE80211_ADDR_LEN];
5477	uint32_t dialog_id;
5478} __packed;
5479
5480struct wmi_twt_pause_dialog_params_cmd {
5481	uint32_t tlv_header;
5482	uint32_t vdev_id;
5483	struct wmi_mac_addr peer_macaddr;
5484	uint32_t dialog_id;
5485} __packed;
5486
5487struct wmi_twt_resume_dialog_params {
5488	uint32_t vdev_id;
5489	uint8_t peer_macaddr[IEEE80211_ADDR_LEN];
5490	uint32_t dialog_id;
5491	uint32_t sp_offset_us;
5492	uint32_t next_twt_size;
5493} __packed;
5494
5495struct wmi_twt_resume_dialog_params_cmd {
5496	uint32_t tlv_header;
5497	uint32_t vdev_id;
5498	struct wmi_mac_addr peer_macaddr;
5499	uint32_t dialog_id;
5500	uint32_t sp_offset_us;
5501	uint32_t next_twt_size;
5502} __packed;
5503
5504struct wmi_obss_spatial_reuse_params_cmd {
5505	uint32_t tlv_header;
5506	uint32_t pdev_id;
5507	uint32_t enable;
5508	int32_t obss_min;
5509	int32_t obss_max;
5510	uint32_t vdev_id;
5511} __packed;
5512
5513struct wmi_pdev_obss_pd_bitmap_cmd {
5514	uint32_t tlv_header;
5515	uint32_t pdev_id;
5516	uint32_t bitmap[2];
5517} __packed;
5518
5519#define ATH12K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS		200
5520#define ATH12K_OBSS_COLOR_COLLISION_DETECTION_DISABLE		0
5521#define ATH12K_OBSS_COLOR_COLLISION_DETECTION			1
5522
5523#define ATH12K_BSS_COLOR_COLLISION_DETECTION_STA_PERIOD_MS	10000
5524#define ATH12K_BSS_COLOR_COLLISION_DETECTION_AP_PERIOD_MS	5000
5525
5526enum wmi_bss_color_collision {
5527	WMI_BSS_COLOR_COLLISION_DISABLE = 0,
5528	WMI_BSS_COLOR_COLLISION_DETECTION,
5529	WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY,
5530	WMI_BSS_COLOR_FREE_SLOT_AVAILABLE,
5531};
5532
5533struct wmi_obss_color_collision_cfg_params_cmd {
5534	uint32_t tlv_header;
5535	uint32_t vdev_id;
5536	uint32_t flags;
5537	uint32_t evt_type;
5538	uint32_t current_bss_color;
5539	uint32_t detection_period_ms;
5540	uint32_t scan_period_ms;
5541	uint32_t free_slot_expiry_time_ms;
5542} __packed;
5543
5544struct wmi_bss_color_change_enable_params_cmd {
5545	uint32_t tlv_header;
5546	uint32_t vdev_id;
5547	uint32_t enable;
5548} __packed;
5549
5550struct wmi_obss_color_collision_event {
5551	uint32_t vdev_id;
5552	uint32_t evt_type;
5553	uint64_t obss_color_bitmap;
5554} __packed;
5555
5556#define ATH12K_IPV4_TH_SEED_SIZE 5
5557#define ATH12K_IPV6_TH_SEED_SIZE 11
5558
5559struct ath12k_wmi_pdev_lro_config_cmd {
5560	uint32_t tlv_header;
5561	uint32_t lro_enable;
5562	uint32_t res;
5563	uint32_t th_4[ATH12K_IPV4_TH_SEED_SIZE];
5564	uint32_t th_6[ATH12K_IPV6_TH_SEED_SIZE];
5565	uint32_t pdev_id;
5566} __packed;
5567
5568#define ATH12K_WMI_SPECTRAL_COUNT_DEFAULT                 0
5569#define ATH12K_WMI_SPECTRAL_PERIOD_DEFAULT              224
5570#define ATH12K_WMI_SPECTRAL_PRIORITY_DEFAULT              1
5571#define ATH12K_WMI_SPECTRAL_FFT_SIZE_DEFAULT              7
5572#define ATH12K_WMI_SPECTRAL_GC_ENA_DEFAULT                1
5573#define ATH12K_WMI_SPECTRAL_RESTART_ENA_DEFAULT           0
5574#define ATH12K_WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT     -96
5575#define ATH12K_WMI_SPECTRAL_INIT_DELAY_DEFAULT           80
5576#define ATH12K_WMI_SPECTRAL_NB_TONE_THR_DEFAULT          12
5577#define ATH12K_WMI_SPECTRAL_STR_BIN_THR_DEFAULT           8
5578#define ATH12K_WMI_SPECTRAL_WB_RPT_MODE_DEFAULT           0
5579#define ATH12K_WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT         0
5580#define ATH12K_WMI_SPECTRAL_RSSI_THR_DEFAULT           0xf0
5581#define ATH12K_WMI_SPECTRAL_PWR_FORMAT_DEFAULT            0
5582#define ATH12K_WMI_SPECTRAL_RPT_MODE_DEFAULT              2
5583#define ATH12K_WMI_SPECTRAL_BIN_SCALE_DEFAULT             1
5584#define ATH12K_WMI_SPECTRAL_DBM_ADJ_DEFAULT               1
5585#define ATH12K_WMI_SPECTRAL_CHN_MASK_DEFAULT              1
5586
5587struct ath12k_wmi_vdev_spectral_conf_param {
5588	uint32_t vdev_id;
5589	uint32_t scan_count;
5590	uint32_t scan_period;
5591	uint32_t scan_priority;
5592	uint32_t scan_fft_size;
5593	uint32_t scan_gc_ena;
5594	uint32_t scan_restart_ena;
5595	uint32_t scan_noise_floor_ref;
5596	uint32_t scan_init_delay;
5597	uint32_t scan_nb_tone_thr;
5598	uint32_t scan_str_bin_thr;
5599	uint32_t scan_wb_rpt_mode;
5600	uint32_t scan_rssi_rpt_mode;
5601	uint32_t scan_rssi_thr;
5602	uint32_t scan_pwr_format;
5603	uint32_t scan_rpt_mode;
5604	uint32_t scan_bin_scale;
5605	uint32_t scan_dbm_adj;
5606	uint32_t scan_chn_mask;
5607} __packed;
5608
5609struct ath12k_wmi_vdev_spectral_conf_cmd {
5610	uint32_t tlv_header;
5611	struct ath12k_wmi_vdev_spectral_conf_param param;
5612} __packed;
5613
5614#define ATH12K_WMI_SPECTRAL_TRIGGER_CMD_TRIGGER  1
5615#define ATH12K_WMI_SPECTRAL_TRIGGER_CMD_CLEAR    2
5616#define ATH12K_WMI_SPECTRAL_ENABLE_CMD_ENABLE    1
5617#define ATH12K_WMI_SPECTRAL_ENABLE_CMD_DISABLE   2
5618
5619struct ath12k_wmi_vdev_spectral_enable_cmd {
5620	uint32_t tlv_header;
5621	uint32_t vdev_id;
5622	uint32_t trigger_cmd;
5623	uint32_t enable_cmd;
5624} __packed;
5625
5626struct ath12k_wmi_pdev_dma_ring_cfg_req_cmd {
5627	uint32_t tlv_header;
5628	uint32_t pdev_id;
5629	uint32_t module_id;		/* see enum wmi_direct_buffer_module */
5630	uint32_t base_paddr_lo;
5631	uint32_t base_paddr_hi;
5632	uint32_t head_idx_paddr_lo;
5633	uint32_t head_idx_paddr_hi;
5634	uint32_t tail_idx_paddr_lo;
5635	uint32_t tail_idx_paddr_hi;
5636	uint32_t num_elems;		/* Number of elems in the ring */
5637	uint32_t buf_size;		/* size of allocated buffer in bytes */
5638
5639	/* Number of wmi_dma_buf_release_entry packed together */
5640	uint32_t num_resp_per_event;
5641
5642	/* Target should timeout and send whatever resp
5643	 * it has if this time expires, units in milliseconds
5644	 */
5645	uint32_t event_timeout_ms;
5646} __packed;
5647
5648struct ath12k_wmi_dma_buf_release_fixed_param {
5649	uint32_t pdev_id;
5650	uint32_t module_id;
5651	uint32_t num_buf_release_entry;
5652	uint32_t num_meta_data_entry;
5653} __packed;
5654
5655struct wmi_dma_buf_release_entry {
5656	uint32_t tlv_header;
5657	uint32_t paddr_lo;
5658
5659	/* Bits 11:0:   address of data
5660	 * Bits 31:12:  host context data
5661	 */
5662	uint32_t paddr_hi;
5663} __packed;
5664
5665#define WMI_SPECTRAL_META_INFO1_FREQ1		GENMASK(15, 0)
5666#define WMI_SPECTRAL_META_INFO1_FREQ2		GENMASK(31, 16)
5667
5668#define WMI_SPECTRAL_META_INFO2_CHN_WIDTH	GENMASK(7, 0)
5669
5670struct wmi_dma_buf_release_meta_data {
5671	uint32_t tlv_header;
5672	int32_t noise_floor[WMI_MAX_CHAINS];
5673	uint32_t reset_delay;
5674	uint32_t freq1;
5675	uint32_t freq2;
5676	uint32_t ch_width;
5677} __packed;
5678
5679enum wmi_fils_discovery_cmd_type {
5680	WMI_FILS_DISCOVERY_CMD,
5681	WMI_UNSOL_BCAST_PROBE_RESP,
5682};
5683
5684struct wmi_fils_discovery_cmd {
5685	uint32_t tlv_header;
5686	uint32_t vdev_id;
5687	uint32_t interval;
5688	uint32_t config; /* enum wmi_fils_discovery_cmd_type */
5689} __packed;
5690
5691struct wmi_fils_discovery_tmpl_cmd {
5692	uint32_t tlv_header;
5693	uint32_t vdev_id;
5694	uint32_t buf_len;
5695} __packed;
5696
5697struct wmi_probe_tmpl_cmd {
5698	uint32_t tlv_header;
5699	uint32_t vdev_id;
5700	uint32_t buf_len;
5701} __packed;
5702
5703struct target_resource_config {
5704	uint32_t num_vdevs;
5705	uint32_t num_peers;
5706	uint32_t num_active_peers;
5707	uint32_t num_offload_peers;
5708	uint32_t num_offload_reorder_buffs;
5709	uint32_t num_peer_keys;
5710	uint32_t num_tids;
5711	uint32_t ast_skid_limit;
5712	uint32_t tx_chain_mask;
5713	uint32_t rx_chain_mask;
5714	uint32_t rx_timeout_pri[4];
5715	uint32_t rx_decap_mode;
5716	uint32_t scan_max_pending_req;
5717	uint32_t bmiss_offload_max_vdev;
5718	uint32_t roam_offload_max_vdev;
5719	uint32_t roam_offload_max_ap_profiles;
5720	uint32_t num_mcast_groups;
5721	uint32_t num_mcast_table_elems;
5722	uint32_t mcast2ucast_mode;
5723	uint32_t tx_dbg_log_size;
5724	uint32_t num_wds_entries;
5725	uint32_t dma_burst_size;
5726	uint32_t mac_aggr_delim;
5727	uint32_t rx_skip_defrag_timeout_dup_detection_check;
5728	uint32_t vow_config;
5729	uint32_t gtk_offload_max_vdev;
5730	uint32_t num_msdu_desc;
5731	uint32_t max_frag_entries;
5732	uint32_t max_peer_ext_stats;
5733	uint32_t smart_ant_cap;
5734	uint32_t bk_minfree;
5735	uint32_t be_minfree;
5736	uint32_t vi_minfree;
5737	uint32_t vo_minfree;
5738	uint32_t rx_batchmode;
5739	uint32_t tt_support;
5740	uint32_t flag1;
5741	uint32_t iphdr_pad_config;
5742	uint32_t qwrap_config:16,
5743	    alloc_frag_desc_for_data_pkt:16;
5744	uint32_t num_tdls_vdevs;
5745	uint32_t num_tdls_conn_table_entries;
5746	uint32_t beacon_tx_offload_max_vdev;
5747	uint32_t num_multicast_filter_entries;
5748	uint32_t num_wow_filters;
5749	uint32_t num_keep_alive_pattern;
5750	uint32_t keep_alive_pattern_size;
5751	uint32_t max_tdls_concurrent_sleep_sta;
5752	uint32_t max_tdls_concurrent_buffer_sta;
5753	uint32_t wmi_send_separate;
5754	uint32_t num_ocb_vdevs;
5755	uint32_t num_ocb_channels;
5756	uint32_t num_ocb_schedules;
5757	uint32_t num_ns_ext_tuples_cfg;
5758	uint32_t bpf_instruction_size;
5759	uint32_t max_bssid_rx_filters;
5760	uint32_t use_pdev_id;
5761	uint32_t peer_map_unmap_v2_support;
5762	uint32_t sched_params;
5763	uint32_t twt_ap_pdev_count;
5764	uint32_t twt_ap_sta_count;
5765	uint8_t is_reg_cc_ext_event_supported;
5766	uint32_t ema_max_vap_cnt;
5767	uint32_t ema_max_profile_period;
5768};
5769
5770enum wmi_debug_log_param {
5771	WMI_DEBUG_LOG_PARAM_LOG_LEVEL = 0x1,
5772	WMI_DEBUG_LOG_PARAM_VDEV_ENABLE,
5773	WMI_DEBUG_LOG_PARAM_VDEV_DISABLE,
5774	WMI_DEBUG_LOG_PARAM_VDEV_ENABLE_BITMAP,
5775	WMI_DEBUG_LOG_PARAM_MOD_ENABLE_BITMAP,
5776	WMI_DEBUG_LOG_PARAM_WOW_MOD_ENABLE_BITMAP,
5777};
5778
5779struct wmi_debug_log_config_cmd_fixed_param {
5780	uint32_t tlv_header;
5781	uint32_t dbg_log_param;
5782	uint32_t value;
5783} __packed;
5784
5785#define WMI_MAX_MEM_REQS 32
5786
5787#define MAX_RADIOS 3
5788
5789#define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ)
5790#define WMI_SEND_TIMEOUT_HZ (3 * HZ)
5791
5792enum ath12k_wmi_peer_ps_state {
5793	WMI_PEER_PS_STATE_OFF,
5794	WMI_PEER_PS_STATE_ON,
5795	WMI_PEER_PS_STATE_DISABLED,
5796};
5797
5798enum wmi_peer_ps_supported_bitmap {
5799	/* Used to indicate that power save state change is valid */
5800	WMI_PEER_PS_VALID = 0x1,
5801	WMI_PEER_PS_STATE_TIMESTAMP = 0x2,
5802};
5803
5804struct wmi_peer_sta_ps_state_chg_event {
5805	struct wmi_mac_addr peer_macaddr;
5806	uint32_t peer_ps_state;
5807	uint32_t ps_supported_bitmap;
5808	uint32_t peer_ps_valid;
5809	uint32_t peer_ps_timestamp;
5810} __packed;
5811
5812/* Definition of HW data filtering */
5813enum hw_data_filter_type {
5814	WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0),
5815	WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1),
5816};
5817
5818struct wmi_hw_data_filter_cmd {
5819	uint32_t tlv_header;
5820	uint32_t vdev_id;
5821	uint32_t enable;
5822	uint32_t hw_filter_bitmap;
5823} __packed;
5824
5825/* WOW structures */
5826enum wmi_wow_wakeup_event {
5827	WOW_BMISS_EVENT = 0,
5828	WOW_BETTER_AP_EVENT,
5829	WOW_DEAUTH_RECVD_EVENT,
5830	WOW_MAGIC_PKT_RECVD_EVENT,
5831	WOW_GTK_ERR_EVENT,
5832	WOW_FOURWAY_HSHAKE_EVENT,
5833	WOW_EAPOL_RECVD_EVENT,
5834	WOW_NLO_DETECTED_EVENT,
5835	WOW_DISASSOC_RECVD_EVENT,
5836	WOW_PATTERN_MATCH_EVENT,
5837	WOW_CSA_IE_EVENT,
5838	WOW_PROBE_REQ_WPS_IE_EVENT,
5839	WOW_AUTH_REQ_EVENT,
5840	WOW_ASSOC_REQ_EVENT,
5841	WOW_HTT_EVENT,
5842	WOW_RA_MATCH_EVENT,
5843	WOW_HOST_AUTO_SHUTDOWN_EVENT,
5844	WOW_IOAC_MAGIC_EVENT,
5845	WOW_IOAC_SHORT_EVENT,
5846	WOW_IOAC_EXTEND_EVENT,
5847	WOW_IOAC_TIMER_EVENT,
5848	WOW_DFS_PHYERR_RADAR_EVENT,
5849	WOW_BEACON_EVENT,
5850	WOW_CLIENT_KICKOUT_EVENT,
5851	WOW_EVENT_MAX,
5852};
5853
5854enum wmi_wow_interface_cfg {
5855	WOW_IFACE_PAUSE_ENABLED,
5856	WOW_IFACE_PAUSE_DISABLED
5857};
5858
5859#define C2S(x) case x: return #x
5860
5861static inline const char *wow_wakeup_event(enum wmi_wow_wakeup_event ev)
5862{
5863	switch (ev) {
5864	C2S(WOW_BMISS_EVENT);
5865	C2S(WOW_BETTER_AP_EVENT);
5866	C2S(WOW_DEAUTH_RECVD_EVENT);
5867	C2S(WOW_MAGIC_PKT_RECVD_EVENT);
5868	C2S(WOW_GTK_ERR_EVENT);
5869	C2S(WOW_FOURWAY_HSHAKE_EVENT);
5870	C2S(WOW_EAPOL_RECVD_EVENT);
5871	C2S(WOW_NLO_DETECTED_EVENT);
5872	C2S(WOW_DISASSOC_RECVD_EVENT);
5873	C2S(WOW_PATTERN_MATCH_EVENT);
5874	C2S(WOW_CSA_IE_EVENT);
5875	C2S(WOW_PROBE_REQ_WPS_IE_EVENT);
5876	C2S(WOW_AUTH_REQ_EVENT);
5877	C2S(WOW_ASSOC_REQ_EVENT);
5878	C2S(WOW_HTT_EVENT);
5879	C2S(WOW_RA_MATCH_EVENT);
5880	C2S(WOW_HOST_AUTO_SHUTDOWN_EVENT);
5881	C2S(WOW_IOAC_MAGIC_EVENT);
5882	C2S(WOW_IOAC_SHORT_EVENT);
5883	C2S(WOW_IOAC_EXTEND_EVENT);
5884	C2S(WOW_IOAC_TIMER_EVENT);
5885	C2S(WOW_DFS_PHYERR_RADAR_EVENT);
5886	C2S(WOW_BEACON_EVENT);
5887	C2S(WOW_CLIENT_KICKOUT_EVENT);
5888	C2S(WOW_EVENT_MAX);
5889	default:
5890		return NULL;
5891	}
5892}
5893
5894enum wmi_wow_wake_reason {
5895	WOW_REASON_UNSPECIFIED = -1,
5896	WOW_REASON_NLOD = 0,
5897	WOW_REASON_AP_ASSOC_LOST,
5898	WOW_REASON_LOW_RSSI,
5899	WOW_REASON_DEAUTH_RECVD,
5900	WOW_REASON_DISASSOC_RECVD,
5901	WOW_REASON_GTK_HS_ERR,
5902	WOW_REASON_EAP_REQ,
5903	WOW_REASON_FOURWAY_HS_RECV,
5904	WOW_REASON_TIMER_INTR_RECV,
5905	WOW_REASON_PATTERN_MATCH_FOUND,
5906	WOW_REASON_RECV_MAGIC_PATTERN,
5907	WOW_REASON_P2P_DISC,
5908	WOW_REASON_WLAN_HB,
5909	WOW_REASON_CSA_EVENT,
5910	WOW_REASON_PROBE_REQ_WPS_IE_RECV,
5911	WOW_REASON_AUTH_REQ_RECV,
5912	WOW_REASON_ASSOC_REQ_RECV,
5913	WOW_REASON_HTT_EVENT,
5914	WOW_REASON_RA_MATCH,
5915	WOW_REASON_HOST_AUTO_SHUTDOWN,
5916	WOW_REASON_IOAC_MAGIC_EVENT,
5917	WOW_REASON_IOAC_SHORT_EVENT,
5918	WOW_REASON_IOAC_EXTEND_EVENT,
5919	WOW_REASON_IOAC_TIMER_EVENT,
5920	WOW_REASON_ROAM_HO,
5921	WOW_REASON_DFS_PHYERR_RADADR_EVENT,
5922	WOW_REASON_BEACON_RECV,
5923	WOW_REASON_CLIENT_KICKOUT_EVENT,
5924	WOW_REASON_PAGE_FAULT = 0x3a,
5925	WOW_REASON_DEBUG_TEST = 0xFF,
5926};
5927
5928static inline const char *wow_reason(enum wmi_wow_wake_reason reason)
5929{
5930	switch (reason) {
5931	C2S(WOW_REASON_UNSPECIFIED);
5932	C2S(WOW_REASON_NLOD);
5933	C2S(WOW_REASON_AP_ASSOC_LOST);
5934	C2S(WOW_REASON_LOW_RSSI);
5935	C2S(WOW_REASON_DEAUTH_RECVD);
5936	C2S(WOW_REASON_DISASSOC_RECVD);
5937	C2S(WOW_REASON_GTK_HS_ERR);
5938	C2S(WOW_REASON_EAP_REQ);
5939	C2S(WOW_REASON_FOURWAY_HS_RECV);
5940	C2S(WOW_REASON_TIMER_INTR_RECV);
5941	C2S(WOW_REASON_PATTERN_MATCH_FOUND);
5942	C2S(WOW_REASON_RECV_MAGIC_PATTERN);
5943	C2S(WOW_REASON_P2P_DISC);
5944	C2S(WOW_REASON_WLAN_HB);
5945	C2S(WOW_REASON_CSA_EVENT);
5946	C2S(WOW_REASON_PROBE_REQ_WPS_IE_RECV);
5947	C2S(WOW_REASON_AUTH_REQ_RECV);
5948	C2S(WOW_REASON_ASSOC_REQ_RECV);
5949	C2S(WOW_REASON_HTT_EVENT);
5950	C2S(WOW_REASON_RA_MATCH);
5951	C2S(WOW_REASON_HOST_AUTO_SHUTDOWN);
5952	C2S(WOW_REASON_IOAC_MAGIC_EVENT);
5953	C2S(WOW_REASON_IOAC_SHORT_EVENT);
5954	C2S(WOW_REASON_IOAC_EXTEND_EVENT);
5955	C2S(WOW_REASON_IOAC_TIMER_EVENT);
5956	C2S(WOW_REASON_ROAM_HO);
5957	C2S(WOW_REASON_DFS_PHYERR_RADADR_EVENT);
5958	C2S(WOW_REASON_BEACON_RECV);
5959	C2S(WOW_REASON_CLIENT_KICKOUT_EVENT);
5960	C2S(WOW_REASON_PAGE_FAULT);
5961	C2S(WOW_REASON_DEBUG_TEST);
5962	default:
5963		return NULL;
5964	}
5965}
5966
5967#undef C2S
5968
5969struct wmi_wow_ev_arg {
5970	uint32_t vdev_id;
5971	uint32_t flag;
5972	enum wmi_wow_wake_reason wake_reason;
5973	uint32_t data_len;
5974};
5975
5976enum wmi_tlv_pattern_type {
5977	WOW_PATTERN_MIN = 0,
5978	WOW_BITMAP_PATTERN = WOW_PATTERN_MIN,
5979	WOW_IPV4_SYNC_PATTERN,
5980	WOW_IPV6_SYNC_PATTERN,
5981	WOW_WILD_CARD_PATTERN,
5982	WOW_TIMER_PATTERN,
5983	WOW_MAGIC_PATTERN,
5984	WOW_IPV6_RA_PATTERN,
5985	WOW_IOAC_PKT_PATTERN,
5986	WOW_IOAC_TMR_PATTERN,
5987	WOW_PATTERN_MAX
5988};
5989
5990#define WOW_DEFAULT_BITMAP_PATTERN_SIZE		148
5991#define WOW_DEFAULT_BITMASK_SIZE		148
5992
5993#define WOW_MIN_PATTERN_SIZE	1
5994#define WOW_MAX_PATTERN_SIZE	148
5995#define WOW_MAX_PKT_OFFSET	128
5996#define WOW_HDR_LEN	(sizeof(struct ieee80211_hdr_3addr) + \
5997	sizeof(struct rfc1042_hdr))
5998#define WOW_MAX_REDUCE	(WOW_HDR_LEN - sizeof(struct ethhdr) - \
5999	offsetof(struct ieee80211_hdr_3addr, addr1))
6000
6001struct wmi_wow_add_del_event_cmd {
6002	uint32_t tlv_header;
6003	uint32_t vdev_id;
6004	uint32_t is_add;
6005	uint32_t event_bitmap;
6006} __packed;
6007
6008struct wmi_wow_enable_cmd {
6009	uint32_t tlv_header;
6010	uint32_t enable;
6011	uint32_t pause_iface_config;
6012	uint32_t flags;
6013}  __packed;
6014
6015struct wmi_wow_host_wakeup_ind {
6016	uint32_t tlv_header;
6017	uint32_t reserved;
6018} __packed;
6019
6020struct wmi_tlv_wow_event_info {
6021	uint32_t vdev_id;
6022	uint32_t flag;
6023	uint32_t wake_reason;
6024	uint32_t data_len;
6025} __packed;
6026
6027struct wmi_wow_bitmap_pattern {
6028	uint32_t tlv_header;
6029	uint8_t patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE];
6030	uint8_t bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE];
6031	uint32_t pattern_offset;
6032	uint32_t pattern_len;
6033	uint32_t bitmask_len;
6034	uint32_t pattern_id;
6035} __packed;
6036
6037struct wmi_wow_add_pattern_cmd {
6038	uint32_t tlv_header;
6039	uint32_t vdev_id;
6040	uint32_t pattern_id;
6041	uint32_t pattern_type;
6042} __packed;
6043
6044struct wmi_wow_del_pattern_cmd {
6045	uint32_t tlv_header;
6046	uint32_t vdev_id;
6047	uint32_t pattern_id;
6048	uint32_t pattern_type;
6049} __packed;
6050
6051#define WMI_PNO_MAX_SCHED_SCAN_PLANS      2
6052#define WMI_PNO_MAX_SCHED_SCAN_PLAN_INT   7200
6053#define WMI_PNO_MAX_SCHED_SCAN_PLAN_ITRNS 100
6054#define WMI_PNO_MAX_NETW_CHANNELS         26
6055#define WMI_PNO_MAX_NETW_CHANNELS_EX      60
6056#define WMI_PNO_MAX_SUPP_NETWORKS         WLAN_SCAN_PARAMS_MAX_SSID
6057#define WMI_PNO_MAX_IE_LENGTH             WLAN_SCAN_PARAMS_MAX_IE_LEN
6058
6059/* size based of dot11 declaration without extra IEs as we will not carry those for PNO */
6060#define WMI_PNO_MAX_PB_REQ_SIZE    450
6061
6062#define WMI_PNO_24G_DEFAULT_CH     1
6063#define WMI_PNO_5G_DEFAULT_CH      36
6064
6065#define WMI_ACTIVE_MAX_CHANNEL_TIME 40
6066#define WMI_PASSIVE_MAX_CHANNEL_TIME   110
6067
6068/* SSID broadcast type */
6069enum wmi_ssid_bcast_type {
6070	BCAST_UNKNOWN      = 0,
6071	BCAST_NORMAL       = 1,
6072	BCAST_HIDDEN       = 2,
6073};
6074
6075#define WMI_NLO_MAX_SSIDS    16
6076#define WMI_NLO_MAX_CHAN     48
6077
6078#define WMI_NLO_CONFIG_STOP                             BIT(0)
6079#define WMI_NLO_CONFIG_START                            BIT(1)
6080#define WMI_NLO_CONFIG_RESET                            BIT(2)
6081#define WMI_NLO_CONFIG_SLOW_SCAN                        BIT(4)
6082#define WMI_NLO_CONFIG_FAST_SCAN                        BIT(5)
6083#define WMI_NLO_CONFIG_SSID_HIDE_EN                     BIT(6)
6084
6085/* This bit is used to indicate if EPNO or supplicant PNO is enabled.
6086 * Only one of them can be enabled at a given time
6087 */
6088#define WMI_NLO_CONFIG_ENLO                             BIT(7)
6089#define WMI_NLO_CONFIG_SCAN_PASSIVE                     BIT(8)
6090#define WMI_NLO_CONFIG_ENLO_RESET                       BIT(9)
6091#define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ         BIT(10)
6092#define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ       BIT(11)
6093#define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12)
6094#define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG          BIT(13)
6095
6096struct wmi_nlo_ssid_param {
6097	uint32_t valid;
6098	struct wmi_ssid ssid;
6099} __packed;
6100
6101struct wmi_nlo_enc_param {
6102	uint32_t valid;
6103	uint32_t enc_type;
6104} __packed;
6105
6106struct wmi_nlo_auth_param {
6107	uint32_t valid;
6108	uint32_t auth_type;
6109} __packed;
6110
6111struct wmi_nlo_bcast_nw_param {
6112	uint32_t valid;
6113	uint32_t bcast_nw_type;
6114} __packed;
6115
6116struct wmi_nlo_rssi_param {
6117	uint32_t valid;
6118	int32_t rssi;
6119} __packed;
6120
6121struct nlo_configured_parameters {
6122	/* TLV tag and len;*/
6123	uint32_t tlv_header;
6124	struct wmi_nlo_ssid_param ssid;
6125	struct wmi_nlo_enc_param enc_type;
6126	struct wmi_nlo_auth_param auth_type;
6127	struct wmi_nlo_rssi_param rssi_cond;
6128
6129	/* indicates if the SSID is hidden or not */
6130	struct wmi_nlo_bcast_nw_param bcast_nw_type;
6131} __packed;
6132
6133struct wmi_network_type {
6134	struct wmi_ssid ssid;
6135	uint32_t authentication;
6136	uint32_t encryption;
6137	uint32_t bcast_nw_type;
6138	uint8_t channel_count;
6139	uint16_t channels[WMI_PNO_MAX_NETW_CHANNELS_EX];
6140	int32_t rssi_threshold;
6141};
6142
6143struct wmi_pno_scan_req {
6144	uint8_t enable;
6145	uint8_t vdev_id;
6146	uint8_t uc_networks_count;
6147	struct wmi_network_type a_networks[WMI_PNO_MAX_SUPP_NETWORKS];
6148	uint32_t fast_scan_period;
6149	uint32_t slow_scan_period;
6150	uint8_t fast_scan_max_cycles;
6151
6152	bool do_passive_scan;
6153
6154	uint32_t delay_start_time;
6155	uint32_t active_min_time;
6156	uint32_t active_max_time;
6157	uint32_t passive_min_time;
6158	uint32_t passive_max_time;
6159
6160	/* mac address randomization attributes */
6161	uint32_t enable_pno_scan_randomization;
6162	uint8_t mac_addr[IEEE80211_ADDR_LEN];
6163	uint8_t mac_addr_mask[IEEE80211_ADDR_LEN];
6164};
6165
6166struct wmi_wow_nlo_config_cmd {
6167	uint32_t tlv_header;
6168	uint32_t flags;
6169	uint32_t vdev_id;
6170	uint32_t fast_scan_max_cycles;
6171	uint32_t active_dwell_time;
6172	uint32_t passive_dwell_time;
6173	uint32_t probe_bundle_size;
6174
6175	/* ART = IRT */
6176	uint32_t rest_time;
6177
6178	/* Max value that can be reached after SBM */
6179	uint32_t max_rest_time;
6180
6181	/* SBM */
6182	uint32_t scan_backoff_multiplier;
6183
6184	/* SCBM */
6185	uint32_t fast_scan_period;
6186
6187	/* specific to windows */
6188	uint32_t slow_scan_period;
6189
6190	uint32_t no_of_ssids;
6191
6192	uint32_t num_of_channels;
6193
6194	/* NLO scan start delay time in milliseconds */
6195	uint32_t delay_start_time;
6196
6197	/* MAC Address to use in Probe Req as SA */
6198	struct wmi_mac_addr mac_addr;
6199
6200	/* Mask on which MAC has to be randomized */
6201	struct wmi_mac_addr mac_mask;
6202
6203	/* IE bitmap to use in Probe Req */
6204	uint32_t ie_bitmap[8];
6205
6206	/* Number of vendor OUIs. In the TLV vendor_oui[] */
6207	uint32_t num_vendor_oui;
6208
6209	/* Number of connected NLO band preferences */
6210	uint32_t num_cnlo_band_pref;
6211
6212	/* The TLVs will follow.
6213	 * nlo_configured_parameters nlo_list[];
6214	 * uint32_t channel_list[num_of_channels];
6215	 */
6216} __packed;
6217
6218#define WMI_MAX_NS_OFFLOADS           2
6219#define WMI_MAX_ARP_OFFLOADS          2
6220
6221#define WMI_ARPOL_FLAGS_VALID              BIT(0)
6222#define WMI_ARPOL_FLAGS_MAC_VALID          BIT(1)
6223#define WMI_ARPOL_FLAGS_REMOTE_IP_VALID    BIT(2)
6224
6225struct wmi_arp_offload_tuple {
6226	uint32_t tlv_header;
6227	uint32_t flags;
6228	uint8_t target_ipaddr[4];
6229	uint8_t remote_ipaddr[4];
6230	struct wmi_mac_addr target_mac;
6231} __packed;
6232
6233#define WMI_NSOL_FLAGS_VALID               BIT(0)
6234#define WMI_NSOL_FLAGS_MAC_VALID           BIT(1)
6235#define WMI_NSOL_FLAGS_REMOTE_IP_VALID     BIT(2)
6236#define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST     BIT(3)
6237
6238#define WMI_NSOL_MAX_TARGET_IPS    2
6239
6240struct wmi_ns_offload_tuple {
6241	uint32_t tlv_header;
6242	uint32_t flags;
6243	uint8_t target_ipaddr[WMI_NSOL_MAX_TARGET_IPS][16];
6244	uint8_t solicitation_ipaddr[16];
6245	uint8_t remote_ipaddr[16];
6246	struct wmi_mac_addr target_mac;
6247} __packed;
6248
6249struct wmi_set_arp_ns_offload_cmd {
6250	uint32_t tlv_header;
6251	uint32_t flags;
6252	uint32_t vdev_id;
6253	uint32_t num_ns_ext_tuples;
6254	/* The TLVs follow:
6255	 * wmi_ns_offload_tuple  ns_tuples[WMI_MAX_NS_OFFLOADS];
6256	 * wmi_arp_offload_tuple arp_tuples[WMI_MAX_ARP_OFFLOADS];
6257	 * wmi_ns_offload_tuple  ns_ext_tuples[num_ns_ext_tuples];
6258	 */
6259} __packed;
6260
6261#define GTK_OFFLOAD_OPCODE_MASK             0xFF000000
6262#define GTK_OFFLOAD_ENABLE_OPCODE           0x01000000
6263#define GTK_OFFLOAD_DISABLE_OPCODE          0x02000000
6264#define GTK_OFFLOAD_REQUEST_STATUS_OPCODE   0x04000000
6265
6266#define GTK_OFFLOAD_KEK_BYTES       16
6267#define GTK_OFFLOAD_KCK_BYTES       16
6268#define GTK_REPLAY_COUNTER_BYTES    8
6269#define WMI_MAX_KEY_LEN             32
6270#define IGTK_PN_SIZE                6
6271
6272struct wmi_replayc_cnt {
6273	union {
6274		uint8_t counter[GTK_REPLAY_COUNTER_BYTES];
6275		struct {
6276			uint32_t word0;
6277			uint32_t word1;
6278		} __packed;
6279	} __packed;
6280} __packed;
6281
6282struct wmi_gtk_offload_status_event {
6283	uint32_t vdev_id;
6284	uint32_t flags;
6285	uint32_t refresh_cnt;
6286	struct wmi_replayc_cnt replay_ctr;
6287	uint8_t igtk_key_index;
6288	uint8_t igtk_key_length;
6289	uint8_t igtk_key_rsc[IGTK_PN_SIZE];
6290	uint8_t igtk_key[WMI_MAX_KEY_LEN];
6291	uint8_t gtk_key_index;
6292	uint8_t gtk_key_length;
6293	uint8_t gtk_key_rsc[GTK_REPLAY_COUNTER_BYTES];
6294	uint8_t gtk_key[WMI_MAX_KEY_LEN];
6295} __packed;
6296
6297struct wmi_gtk_rekey_offload_cmd {
6298	uint32_t tlv_header;
6299	uint32_t vdev_id;
6300	uint32_t flags;
6301	uint8_t kek[GTK_OFFLOAD_KEK_BYTES];
6302	uint8_t kck[GTK_OFFLOAD_KCK_BYTES];
6303	uint8_t replay_ctr[GTK_REPLAY_COUNTER_BYTES];
6304} __packed;
6305
6306#define BIOS_SAR_TABLE_LEN	(22)
6307#define BIOS_SAR_RSVD1_LEN	(6)
6308#define BIOS_SAR_RSVD2_LEN	(18)
6309
6310struct wmi_pdev_set_sar_table_cmd {
6311	uint32_t tlv_header;
6312	uint32_t pdev_id;
6313	uint32_t sar_len;
6314	uint32_t rsvd_len;
6315} __packed;
6316
6317struct wmi_pdev_set_geo_table_cmd {
6318	uint32_t tlv_header;
6319	uint32_t pdev_id;
6320	uint32_t rsvd_len;
6321} __packed;
6322
6323struct wmi_sta_keepalive_cmd {
6324	uint32_t tlv_header;
6325	uint32_t vdev_id;
6326	uint32_t enabled;
6327
6328	/* WMI_STA_KEEPALIVE_METHOD_ */
6329	uint32_t method;
6330
6331	/* in seconds */
6332	uint32_t interval;
6333
6334	/* following this structure is the TLV for struct
6335	 * wmi_sta_keepalive_arp_resp
6336	 */
6337} __packed;
6338
6339struct wmi_sta_keepalive_arp_resp {
6340	uint32_t tlv_header;
6341	uint32_t src_ip4_addr;
6342	uint32_t dest_ip4_addr;
6343	struct wmi_mac_addr dest_mac_addr;
6344} __packed;
6345
6346struct wmi_sta_keepalive_arg {
6347	uint32_t vdev_id;
6348	uint32_t enabled;
6349	uint32_t method;
6350	uint32_t interval;
6351	uint32_t src_ip4_addr;
6352	uint32_t dest_ip4_addr;
6353	const uint8_t dest_mac_addr[IEEE80211_ADDR_LEN];
6354};
6355
6356enum wmi_sta_keepalive_method {
6357	WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1,
6358	WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2,
6359	WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3,
6360	WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4,
6361	WMI_STA_KEEPALIVE_METHOD_MGMT_VENDOR_ACTION = 5,
6362};
6363
6364#define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT	30
6365#define WMI_STA_KEEPALIVE_INTERVAL_DISABLE	0
6366
6367
6368/*
6369 * qrtr.h
6370 */
6371
6372#define QRTR_PROTO_VER_1	1
6373#define QRTR_PROTO_VER_2	3 /* (sic!) */
6374
6375struct qrtr_hdr_v1 {
6376	uint32_t version;
6377	uint32_t type;
6378	uint32_t src_node_id;
6379	uint32_t src_port_id;
6380	uint32_t confirm_rx;
6381	uint32_t size;
6382	uint32_t dst_node_id;
6383	uint32_t dst_port_id;
6384} __packed;
6385
6386struct qrtr_hdr_v2 {
6387	uint8_t version;
6388	uint8_t type;
6389	uint8_t flags;
6390	uint8_t optlen;
6391	uint32_t size;
6392	uint16_t src_node_id;
6393	uint16_t src_port_id;
6394	uint16_t dst_node_id;
6395	uint16_t dst_port_id;
6396};
6397
6398struct qrtr_ctrl_pkt {
6399	uint32_t cmd;
6400
6401	union {
6402		struct {
6403			uint32_t service;
6404			uint32_t instance;
6405			uint32_t node;
6406			uint32_t port;
6407		} server;
6408		struct {
6409			uint32_t node;
6410			uint32_t port;
6411		} client;
6412	};
6413} __packed;
6414
6415#define QRTR_TYPE_DATA		1
6416#define QRTR_TYPE_HELLO		2
6417#define QRTR_TYPE_BYE		3
6418#define QRTR_TYPE_NEW_SERVER	4
6419#define QRTR_TYPE_DEL_SERVER	5
6420#define QRTR_TYPE_DEL_CLIENT	6
6421#define QRTR_TYPE_RESUME_TX	7
6422#define QRTR_TYPE_EXIT		8
6423#define QRTR_TYPE_PING		9
6424#define QRTR_TYPE_NEW_LOOKUP	10
6425#define QRTR_TYPE_DEL_LOOKUP	11
6426
6427#define QRTR_FLAGS_CONFIRM_RX	(1 << 0)
6428
6429#define QRTR_NODE_BCAST		0xffffffffU
6430#define QRTR_PORT_CTRL		0xfffffffeU
6431
6432/*
6433 * qmi.h
6434 */
6435
6436#define QMI_REQUEST	0
6437#define QMI_RESPONSE	2
6438#define QMI_INDICATION	4
6439
6440struct qmi_header {
6441	uint8_t type;
6442	uint16_t txn_id;
6443	uint16_t msg_id;
6444	uint16_t msg_len;
6445} __packed;
6446
6447#define QMI_COMMON_TLV_TYPE	0
6448
6449enum qmi_elem_type {
6450	QMI_EOTI,
6451	QMI_OPT_FLAG,
6452	QMI_DATA_LEN,
6453	QMI_UNSIGNED_1_BYTE,
6454	QMI_UNSIGNED_2_BYTE,
6455	QMI_UNSIGNED_4_BYTE,
6456	QMI_UNSIGNED_8_BYTE,
6457	QMI_SIGNED_2_BYTE_ENUM,
6458	QMI_SIGNED_4_BYTE_ENUM,
6459	QMI_STRUCT,
6460	QMI_STRING,
6461	QMI_NUM_DATA_TYPES
6462};
6463
6464enum qmi_array_type {
6465	NO_ARRAY,
6466	STATIC_ARRAY,
6467	VAR_LEN_ARRAY,
6468};
6469
6470struct qmi_elem_info {
6471	enum qmi_elem_type data_type;
6472	uint32_t elem_len;
6473	uint32_t elem_size;
6474	enum qmi_array_type array_type;
6475	uint8_t tlv_type;
6476	uint32_t offset;
6477	const struct qmi_elem_info *ei_array;
6478};
6479
6480#define QMI_RESULT_SUCCESS_V01			0
6481#define QMI_RESULT_FAILURE_V01			1
6482
6483#define QMI_ERR_NONE_V01			0
6484#define QMI_ERR_MALFORMED_MSG_V01		1
6485#define QMI_ERR_NO_MEMORY_V01			2
6486#define QMI_ERR_INTERNAL_V01			3
6487#define QMI_ERR_CLIENT_IDS_EXHAUSTED_V01	5
6488#define QMI_ERR_INVALID_ID_V01			41
6489#define QMI_ERR_ENCODING_V01			58
6490#define QMI_ERR_DISABLED_V01                    69
6491#define QMI_ERR_INCOMPATIBLE_STATE_V01		90
6492#define QMI_ERR_NOT_SUPPORTED_V01		94
6493
6494struct qmi_response_type_v01 {
6495	uint16_t result;
6496	uint16_t error;
6497};
6498
6499#define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN			0
6500#define QMI_WLANFW_PHY_CAP_REQ_V01				0x0057
6501#define QMI_WLANFW_PHY_CAP_RESP_MSG_V01_MAX_LEN			18
6502#define QMI_WLANFW_PHY_CAP_RESP_V01				0x0057
6503
6504struct qmi_wlanfw_phy_cap_req_msg_v01 {
6505};
6506
6507struct qmi_wlanfw_phy_cap_resp_msg_v01 {
6508	struct qmi_response_type_v01 resp;
6509	uint8_t num_phy_valid;
6510	uint8_t num_phy;
6511	uint8_t board_id_valid;
6512	uint32_t board_id;
6513	uint8_t single_chip_mlo_support_valid;
6514	uint8_t single_chip_mlo_support;
6515};
6516
6517#define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN		54
6518#define QMI_WLANFW_IND_REGISTER_REQ_V01				0x0020
6519#define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN		18
6520#define QMI_WLANFW_IND_REGISTER_RESP_V01			0x0020
6521#define QMI_WLANFW_CLIENT_ID					0x4b4e454c
6522
6523struct qmi_wlanfw_ind_register_req_msg_v01 {
6524	uint8_t fw_ready_enable_valid;
6525	uint8_t fw_ready_enable;
6526	uint8_t initiate_cal_download_enable_valid;
6527	uint8_t initiate_cal_download_enable;
6528	uint8_t initiate_cal_update_enable_valid;
6529	uint8_t initiate_cal_update_enable;
6530	uint8_t msa_ready_enable_valid;
6531	uint8_t msa_ready_enable;
6532	uint8_t pin_connect_result_enable_valid;
6533	uint8_t pin_connect_result_enable;
6534	uint8_t client_id_valid;
6535	uint32_t client_id;
6536	uint8_t request_mem_enable_valid;
6537	uint8_t request_mem_enable;
6538	uint8_t fw_mem_ready_enable_valid;
6539	uint8_t fw_mem_ready_enable;
6540	uint8_t fw_init_done_enable_valid;
6541	uint8_t fw_init_done_enable;
6542	uint8_t rejuvenate_enable_valid;
6543	uint32_t rejuvenate_enable;
6544	uint8_t xo_cal_enable_valid;
6545	uint8_t xo_cal_enable;
6546	uint8_t cal_done_enable_valid;
6547	uint8_t cal_done_enable;
6548};
6549
6550struct qmi_wlanfw_ind_register_resp_msg_v01 {
6551	struct qmi_response_type_v01 resp;
6552	uint8_t fw_status_valid;
6553	uint64_t fw_status;
6554};
6555
6556#define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN		261
6557#define QMI_WLANFW_HOST_CAP_REQ_V01			0x0034
6558#define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN	7
6559#define QMI_WLFW_HOST_CAP_RESP_V01			0x0034
6560#define QMI_WLFW_MAX_NUM_GPIO_V01			32
6561#define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01		64
6562#define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01		3
6563#define QMI_IPQ8074_FW_MEM_MODE				0xFF
6564#define HOST_DDR_REGION_TYPE				0x1
6565#define BDF_MEM_REGION_TYPE				0x2
6566#define M3_DUMP_REGION_TYPE				0x3
6567#define CALDB_MEM_REGION_TYPE				0x4
6568
6569struct qmi_wlanfw_host_ddr_range {
6570	uint64_t start;
6571	uint64_t size;
6572};
6573
6574enum qmi_wlanfw_host_build_type {
6575	WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
6576	QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0,
6577	QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1,
6578	QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2,
6579	WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
6580};
6581
6582#define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3
6583#define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2
6584
6585struct wlfw_host_mlo_chip_info_s_v01 {
6586	uint8_t chip_id;
6587	uint8_t num_local_links;
6588	uint8_t hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
6589	uint8_t valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
6590};
6591
6592enum ath12k_qmi_cnss_feature {
6593	CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN,
6594	CNSS_QDSS_CFG_MISS_V01 = 3,
6595	CNSS_PCIE_PERST_NO_PULL_V01 = 4,
6596	CNSS_MAX_FEATURE_V01 = 64,
6597	CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX,
6598};
6599
6600struct qmi_wlanfw_host_cap_req_msg_v01 {
6601	uint8_t num_clients_valid;
6602	uint32_t num_clients;
6603	uint8_t wake_msi_valid;
6604	uint32_t wake_msi;
6605	uint8_t gpios_valid;
6606	uint32_t gpios_len;
6607	uint32_t gpios[QMI_WLFW_MAX_NUM_GPIO_V01];
6608	uint8_t nm_modem_valid;
6609	uint8_t nm_modem;
6610	uint8_t bdf_support_valid;
6611	uint8_t bdf_support;
6612	uint8_t bdf_cache_support_valid;
6613	uint8_t bdf_cache_support;
6614	uint8_t m3_support_valid;
6615	uint8_t m3_support;
6616	uint8_t m3_cache_support_valid;
6617	uint8_t m3_cache_support;
6618	uint8_t cal_filesys_support_valid;
6619	uint8_t cal_filesys_support;
6620	uint8_t cal_cache_support_valid;
6621	uint8_t cal_cache_support;
6622	uint8_t cal_done_valid;
6623	uint8_t cal_done;
6624	uint8_t mem_bucket_valid;
6625	uint32_t mem_bucket;
6626	uint8_t mem_cfg_mode_valid;
6627	uint8_t mem_cfg_mode;
6628	uint8_t cal_duration_valid;
6629	uint16_t cal_duration;
6630	uint8_t platform_name_valid;
6631	char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1];
6632	uint8_t ddr_range_valid;
6633	struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01];
6634	uint8_t host_build_type_valid;
6635	enum qmi_wlanfw_host_build_type host_build_type;
6636	uint8_t mlo_capable_valid;
6637	uint8_t mlo_capable;
6638	uint8_t mlo_chip_id_valid;
6639	uint16_t mlo_chip_id;
6640	uint8_t mlo_group_id_valid;
6641	uint8_t mlo_group_id;
6642	uint8_t max_mlo_peer_valid;
6643	uint16_t max_mlo_peer;
6644	uint8_t mlo_num_chips_valid;
6645	uint8_t mlo_num_chips;
6646	uint8_t mlo_chip_info_valid;
6647	struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01];
6648	uint8_t feature_list_valid;
6649	uint64_t feature_list;
6650};
6651
6652struct qmi_wlanfw_host_cap_resp_msg_v01 {
6653	struct qmi_response_type_v01 resp;
6654};
6655
6656#define ATH12K_HOST_VERSION_STRING		"WIN"
6657#define ATH12K_QMI_WLANFW_TIMEOUT_MS		10000
6658#define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE	64
6659#define ATH12K_QMI_CALDB_ADDRESS		0x4BA00000
6660#define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01	128
6661#define ATH12K_QMI_WLFW_SERVICE_ID_V01		0x45
6662#define ATH12K_QMI_WLFW_SERVICE_VERS_V01	0x01
6663#define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01	0x02
6664#define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850	0x01
6665#define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274	0x07
6666#define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01	32
6667
6668#define ATH12K_QMI_RESP_LEN_MAX			8192
6669#define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01	52
6670#define ATH12K_QMI_CALDB_SIZE			0x480000
6671#define ATH12K_QMI_BDF_EXT_STR_LENGTH		0x20
6672#define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT	3
6673#define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01	4
6674#define ATH12K_QMI_DEVMEM_CMEM_INDEX		0
6675
6676#define QMI_WLFW_REQUEST_MEM_IND_V01		0x0035
6677#define QMI_WLFW_RESPOND_MEM_RESP_V01		0x0036
6678#define QMI_WLFW_FW_MEM_READY_IND_V01		0x0037
6679#define QMI_WLFW_FW_READY_IND_V01		0x0038
6680
6681#define QMI_WLANFW_MAX_DATA_SIZE_V01		6144
6682#define ATH12K_FIRMWARE_MODE_OFF		4
6683#define ATH12K_QMI_TARGET_MEM_MODE_DEFAULT	0
6684
6685#define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN	1824
6686#define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN	888
6687#define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN	7
6688#define QMI_WLANFW_REQUEST_MEM_IND_V01			0x0035
6689#define QMI_WLANFW_RESPOND_MEM_REQ_V01			0x0036
6690#define QMI_WLANFW_RESPOND_MEM_RESP_V01			0x0036
6691#define QMI_WLANFW_MAX_NUM_MEM_CFG_V01			2
6692
6693struct qmi_wlanfw_mem_cfg_s_v01 {
6694	uint64_t offset;
6695	uint32_t size;
6696	uint8_t secure_flag;
6697};
6698
6699enum qmi_wlanfw_mem_type_enum_v01 {
6700	WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
6701	QMI_WLANFW_MEM_TYPE_MSA_V01 = 0,
6702	QMI_WLANFW_MEM_TYPE_DDR_V01 = 1,
6703	QMI_WLANFW_MEM_BDF_V01 = 2,
6704	QMI_WLANFW_MEM_M3_V01 = 3,
6705	QMI_WLANFW_MEM_CAL_V01 = 4,
6706	QMI_WLANFW_MEM_DPD_V01 = 5,
6707	WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
6708};
6709
6710struct qmi_wlanfw_mem_seg_s_v01 {
6711	uint32_t size;
6712	enum qmi_wlanfw_mem_type_enum_v01 type;
6713	uint32_t mem_cfg_len;
6714	struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01];
6715};
6716
6717struct qmi_wlanfw_request_mem_ind_msg_v01 {
6718	uint32_t mem_seg_len;
6719	struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
6720};
6721
6722struct qmi_wlanfw_mem_seg_resp_s_v01 {
6723	uint64_t addr;
6724	uint32_t size;
6725	enum qmi_wlanfw_mem_type_enum_v01 type;
6726	uint8_t restore;
6727};
6728
6729struct qmi_wlanfw_respond_mem_req_msg_v01 {
6730	uint32_t mem_seg_len;
6731	struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
6732};
6733
6734struct qmi_wlanfw_respond_mem_resp_msg_v01 {
6735	struct qmi_response_type_v01 resp;
6736};
6737
6738struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 {
6739	char placeholder;
6740};
6741
6742struct qmi_wlanfw_fw_ready_ind_msg_v01 {
6743	char placeholder;
6744};
6745
6746struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 {
6747	char placeholder;
6748};
6749
6750struct qmi_wlfw_fw_init_done_ind_msg_v01 {
6751	char placeholder;
6752};
6753
6754#define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN		0
6755#define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN		235
6756#define QMI_WLANFW_CAP_REQ_V01				0x0024
6757#define QMI_WLANFW_CAP_RESP_V01				0x0024
6758#define QMI_WLANFW_DEVICE_INFO_REQ_V01			0x004C
6759#define QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN	0
6760
6761enum qmi_wlanfw_pipedir_enum_v01 {
6762	QMI_WLFW_PIPEDIR_NONE_V01 = 0,
6763	QMI_WLFW_PIPEDIR_IN_V01 = 1,
6764	QMI_WLFW_PIPEDIR_OUT_V01 = 2,
6765	QMI_WLFW_PIPEDIR_INOUT_V01 = 3,
6766};
6767
6768struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 {
6769	uint32_t pipe_num;
6770	uint32_t pipe_dir;
6771	uint32_t nentries;
6772	uint32_t nbytes_max;
6773	uint32_t flags;
6774};
6775
6776struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 {
6777	uint32_t service_id;
6778	uint32_t pipe_dir;
6779	uint32_t pipe_num;
6780};
6781
6782struct qmi_wlanfw_shadow_reg_cfg_s_v01 {
6783	uint16_t id;
6784	uint16_t offset;
6785};
6786
6787struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 {
6788	uint32_t addr;
6789};
6790
6791struct qmi_wlanfw_memory_region_info_s_v01 {
6792	uint64_t region_addr;
6793	uint32_t size;
6794	uint8_t secure_flag;
6795};
6796
6797struct qmi_wlanfw_rf_chip_info_s_v01 {
6798	uint32_t chip_id;
6799	uint32_t chip_family;
6800};
6801
6802struct qmi_wlanfw_rf_board_info_s_v01 {
6803	uint32_t board_id;
6804};
6805
6806struct qmi_wlanfw_soc_info_s_v01 {
6807	uint32_t soc_id;
6808};
6809
6810struct qmi_wlanfw_fw_version_info_s_v01 {
6811	uint32_t fw_version;
6812	char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
6813};
6814
6815struct qmi_wlanfw_dev_mem_info_s_v01 {
6816	uint64_t start;
6817	uint64_t size;
6818};
6819
6820enum qmi_wlanfw_cal_temp_id_enum_v01 {
6821	QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0,
6822	QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1,
6823	QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2,
6824	QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3,
6825	QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4,
6826	QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF,
6827};
6828
6829enum qmi_wlanfw_rd_card_chain_cap_v01 {
6830	WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN,
6831	WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0,
6832	WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1,
6833	WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2,
6834	WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX,
6835};
6836
6837struct qmi_wlanfw_cap_resp_msg_v01 {
6838	struct qmi_response_type_v01 resp;
6839	uint8_t chip_info_valid;
6840	struct qmi_wlanfw_rf_chip_info_s_v01 chip_info;
6841	uint8_t board_info_valid;
6842	struct qmi_wlanfw_rf_board_info_s_v01 board_info;
6843	uint8_t soc_info_valid;
6844	struct qmi_wlanfw_soc_info_s_v01 soc_info;
6845	uint8_t fw_version_info_valid;
6846	struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info;
6847	uint8_t fw_build_id_valid;
6848	char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
6849	uint8_t num_macs_valid;
6850	uint8_t num_macs;
6851	uint8_t voltage_mv_valid;
6852	uint32_t voltage_mv;
6853	uint8_t time_freq_hz_valid;
6854	uint32_t time_freq_hz;
6855	uint8_t otp_version_valid;
6856	uint32_t otp_version;
6857	uint8_t eeprom_read_timeout_valid;
6858	uint32_t eeprom_read_timeout;
6859	uint8_t fw_caps_valid;
6860	uint64_t fw_caps;
6861	uint8_t rd_card_chain_cap_valid;
6862	enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap;
6863	uint8_t dev_mem_info_valid;
6864	struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
6865};
6866
6867struct qmi_wlanfw_cap_req_msg_v01 {
6868	char placeholder;
6869};
6870
6871#define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN	6182
6872#define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN	7
6873#define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01		0x0025
6874#define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01			0x0025
6875/* TODO: Need to check with MCL and FW team that data can be pointer and
6876 * can be last element in structure
6877 */
6878struct qmi_wlanfw_bdf_download_req_msg_v01 {
6879	uint8_t valid;
6880	uint8_t file_id_valid;
6881	enum qmi_wlanfw_cal_temp_id_enum_v01 file_id;
6882	uint8_t total_size_valid;
6883	uint32_t total_size;
6884	uint8_t seg_id_valid;
6885	uint32_t seg_id;
6886	uint8_t data_valid;
6887	uint32_t data_len;
6888	uint8_t data[QMI_WLANFW_MAX_DATA_SIZE_V01];
6889	uint8_t end_valid;
6890	uint8_t end;
6891	uint8_t bdf_type_valid;
6892	uint8_t bdf_type;
6893};
6894
6895struct qmi_wlanfw_bdf_download_resp_msg_v01 {
6896	struct qmi_response_type_v01 resp;
6897};
6898
6899#define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN	18
6900#define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN	7
6901#define QMI_WLANFW_M3_INFO_RESP_V01		0x003c
6902#define QMI_WLANFW_M3_INFO_REQ_V01		0x003c
6903
6904struct qmi_wlanfw_m3_info_req_msg_v01 {
6905	uint64_t addr;
6906	uint32_t size;
6907};
6908
6909struct qmi_wlanfw_m3_info_resp_msg_v01 {
6910	struct qmi_response_type_v01 resp;
6911};
6912
6913#define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN	11
6914#define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN	7
6915#define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN		803
6916#define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN	7
6917#define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN		7
6918#define QMI_WLANFW_WLAN_MODE_REQ_V01			0x0022
6919#define QMI_WLANFW_WLAN_MODE_RESP_V01			0x0022
6920#define QMI_WLANFW_WLAN_CFG_REQ_V01			0x0023
6921#define QMI_WLANFW_WLAN_CFG_RESP_V01			0x0023
6922#define QMI_WLANFW_WLAN_INI_REQ_V01			0x002f
6923#define QMI_WLANFW_WLAN_INI_RESP_V01			0x002f
6924#define QMI_WLANFW_MAX_STR_LEN_V01			16
6925#define QMI_WLANFW_MAX_NUM_CE_V01			12
6926#define QMI_WLANFW_MAX_NUM_SVC_V01			24
6927#define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01		24
6928#define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01		60
6929
6930struct qmi_wlanfw_wlan_mode_req_msg_v01 {
6931	uint32_t mode;
6932	uint8_t hw_debug_valid;
6933	uint8_t hw_debug;
6934};
6935
6936struct qmi_wlanfw_wlan_mode_resp_msg_v01 {
6937	struct qmi_response_type_v01 resp;
6938};
6939
6940struct qmi_wlanfw_wlan_cfg_req_msg_v01 {
6941	uint8_t host_version_valid;
6942	char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1];
6943	uint8_t tgt_cfg_valid;
6944	uint32_t tgt_cfg_len;
6945	struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01
6946	    tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01];
6947	uint8_t svc_cfg_valid;
6948	uint32_t svc_cfg_len;
6949	struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01
6950	    svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01];
6951	uint8_t shadow_reg_valid;
6952	uint32_t shadow_reg_len;
6953	struct qmi_wlanfw_shadow_reg_cfg_s_v01
6954	    shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01];
6955	uint8_t shadow_reg_v3_valid;
6956	uint32_t shadow_reg_v3_len;
6957	struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01
6958		shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01];
6959};
6960
6961struct qmi_wlanfw_wlan_cfg_resp_msg_v01 {
6962	struct qmi_response_type_v01 resp;
6963};
6964
6965struct qmi_wlanfw_wlan_ini_req_msg_v01 {
6966	/* Must be set to true if enablefwlog is being passed */
6967	uint8_t enablefwlog_valid;
6968	uint8_t enablefwlog;
6969};
6970
6971struct qmi_wlanfw_wlan_ini_resp_msg_v01 {
6972	struct qmi_response_type_v01 resp;
6973};
6974
6975enum ath12k_qmi_file_type {
6976	ATH12K_QMI_FILE_TYPE_BDF_GOLDEN,
6977	ATH12K_QMI_FILE_TYPE_CALDATA = 2,
6978	ATH12K_QMI_FILE_TYPE_EEPROM,
6979	ATH12K_QMI_MAX_FILE_TYPE,
6980};
6981
6982enum ath12k_qmi_bdf_type {
6983	ATH12K_QMI_BDF_TYPE_BIN			= 0,
6984	ATH12K_QMI_BDF_TYPE_ELF			= 1,
6985	ATH12K_QMI_BDF_TYPE_REGDB		= 4,
6986};
6987
6988#define HAL_LINK_DESC_SIZE			(32 << 2)
6989#define HAL_LINK_DESC_ALIGN			128
6990#define HAL_NUM_MPDUS_PER_LINK_DESC		6
6991#define HAL_NUM_TX_MSDUS_PER_LINK_DESC		7
6992#define HAL_NUM_RX_MSDUS_PER_LINK_DESC		6
6993#define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC	12
6994#define HAL_MAX_AVAIL_BLK_RES			3
6995
6996#define HAL_RING_BASE_ALIGN	8
6997
6998#define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX	32704
6999/* TODO: Check with hw team on the supported scatter buf size */
7000#define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE	8
7001#define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \
7002				       HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE)
7003
7004#define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX	32
7005#define HAL_DSCP_TID_TBL_SIZE			24
7006
7007/* calculate the register address from bar0 of shadow register x */
7008#define HAL_SHADOW_BASE_ADDR			0x000008fc
7009#define HAL_SHADOW_NUM_REGS			40
7010#define HAL_HP_OFFSET_IN_REG_START		1
7011#define HAL_OFFSET_FROM_HP_TO_TP		4
7012
7013#define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x)))
7014
7015enum hal_srng_ring_id {
7016	HAL_SRNG_RING_ID_REO2SW0 = 0,
7017	HAL_SRNG_RING_ID_REO2SW1,
7018	HAL_SRNG_RING_ID_REO2SW2,
7019	HAL_SRNG_RING_ID_REO2SW3,
7020	HAL_SRNG_RING_ID_REO2SW4,
7021	HAL_SRNG_RING_ID_REO2SW5,
7022	HAL_SRNG_RING_ID_REO2SW6,
7023	HAL_SRNG_RING_ID_REO2SW7,
7024	HAL_SRNG_RING_ID_REO2SW8,
7025	HAL_SRNG_RING_ID_REO2TCL,
7026	HAL_SRNG_RING_ID_REO2PPE,
7027
7028	HAL_SRNG_RING_ID_SW2REO = 16,
7029	HAL_SRNG_RING_ID_SW2REO1,
7030	HAL_SRNG_RING_ID_SW2REO2,
7031	HAL_SRNG_RING_ID_SW2REO3,
7032
7033	HAL_SRNG_RING_ID_REO_CMD,
7034	HAL_SRNG_RING_ID_REO_STATUS,
7035
7036	HAL_SRNG_RING_ID_SW2TCL1 = 24,
7037	HAL_SRNG_RING_ID_SW2TCL2,
7038	HAL_SRNG_RING_ID_SW2TCL3,
7039	HAL_SRNG_RING_ID_SW2TCL4,
7040	HAL_SRNG_RING_ID_SW2TCL5,
7041	HAL_SRNG_RING_ID_SW2TCL6,
7042	HAL_SRNG_RING_ID_PPE2TCL1	= 30,
7043
7044	HAL_SRNG_RING_ID_SW2TCL_CMD	= 40,
7045	HAL_SRNG_RING_ID_SW2TCL1_CMD,
7046	HAL_SRNG_RING_ID_TCL_STATUS,
7047
7048	HAL_SRNG_RING_ID_CE0_SRC = 64,
7049	HAL_SRNG_RING_ID_CE1_SRC,
7050	HAL_SRNG_RING_ID_CE2_SRC,
7051	HAL_SRNG_RING_ID_CE3_SRC,
7052	HAL_SRNG_RING_ID_CE4_SRC,
7053	HAL_SRNG_RING_ID_CE5_SRC,
7054	HAL_SRNG_RING_ID_CE6_SRC,
7055	HAL_SRNG_RING_ID_CE7_SRC,
7056	HAL_SRNG_RING_ID_CE8_SRC,
7057	HAL_SRNG_RING_ID_CE9_SRC,
7058	HAL_SRNG_RING_ID_CE10_SRC,
7059	HAL_SRNG_RING_ID_CE11_SRC,
7060	HAL_SRNG_RING_ID_CE12_SRC,
7061	HAL_SRNG_RING_ID_CE13_SRC,
7062	HAL_SRNG_RING_ID_CE14_SRC,
7063	HAL_SRNG_RING_ID_CE15_SRC,
7064
7065	HAL_SRNG_RING_ID_CE0_DST = 81,
7066	HAL_SRNG_RING_ID_CE1_DST,
7067	HAL_SRNG_RING_ID_CE2_DST,
7068	HAL_SRNG_RING_ID_CE3_DST,
7069	HAL_SRNG_RING_ID_CE4_DST,
7070	HAL_SRNG_RING_ID_CE5_DST,
7071	HAL_SRNG_RING_ID_CE6_DST,
7072	HAL_SRNG_RING_ID_CE7_DST,
7073	HAL_SRNG_RING_ID_CE8_DST,
7074	HAL_SRNG_RING_ID_CE9_DST,
7075	HAL_SRNG_RING_ID_CE10_DST,
7076	HAL_SRNG_RING_ID_CE11_DST,
7077	HAL_SRNG_RING_ID_CE12_DST,
7078	HAL_SRNG_RING_ID_CE13_DST,
7079	HAL_SRNG_RING_ID_CE14_DST,
7080	HAL_SRNG_RING_ID_CE15_DST,
7081
7082	HAL_SRNG_RING_ID_CE0_DST_STATUS = 100,
7083	HAL_SRNG_RING_ID_CE1_DST_STATUS,
7084	HAL_SRNG_RING_ID_CE2_DST_STATUS,
7085	HAL_SRNG_RING_ID_CE3_DST_STATUS,
7086	HAL_SRNG_RING_ID_CE4_DST_STATUS,
7087	HAL_SRNG_RING_ID_CE5_DST_STATUS,
7088	HAL_SRNG_RING_ID_CE6_DST_STATUS,
7089	HAL_SRNG_RING_ID_CE7_DST_STATUS,
7090	HAL_SRNG_RING_ID_CE8_DST_STATUS,
7091	HAL_SRNG_RING_ID_CE9_DST_STATUS,
7092	HAL_SRNG_RING_ID_CE10_DST_STATUS,
7093	HAL_SRNG_RING_ID_CE11_DST_STATUS,
7094	HAL_SRNG_RING_ID_CE12_DST_STATUS,
7095	HAL_SRNG_RING_ID_CE13_DST_STATUS,
7096	HAL_SRNG_RING_ID_CE14_DST_STATUS,
7097	HAL_SRNG_RING_ID_CE15_DST_STATUS,
7098
7099	HAL_SRNG_RING_ID_WBM_IDLE_LINK = 120,
7100	HAL_SRNG_RING_ID_WBM_SW0_RELEASE,
7101	HAL_SRNG_RING_ID_WBM_SW1_RELEASE,
7102	HAL_SRNG_RING_ID_WBM_PPE_RELEASE = 123,
7103
7104	HAL_SRNG_RING_ID_WBM2SW0_RELEASE = 128,
7105	HAL_SRNG_RING_ID_WBM2SW1_RELEASE,
7106	HAL_SRNG_RING_ID_WBM2SW2_RELEASE,
7107	HAL_SRNG_RING_ID_WBM2SW3_RELEASE, /* RX ERROR RING */
7108	HAL_SRNG_RING_ID_WBM2SW4_RELEASE,
7109	HAL_SRNG_RING_ID_WBM2SW5_RELEASE,
7110	HAL_SRNG_RING_ID_WBM2SW6_RELEASE,
7111	HAL_SRNG_RING_ID_WBM2SW7_RELEASE,
7112
7113	HAL_SRNG_RING_ID_UMAC_ID_END = 159,
7114
7115	/* Common DMAC rings shared by all LMACs */
7116	HAL_SRNG_RING_ID_DMAC_CMN_ID_START = 160,
7117	HAL_SRNG_SW2RXDMA_BUF0 =
7118	    HAL_SRNG_RING_ID_DMAC_CMN_ID_START,
7119	HAL_SRNG_SW2RXDMA_BUF1 = 161,
7120	HAL_SRNG_SW2RXDMA_BUF2 = 162,
7121
7122	HAL_SRNG_SW2RXMON_BUF0 = 168,
7123
7124	HAL_SRNG_SW2TXMON_BUF0 = 176,
7125
7126	HAL_SRNG_RING_ID_DMAC_CMN_ID_END = 183,
7127	HAL_SRNG_RING_ID_PMAC1_ID_START = 184,
7128
7129	HAL_SRNG_RING_ID_WMAC1_SW2RXMON_BUF0 =
7130	    HAL_SRNG_RING_ID_PMAC1_ID_START,
7131
7132	HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0,
7133	HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1,
7134	HAL_SRNG_RING_ID_WMAC1_RXMON2SW0 =
7135	    HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1,
7136	HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC,
7137	HAL_SRNG_RING_ID_RXDMA_DIR_BUF,
7138	HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0,
7139	HAL_SRNG_RING_ID_WMAC1_TXMON2SW0_BUF0,
7140
7141	HAL_SRNG_RING_ID_PMAC1_ID_END,
7142};
7143
7144/* SRNG registers are split into two groups R0 and R2 */
7145#define HAL_SRNG_REG_GRP_R0	0
7146#define HAL_SRNG_REG_GRP_R2	1
7147#define HAL_SRNG_NUM_REG_GRP    2
7148
7149#define HAL_SRNG_NUM_LMACS      3
7150#define HAL_SRNG_REO_EXCEPTION  HAL_SRNG_RING_ID_REO2SW1
7151#define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \
7152				 HAL_SRNG_RING_ID_LMAC1_ID_START)
7153#define HAL_SRNG_NUM_LMAC_RINGS (HAL_SRNG_NUM_LMACS * HAL_SRNG_RINGS_PER_LMAC)
7154
7155/* TODO: number of PMACs */
7156#define HAL_SRNG_NUM_PMACS	3
7157#define HAL_SRNG_NUM_DMAC_RINGS						\
7158	(HAL_SRNG_RING_ID_DMAC_CMN_ID_END -			\
7159	HAL_SRNG_RING_ID_DMAC_CMN_ID_START)
7160#define HAL_SRNG_RINGS_PER_PMAC	(HAL_SRNG_RING_ID_PMAC1_ID_END -	\
7161				 HAL_SRNG_RING_ID_PMAC1_ID_START)
7162#define HAL_SRNG_NUM_PMAC_RINGS	(HAL_SRNG_NUM_PMACS * HAL_SRNG_RINGS_PER_PMAC)
7163#define HAL_SRNG_RING_ID_MAX					\
7164	(HAL_SRNG_RING_ID_DMAC_CMN_ID_END + HAL_SRNG_NUM_PMAC_RINGS)
7165
7166#define HAL_RX_MAX_BA_WINDOW	256
7167
7168#define ATH12K_HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC	(100 * 1000)
7169#define HAL_DEFAULT_REO_TIMEOUT_USEC		(40 * 1000)
7170
7171/**
7172 * enum hal_reo_cmd_type: Enum for REO command type
7173 * @HAL_REO_CMD_GET_QUEUE_STATS: Get REO queue status/stats
7174 * @HAL_REO_CMD_FLUSH_QUEUE: Flush all frames in REO queue
7175 * @HAL_REO_CMD_FLUSH_CACHE: Flush descriptor entries in the cache
7176 * @HAL_REO_CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked
7177 *      earlier with a 'REO_FLUSH_CACHE' command
7178 * @HAL_REO_CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list
7179 * @HAL_REO_CMD_UPDATE_RX_QUEUE: Update REO queue settings
7180 */
7181enum hal_reo_cmd_type {
7182	HAL_REO_CMD_GET_QUEUE_STATS     = 0,
7183	HAL_REO_CMD_FLUSH_QUEUE         = 1,
7184	HAL_REO_CMD_FLUSH_CACHE         = 2,
7185	HAL_REO_CMD_UNBLOCK_CACHE       = 3,
7186	HAL_REO_CMD_FLUSH_TIMEOUT_LIST  = 4,
7187	HAL_REO_CMD_UPDATE_RX_QUEUE     = 5,
7188};
7189
7190/**
7191 * enum hal_reo_cmd_status: Enum for execution status of REO command
7192 * @HAL_REO_CMD_SUCCESS: Command has successfully executed
7193 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue
7194 *			 or cache was blocked
7195 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to
7196 *			invalid queue desc
7197 * @HAL_REO_CMD_RESOURCE_BLOCKED:
7198 * @HAL_REO_CMD_DRAIN:
7199 */
7200enum hal_reo_cmd_status {
7201	HAL_REO_CMD_SUCCESS		= 0,
7202	HAL_REO_CMD_BLOCKED		= 1,
7203	HAL_REO_CMD_FAILED		= 2,
7204	HAL_REO_CMD_RESOURCE_BLOCKED	= 3,
7205	HAL_REO_CMD_DRAIN		= 0xff,
7206};
7207
7208/* Interrupt mitigation - Batch threshold in terms of number of frames */
7209#define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256
7210#define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128
7211#define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1
7212
7213/* Interrupt mitigation - timer threshold in us */
7214#define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000
7215#define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500
7216#define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256
7217
7218/* WCSS Relative address */
7219#define HAL_SEQ_WCSS_UMAC_OFFSET		0x00a00000
7220#define HAL_SEQ_WCSS_UMAC_REO_REG		0x00a38000
7221#define HAL_SEQ_WCSS_UMAC_TCL_REG		0x00a44000
7222#define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG		0x01b80000
7223#define HAL_SEQ_WCSS_UMAC_CE0_DST_REG		0x01b81000
7224#define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG		0x01b82000
7225#define HAL_SEQ_WCSS_UMAC_CE1_DST_REG		0x01b83000
7226#define HAL_SEQ_WCSS_UMAC_WBM_REG		0x00a34000
7227
7228#define HAL_CE_WFSS_CE_REG_BASE			0x01b80000
7229
7230#define HAL_TCL_SW_CONFIG_BANK_ADDR		0x00a4408c
7231
7232/* SW2TCL(x) R0 ring configuration address */
7233#define HAL_TCL1_RING_CMN_CTRL_REG		0x00000020
7234#define HAL_TCL1_RING_DSCP_TID_MAP		0x00000240
7235#define HAL_TCL1_RING_BASE_LSB			0x00000900
7236#define HAL_TCL1_RING_BASE_MSB			0x00000904
7237#define HAL_TCL1_RING_ID(sc)			(sc->hw_params.regs->hal_tcl1_ring_id)
7238#define HAL_TCL1_RING_MISC(sc) \
7239	(sc->hw_params.regs->hal_tcl1_ring_misc)
7240#define HAL_TCL1_RING_TP_ADDR_LSB(sc) \
7241	(sc->hw_params.regs->hal_tcl1_ring_tp_addr_lsb)
7242#define HAL_TCL1_RING_TP_ADDR_MSB(sc) \
7243	(sc->hw_params.regs->hal_tcl1_ring_tp_addr_msb)
7244#define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(sc) \
7245	(sc->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix0)
7246#define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(sc) \
7247	(sc->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix1)
7248#define HAL_TCL1_RING_MSI1_BASE_LSB(sc) \
7249	(sc->hw_params.regs->hal_tcl1_ring_msi1_base_lsb)
7250#define HAL_TCL1_RING_MSI1_BASE_MSB(sc) \
7251	(sc->hw_params.regs->hal_tcl1_ring_msi1_base_msb)
7252#define HAL_TCL1_RING_MSI1_DATA(sc) \
7253	(sc->hw_params.regs->hal_tcl1_ring_msi1_data)
7254#define HAL_TCL2_RING_BASE_LSB			0x00000978
7255#define HAL_TCL_RING_BASE_LSB(sc) \
7256	(sc->hw_params.regs->hal_tcl_ring_base_lsb)
7257
7258#define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(sc)				\
7259	(HAL_TCL1_RING_MSI1_BASE_LSB(sc) - HAL_TCL1_RING_BASE_LSB)
7260#define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(sc)				\
7261	(HAL_TCL1_RING_MSI1_BASE_MSB(sc) - HAL_TCL1_RING_BASE_LSB)
7262#define HAL_TCL1_RING_MSI1_DATA_OFFSET(sc)				\
7263	(HAL_TCL1_RING_MSI1_DATA(sc) - HAL_TCL1_RING_BASE_LSB)
7264#define HAL_TCL1_RING_BASE_MSB_OFFSET				\
7265	(HAL_TCL1_RING_BASE_MSB - HAL_TCL1_RING_BASE_LSB)
7266#define HAL_TCL1_RING_ID_OFFSET(sc)				\
7267	(HAL_TCL1_RING_ID(sc) - HAL_TCL1_RING_BASE_LSB)
7268#define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(sc)			\
7269	(HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(sc) - HAL_TCL1_RING_BASE_LSB)
7270#define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(sc) \
7271		(HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(sc) - HAL_TCL1_RING_BASE_LSB)
7272#define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(sc) \
7273		(HAL_TCL1_RING_TP_ADDR_LSB(sc) - HAL_TCL1_RING_BASE_LSB)
7274#define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(sc) \
7275		(HAL_TCL1_RING_TP_ADDR_MSB(sc) - HAL_TCL1_RING_BASE_LSB)
7276#define HAL_TCL1_RING_MISC_OFFSET(sc) \
7277		(HAL_TCL1_RING_MISC(sc) - HAL_TCL1_RING_BASE_LSB)
7278
7279/* SW2TCL(x) R2 ring pointers (head/tail) address */
7280#define HAL_TCL1_RING_HP			0x00002000
7281#define HAL_TCL1_RING_TP			0x00002004
7282#define HAL_TCL2_RING_HP			0x00002008
7283#define HAL_TCL_RING_HP				0x00002028
7284
7285#define HAL_TCL1_RING_TP_OFFSET \
7286		(HAL_TCL1_RING_TP - HAL_TCL1_RING_HP)
7287
7288/* TCL STATUS ring address */
7289#define HAL_TCL_STATUS_RING_BASE_LSB(sc)	\
7290	(sc->hw_params.regs->hal_tcl_status_ring_base_lsb)
7291#define HAL_TCL_STATUS_RING_HP			0x00002048
7292
7293/* PPE2TCL1 Ring address */
7294#define HAL_TCL_PPE2TCL1_RING_BASE_LSB		0x00000c48
7295#define HAL_TCL_PPE2TCL1_RING_HP		0x00002038
7296
7297/* WBM PPE Release Ring address */
7298#define HAL_WBM_PPE_RELEASE_RING_BASE_LSB(sc) \
7299	(sc->hw_params.regs->hal_ppe_rel_ring_base)
7300#define HAL_WBM_PPE_RELEASE_RING_HP		0x00003020
7301
7302/* REO2SW(x) R0 ring configuration address */
7303#define HAL_REO1_GEN_ENABLE			0x00000000
7304#define HAL_REO1_MISC_CTRL_ADDR(sc) \
7305	(sc->hw_params.regs->hal_reo1_misc_ctrl_addr)
7306#define HAL_REO1_DEST_RING_CTRL_IX_0		0x00000004
7307#define HAL_REO1_DEST_RING_CTRL_IX_1		0x00000008
7308#define HAL_REO1_DEST_RING_CTRL_IX_2		0x0000000c
7309#define HAL_REO1_DEST_RING_CTRL_IX_3		0x00000010
7310#define HAL_REO1_SW_COOKIE_CFG0(sc) \
7311	(sc->hw_params.regs->hal_reo1_sw_cookie_cfg0)
7312#define HAL_REO1_SW_COOKIE_CFG1(sc) \
7313	(sc->hw_params.regs->hal_reo1_sw_cookie_cfg1)
7314#define HAL_REO1_QDESC_LUT_BASE0(sc) \
7315	(sc->hw_params.regs->hal_reo1_qdesc_lut_base0)
7316#define HAL_REO1_QDESC_LUT_BASE1(sc) \
7317	(sc->hw_params.regs->hal_reo1_qdesc_lut_base1)
7318#define HAL_REO1_RING_BASE_LSB(sc) \
7319	(sc->hw_params.regs->hal_reo1_ring_base_lsb)
7320#define HAL_REO1_RING_BASE_MSB(sc) \
7321	(sc->hw_params.regs->hal_reo1_ring_base_msb)
7322#define HAL_REO1_RING_ID(sc) \
7323	(sc->hw_params.regs->hal_reo1_ring_id)
7324#define HAL_REO1_RING_MISC(sc) \
7325	(sc->hw_params.regs->hal_reo1_ring_misc)
7326#define HAL_REO1_RING_HP_ADDR_LSB(sc) \
7327	(sc->hw_params.regs->hal_reo1_ring_hp_addr_lsb)
7328#define HAL_REO1_RING_HP_ADDR_MSB(sc) \
7329	(sc->hw_params.regs->hal_reo1_ring_hp_addr_msb)
7330#define HAL_REO1_RING_PRODUCER_INT_SETUP(sc) \
7331	(sc->hw_params.regs->hal_reo1_ring_producer_int_setup)
7332#define HAL_REO1_RING_MSI1_BASE_LSB(sc) \
7333	(sc->hw_params.regs->hal_reo1_ring_msi1_base_lsb)
7334#define HAL_REO1_RING_MSI1_BASE_MSB(sc) \
7335	(sc->hw_params.regs->hal_reo1_ring_msi1_base_msb)
7336#define HAL_REO1_RING_MSI1_DATA(sc) \
7337	(sc->hw_params.regs->hal_reo1_ring_msi1_data)
7338#define HAL_REO2_RING_BASE_LSB(sc) \
7339	(sc->hw_params.regs->hal_reo2_ring_base)
7340#define HAL_REO1_AGING_THRESH_IX_0(sc) \
7341	(sc->hw_params.regs->hal_reo1_aging_thres_ix0)
7342#define HAL_REO1_AGING_THRESH_IX_1(sc) \
7343	(sc->hw_params.regs->hal_reo1_aging_thres_ix1)
7344#define HAL_REO1_AGING_THRESH_IX_2(sc) \
7345	(sc->hw_params.regs->hal_reo1_aging_thres_ix2)
7346#define HAL_REO1_AGING_THRESH_IX_3(sc) \
7347	(sc->hw_params.regs->hal_reo1_aging_thres_ix3)
7348
7349#define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(sc) \
7350	(HAL_REO1_RING_MSI1_BASE_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
7351#define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(sc) \
7352	(HAL_REO1_RING_MSI1_BASE_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
7353#define HAL_REO1_RING_MSI1_DATA_OFFSET(sc) \
7354	(HAL_REO1_RING_MSI1_DATA(sc) - HAL_REO1_RING_BASE_LSB(sc))
7355#define HAL_REO1_RING_BASE_MSB_OFFSET(sc) \
7356	(HAL_REO1_RING_BASE_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
7357#define HAL_REO1_RING_ID_OFFSET(sc) \
7358	(HAL_REO1_RING_ID(sc) - HAL_REO1_RING_BASE_LSB(sc))
7359#define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(sc) \
7360	(HAL_REO1_RING_PRODUCER_INT_SETUP(sc) - HAL_REO1_RING_BASE_LSB(sc))
7361#define HAL_REO1_RING_HP_ADDR_LSB_OFFSET(sc) \
7362	(HAL_REO1_RING_HP_ADDR_LSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
7363#define HAL_REO1_RING_HP_ADDR_MSB_OFFSET(sc) \
7364	(HAL_REO1_RING_HP_ADDR_MSB(sc) - HAL_REO1_RING_BASE_LSB(sc))
7365#define HAL_REO1_RING_MISC_OFFSET(sc) \
7366	(HAL_REO1_RING_MISC(sc) - HAL_REO1_RING_BASE_LSB(sc))
7367
7368/* REO2SW(x) R2 ring pointers (head/tail) address */
7369#define HAL_REO1_RING_HP			0x00003048
7370#define HAL_REO1_RING_TP			0x0000304c
7371#define HAL_REO2_RING_HP			0x00003050
7372
7373#define HAL_REO1_RING_TP_OFFSET			(HAL_REO1_RING_TP - HAL_REO1_RING_HP)
7374
7375/* REO2SW0 ring configuration address */
7376#define HAL_REO_SW0_RING_BASE_LSB(sc)		\
7377	((sc)->hw_params.regs->hal_reo2_sw0_ring_base)
7378
7379/* REO2SW0 R2 ring pointer (head/tail) address */
7380#define HAL_REO_SW0_RING_HP			0x00003088
7381
7382/* REO CMD R0 address */
7383#define HAL_REO_CMD_RING_BASE_LSB(sc) \
7384	(sc->hw_params.regs->hal_reo_cmd_ring_base)
7385
7386/* REO CMD R2 address */
7387#define HAL_REO_CMD_HP				0x00003020
7388
7389/* SW2REO R0 address */
7390#define HAL_SW2REO_RING_BASE_LSB(sc) \
7391	(sc->hw_params.regs->hal_sw2reo_ring_base)
7392#define HAL_SW2REO1_RING_BASE_LSB(sc) \
7393	(sc->hw_params.regs->hal_sw2reo1_ring_base)
7394
7395/* SW2REO R2 address */
7396#define HAL_SW2REO_RING_HP			0x00003028
7397#define HAL_SW2REO1_RING_HP			0x00003030
7398
7399/* CE ring R0 address */
7400#define HAL_CE_SRC_RING_BASE_LSB		0x00000000
7401#define HAL_CE_DST_RING_BASE_LSB		0x00000000
7402#define HAL_CE_DST_STATUS_RING_BASE_LSB		0x00000058
7403#define HAL_CE_DST_RING_CTRL			0x000000b0
7404
7405/* CE ring R2 address */
7406#define HAL_CE_DST_RING_HP			0x00000400
7407#define HAL_CE_DST_STATUS_RING_HP		0x00000408
7408
7409/* REO status address */
7410#define HAL_REO_STATUS_RING_BASE_LSB(sc) \
7411	(sc->hw_params.regs->hal_reo_status_ring_base)
7412#define HAL_REO_STATUS_HP			0x000030a8
7413
7414/* WBM Idle R0 address */
7415#define HAL_WBM_IDLE_LINK_RING_BASE_LSB(sc) \
7416	(sc->hw_params.regs->hal_wbm_idle_ring_base_lsb)
7417#define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(sc) \
7418	(sc->hw_params.regs->hal_wbm_idle_ring_misc_addr)
7419#define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR(sc) \
7420	(sc->hw_params.regs->hal_wbm_r0_idle_list_cntl_addr)
7421#define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR(sc) \
7422	(sc->hw_params.regs->hal_wbm_r0_idle_list_size_addr)
7423#define HAL_WBM_SCATTERED_RING_BASE_LSB(sc) \
7424	(sc->hw_params.regs->hal_wbm_scattered_ring_base_lsb)
7425#define HAL_WBM_SCATTERED_RING_BASE_MSB(sc) \
7426	(sc->hw_params.regs->hal_wbm_scattered_ring_base_msb)
7427#define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(sc) \
7428	(sc->hw_params.regs->hal_wbm_scattered_desc_head_info_ix0)
7429#define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1(sc) \
7430	(sc->hw_params.regs->hal_wbm_scattered_desc_head_info_ix1)
7431#define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0(sc) \
7432	(sc->hw_params.regs->hal_wbm_scattered_desc_tail_info_ix0)
7433#define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1(sc) \
7434	(sc->hw_params.regs->hal_wbm_scattered_desc_tail_info_ix1)
7435#define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR(sc) \
7436	(sc->hw_params.regs->hal_wbm_scattered_desc_ptr_hp_addr)
7437
7438/* WBM Idle R2 address */
7439#define HAL_WBM_IDLE_LINK_RING_HP		0x000030b8
7440
7441/* SW2WBM R0 release address */
7442#define HAL_WBM_SW_RELEASE_RING_BASE_LSB(sc) \
7443	(sc->hw_params.regs->hal_wbm_sw_release_ring_base_lsb)
7444#define HAL_WBM_SW1_RELEASE_RING_BASE_LSB(sc) \
7445	(sc->hw_params.regs->hal_wbm_sw1_release_ring_base_lsb)
7446
7447/* SW2WBM R2 release address */
7448#define HAL_WBM_SW_RELEASE_RING_HP		0x00003010
7449#define HAL_WBM_SW1_RELEASE_RING_HP		0x00003018
7450
7451/* WBM2SW R0 release address */
7452#define HAL_WBM0_RELEASE_RING_BASE_LSB(sc)	\
7453	(sc->hw_params.regs->hal_wbm0_release_ring_base_lsb)
7454
7455#define HAL_WBM1_RELEASE_RING_BASE_LSB(sc)	\
7456	(sc->hw_params.regs->hal_wbm1_release_ring_base_lsb)
7457
7458/* WBM2SW R2 release address */
7459#define HAL_WBM0_RELEASE_RING_HP		0x000030c8
7460#define HAL_WBM1_RELEASE_RING_HP		0x000030d0
7461
7462/* WBM cookie config address and mask */
7463#define HAL_WBM_SW_COOKIE_CFG0			0x00000040
7464#define HAL_WBM_SW_COOKIE_CFG1			0x00000044
7465#define HAL_WBM_SW_COOKIE_CFG2			0x00000090
7466#define HAL_WBM_SW_COOKIE_CONVERT_CFG		0x00000094
7467
7468#define HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB	GENMASK(7, 0)
7469#define HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB		GENMASK(12, 8)
7470#define HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB		GENMASK(17, 13)
7471#define HAL_WBM_SW_COOKIE_CFG_ALIGN			BIT(18)
7472#define HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN		BIT(0)
7473#define HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN		BIT(1)
7474#define HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN		BIT(3)
7475
7476#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN		BIT(1)
7477#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN		BIT(2)
7478#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN		BIT(3)
7479#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN		BIT(4)
7480#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN		BIT(5)
7481#define HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN		BIT(8)
7482
7483/* TCL ring field mask and offset */
7484#define HAL_TCL1_RING_BASE_MSB_RING_SIZE		GENMASK(27, 8)
7485#define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB	GENMASK(7, 0)
7486#define HAL_TCL1_RING_ID_ENTRY_SIZE			GENMASK(7, 0)
7487#define HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE		BIT(0)
7488#define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE		BIT(1)
7489#define HAL_TCL1_RING_MISC_MSI_SWAP			BIT(3)
7490#define HAL_TCL1_RING_MISC_HOST_FW_SWAP			BIT(4)
7491#define HAL_TCL1_RING_MISC_DATA_TLV_SWAP		BIT(5)
7492#define HAL_TCL1_RING_MISC_SRNG_ENABLE			BIT(6)
7493#define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD   GENMASK(31, 16)
7494#define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0)
7495#define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD	GENMASK(15, 0)
7496#define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE		BIT(8)
7497#define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR		GENMASK(7, 0)
7498#define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN	BIT(23)
7499#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP		GENMASK(31, 0)
7500#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0		GENMASK(2, 0)
7501#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1		GENMASK(5, 3)
7502#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2		GENMASK(8, 6)
7503#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3		GENMASK(11, 9)
7504#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4		GENMASK(14, 12)
7505#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5		GENMASK(17, 15)
7506#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6		GENMASK(20, 18)
7507#define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7		GENMASK(23, 21)
7508
7509/* REO ring field mask and offset */
7510#define HAL_REO1_RING_BASE_MSB_RING_SIZE		GENMASK(27, 8)
7511#define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB	GENMASK(7, 0)
7512#define HAL_REO1_RING_ID_RING_ID			GENMASK(15, 8)
7513#define HAL_REO1_RING_ID_ENTRY_SIZE			GENMASK(7, 0)
7514#define HAL_REO1_RING_MISC_MSI_SWAP			BIT(3)
7515#define HAL_REO1_RING_MISC_HOST_FW_SWAP			BIT(4)
7516#define HAL_REO1_RING_MISC_DATA_TLV_SWAP		BIT(5)
7517#define HAL_REO1_RING_MISC_SRNG_ENABLE			BIT(6)
7518#define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD	GENMASK(31, 16)
7519#define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0)
7520#define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE		BIT(8)
7521#define HAL_REO1_RING_MSI1_BASE_MSB_ADDR		GENMASK(7, 0)
7522#define HAL_REO1_MISC_CTL_FRAG_DST_RING			GENMASK(20, 17)
7523#define HAL_REO1_MISC_CTL_BAR_DST_RING			GENMASK(24, 21)
7524#define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE		BIT(2)
7525#define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE		BIT(3)
7526#define HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB	GENMASK(7, 0)
7527#define HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB		GENMASK(12, 8)
7528#define HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB		GENMASK(17, 13)
7529#define HAL_REO1_SW_COOKIE_CFG_ALIGN			BIT(18)
7530#define HAL_REO1_SW_COOKIE_CFG_ENABLE			BIT(19)
7531#define HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE		BIT(20)
7532
7533/* CE ring bit field mask and shift */
7534#define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN			GENMASK(15, 0)
7535
7536#define HAL_ADDR_LSB_REG_MASK				0xffffffff
7537
7538#define HAL_ADDR_MSB_REG_SHIFT				32
7539
7540/* WBM ring bit field mask and shift */
7541#define HAL_WBM_LINK_DESC_IDLE_LIST_MODE		BIT(1)
7542#define HAL_WBM_SCATTER_BUFFER_SIZE			GENMASK(10, 2)
7543#define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16)
7544#define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32	GENMASK(7, 0)
7545#define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG	GENMASK(31, 8)
7546
7547#define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1	GENMASK(20, 8)
7548#define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1	GENMASK(20, 8)
7549
7550#define HAL_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE		BIT(6)
7551#define HAL_WBM_IDLE_LINK_RING_MISC_RIND_ID_DISABLE	BIT(0)
7552
7553#define BASE_ADDR_MATCH_TAG_VAL 0x5
7554
7555#define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE		0x000fffff
7556#define HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE		0x000fffff
7557#define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE		0x0000ffff
7558#define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE		0x0000ffff
7559#define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE		0x0000ffff
7560#define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE		0x000fffff
7561#define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE		0x000fffff
7562#define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE		0x0000ffff
7563#define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE		0x0000ffff
7564#define HAL_CE_DST_RING_BASE_MSB_RING_SIZE		0x0000ffff
7565#define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE	0x0000ffff
7566#define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE	0x000fffff
7567#define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE	0x0000ffff
7568#define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE	0x000fffff
7569#define HAL_RXDMA_RING_MAX_SIZE				0x0000ffff
7570#define HAL_RXDMA_RING_MAX_SIZE_BE			0x000fffff
7571#define HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE	0x000fffff
7572
7573#define HAL_WBM2SW_REL_ERR_RING_NUM 3
7574
7575#define BUFFER_ADDR_INFO0_ADDR         GENMASK(31, 0)
7576
7577#define BUFFER_ADDR_INFO1_ADDR         GENMASK(7, 0)
7578#define BUFFER_ADDR_INFO1_RET_BUF_MGR  GENMASK(10, 8)
7579#define BUFFER_ADDR_INFO1_SW_COOKIE    GENMASK(31, 11)
7580
7581struct ath12k_buffer_addr {
7582	uint32_t info0;
7583	uint32_t info1;
7584} __packed;
7585
7586/* ath12k_buffer_addr
7587 *
7588 * info0
7589 *		Address (lower 32 bits) of the msdu buffer or msdu extension
7590 *		descriptor or Link descriptor
7591 *
7592 * addr
7593 *		Address (upper 8 bits) of the msdu buffer or msdu extension
7594 *		descriptor or Link descriptor
7595 *
7596 * return_buffer_manager (RBM)
7597 *		Consumer: WBM
7598 *		Producer: SW/FW
7599 *		Indicates to which buffer manager the buffer or MSDU_EXTENSION
7600 *		descriptor or link descriptor that is being pointed to shall be
7601 *		returned after the frame has been processed. It is used by WBM
7602 *		for routing purposes.
7603 *
7604 *		Values are defined in enum %HAL_RX_BUF_RBM_
7605 *
7606 * sw_buffer_cookie
7607 *		Cookie field exclusively used by SW. HW ignores the contents,
7608 *		accept that it passes the programmed value on to other
7609 *		descriptors together with the physical address.
7610 *
7611 *		Field can be used by SW to for example associate the buffers
7612 *		physical address with the virtual address.
7613 */
7614
7615enum hal_tlv_tag {
7616	HAL_MACTX_CBF_START                    =   0 /* 0x0 */,
7617	HAL_PHYRX_DATA                         =   1 /* 0x1 */,
7618	HAL_PHYRX_CBF_DATA_RESP                =   2 /* 0x2 */,
7619	HAL_PHYRX_ABORT_REQUEST                =   3 /* 0x3 */,
7620	HAL_PHYRX_USER_ABORT_NOTIFICATION      =   4 /* 0x4 */,
7621	HAL_MACTX_DATA_RESP                    =   5 /* 0x5 */,
7622	HAL_MACTX_CBF_DATA                     =   6 /* 0x6 */,
7623	HAL_MACTX_CBF_DONE                     =   7 /* 0x7 */,
7624	HAL_MACRX_CBF_READ_REQUEST             =   8 /* 0x8 */,
7625	HAL_MACRX_CBF_DATA_REQUEST             =   9 /* 0x9 */,
7626	HAL_MACRX_EXPECT_NDP_RECEPTION         =  10 /* 0xa */,
7627	HAL_MACRX_FREEZE_CAPTURE_CHANNEL       =  11 /* 0xb */,
7628	HAL_MACRX_NDP_TIMEOUT                  =  12 /* 0xc */,
7629	HAL_MACRX_ABORT_ACK                    =  13 /* 0xd */,
7630	HAL_MACRX_REQ_IMPLICIT_FB              =  14 /* 0xe */,
7631	HAL_MACRX_CHAIN_MASK                   =  15 /* 0xf */,
7632	HAL_MACRX_NAP_USER                     =  16 /* 0x10 */,
7633	HAL_MACRX_ABORT_REQUEST                =  17 /* 0x11 */,
7634	HAL_PHYTX_OTHER_TRANSMIT_INFO16        =  18 /* 0x12 */,
7635	HAL_PHYTX_ABORT_ACK                    =  19 /* 0x13 */,
7636	HAL_PHYTX_ABORT_REQUEST                =  20 /* 0x14 */,
7637	HAL_PHYTX_PKT_END                      =  21 /* 0x15 */,
7638	HAL_PHYTX_PPDU_HEADER_INFO_REQUEST     =  22 /* 0x16 */,
7639	HAL_PHYTX_REQUEST_CTRL_INFO            =  23 /* 0x17 */,
7640	HAL_PHYTX_DATA_REQUEST                 =  24 /* 0x18 */,
7641	HAL_PHYTX_BF_CV_LOADING_DONE           =  25 /* 0x19 */,
7642	HAL_PHYTX_NAP_ACK                      =  26 /* 0x1a */,
7643	HAL_PHYTX_NAP_DONE                     =  27 /* 0x1b */,
7644	HAL_PHYTX_OFF_ACK                      =  28 /* 0x1c */,
7645	HAL_PHYTX_ON_ACK                       =  29 /* 0x1d */,
7646	HAL_PHYTX_SYNTH_OFF_ACK                =  30 /* 0x1e */,
7647	HAL_PHYTX_DEBUG16                      =  31 /* 0x1f */,
7648	HAL_MACTX_ABORT_REQUEST                =  32 /* 0x20 */,
7649	HAL_MACTX_ABORT_ACK                    =  33 /* 0x21 */,
7650	HAL_MACTX_PKT_END                      =  34 /* 0x22 */,
7651	HAL_MACTX_PRE_PHY_DESC                 =  35 /* 0x23 */,
7652	HAL_MACTX_BF_PARAMS_COMMON             =  36 /* 0x24 */,
7653	HAL_MACTX_BF_PARAMS_PER_USER           =  37 /* 0x25 */,
7654	HAL_MACTX_PREFETCH_CV                  =  38 /* 0x26 */,
7655	HAL_MACTX_USER_DESC_COMMON             =  39 /* 0x27 */,
7656	HAL_MACTX_USER_DESC_PER_USER           =  40 /* 0x28 */,
7657	HAL_EXAMPLE_USER_TLV_16                =  41 /* 0x29 */,
7658	HAL_EXAMPLE_TLV_16                     =  42 /* 0x2a */,
7659	HAL_MACTX_PHY_OFF                      =  43 /* 0x2b */,
7660	HAL_MACTX_PHY_ON                       =  44 /* 0x2c */,
7661	HAL_MACTX_SYNTH_OFF                    =  45 /* 0x2d */,
7662	HAL_MACTX_EXPECT_CBF_COMMON            =  46 /* 0x2e */,
7663	HAL_MACTX_EXPECT_CBF_PER_USER          =  47 /* 0x2f */,
7664	HAL_MACTX_PHY_DESC                     =  48 /* 0x30 */,
7665	HAL_MACTX_L_SIG_A                      =  49 /* 0x31 */,
7666	HAL_MACTX_L_SIG_B                      =  50 /* 0x32 */,
7667	HAL_MACTX_HT_SIG                       =  51 /* 0x33 */,
7668	HAL_MACTX_VHT_SIG_A                    =  52 /* 0x34 */,
7669	HAL_MACTX_VHT_SIG_B_SU20               =  53 /* 0x35 */,
7670	HAL_MACTX_VHT_SIG_B_SU40               =  54 /* 0x36 */,
7671	HAL_MACTX_VHT_SIG_B_SU80               =  55 /* 0x37 */,
7672	HAL_MACTX_VHT_SIG_B_SU160              =  56 /* 0x38 */,
7673	HAL_MACTX_VHT_SIG_B_MU20               =  57 /* 0x39 */,
7674	HAL_MACTX_VHT_SIG_B_MU40               =  58 /* 0x3a */,
7675	HAL_MACTX_VHT_SIG_B_MU80               =  59 /* 0x3b */,
7676	HAL_MACTX_VHT_SIG_B_MU160              =  60 /* 0x3c */,
7677	HAL_MACTX_SERVICE                      =  61 /* 0x3d */,
7678	HAL_MACTX_HE_SIG_A_SU                  =  62 /* 0x3e */,
7679	HAL_MACTX_HE_SIG_A_MU_DL               =  63 /* 0x3f */,
7680	HAL_MACTX_HE_SIG_A_MU_UL               =  64 /* 0x40 */,
7681	HAL_MACTX_HE_SIG_B1_MU                 =  65 /* 0x41 */,
7682	HAL_MACTX_HE_SIG_B2_MU                 =  66 /* 0x42 */,
7683	HAL_MACTX_HE_SIG_B2_OFDMA              =  67 /* 0x43 */,
7684	HAL_MACTX_DELETE_CV                    =  68 /* 0x44 */,
7685	HAL_MACTX_MU_UPLINK_COMMON             =  69 /* 0x45 */,
7686	HAL_MACTX_MU_UPLINK_USER_SETUP         =  70 /* 0x46 */,
7687	HAL_MACTX_OTHER_TRANSMIT_INFO          =  71 /* 0x47 */,
7688	HAL_MACTX_PHY_NAP                      =  72 /* 0x48 */,
7689	HAL_MACTX_DEBUG                        =  73 /* 0x49 */,
7690	HAL_PHYRX_ABORT_ACK                    =  74 /* 0x4a */,
7691	HAL_PHYRX_GENERATED_CBF_DETAILS        =  75 /* 0x4b */,
7692	HAL_PHYRX_RSSI_LEGACY                  =  76 /* 0x4c */,
7693	HAL_PHYRX_RSSI_HT                      =  77 /* 0x4d */,
7694	HAL_PHYRX_USER_INFO                    =  78 /* 0x4e */,
7695	HAL_PHYRX_PKT_END                      =  79 /* 0x4f */,
7696	HAL_PHYRX_DEBUG                        =  80 /* 0x50 */,
7697	HAL_PHYRX_CBF_TRANSFER_DONE            =  81 /* 0x51 */,
7698	HAL_PHYRX_CBF_TRANSFER_ABORT           =  82 /* 0x52 */,
7699	HAL_PHYRX_L_SIG_A                      =  83 /* 0x53 */,
7700	HAL_PHYRX_L_SIG_B                      =  84 /* 0x54 */,
7701	HAL_PHYRX_HT_SIG                       =  85 /* 0x55 */,
7702	HAL_PHYRX_VHT_SIG_A                    =  86 /* 0x56 */,
7703	HAL_PHYRX_VHT_SIG_B_SU20               =  87 /* 0x57 */,
7704	HAL_PHYRX_VHT_SIG_B_SU40               =  88 /* 0x58 */,
7705	HAL_PHYRX_VHT_SIG_B_SU80               =  89 /* 0x59 */,
7706	HAL_PHYRX_VHT_SIG_B_SU160              =  90 /* 0x5a */,
7707	HAL_PHYRX_VHT_SIG_B_MU20               =  91 /* 0x5b */,
7708	HAL_PHYRX_VHT_SIG_B_MU40               =  92 /* 0x5c */,
7709	HAL_PHYRX_VHT_SIG_B_MU80               =  93 /* 0x5d */,
7710	HAL_PHYRX_VHT_SIG_B_MU160              =  94 /* 0x5e */,
7711	HAL_PHYRX_HE_SIG_A_SU                  =  95 /* 0x5f */,
7712	HAL_PHYRX_HE_SIG_A_MU_DL               =  96 /* 0x60 */,
7713	HAL_PHYRX_HE_SIG_A_MU_UL               =  97 /* 0x61 */,
7714	HAL_PHYRX_HE_SIG_B1_MU                 =  98 /* 0x62 */,
7715	HAL_PHYRX_HE_SIG_B2_MU                 =  99 /* 0x63 */,
7716	HAL_PHYRX_HE_SIG_B2_OFDMA              = 100 /* 0x64 */,
7717	HAL_PHYRX_OTHER_RECEIVE_INFO           = 101 /* 0x65 */,
7718	HAL_PHYRX_COMMON_USER_INFO             = 102 /* 0x66 */,
7719	HAL_PHYRX_DATA_DONE                    = 103 /* 0x67 */,
7720	HAL_RECEIVE_RSSI_INFO                  = 104 /* 0x68 */,
7721	HAL_RECEIVE_USER_INFO                  = 105 /* 0x69 */,
7722	HAL_MIMO_CONTROL_INFO                  = 106 /* 0x6a */,
7723	HAL_RX_LOCATION_INFO                   = 107 /* 0x6b */,
7724	HAL_COEX_TX_REQ                        = 108 /* 0x6c */,
7725	HAL_DUMMY                              = 109 /* 0x6d */,
7726	HAL_RX_TIMING_OFFSET_INFO              = 110 /* 0x6e */,
7727	HAL_EXAMPLE_TLV_32_NAME                = 111 /* 0x6f */,
7728	HAL_MPDU_LIMIT                         = 112 /* 0x70 */,
7729	HAL_NA_LENGTH_END                      = 113 /* 0x71 */,
7730	HAL_OLE_BUF_STATUS                     = 114 /* 0x72 */,
7731	HAL_PCU_PPDU_SETUP_DONE                = 115 /* 0x73 */,
7732	HAL_PCU_PPDU_SETUP_END                 = 116 /* 0x74 */,
7733	HAL_PCU_PPDU_SETUP_INIT                = 117 /* 0x75 */,
7734	HAL_PCU_PPDU_SETUP_START               = 118 /* 0x76 */,
7735	HAL_PDG_FES_SETUP                      = 119 /* 0x77 */,
7736	HAL_PDG_RESPONSE                       = 120 /* 0x78 */,
7737	HAL_PDG_TX_REQ                         = 121 /* 0x79 */,
7738	HAL_SCH_WAIT_INSTR                     = 122 /* 0x7a */,
7739	HAL_SCHEDULER_TLV                      = 123 /* 0x7b */,
7740	HAL_TQM_FLOW_EMPTY_STATUS              = 124 /* 0x7c */,
7741	HAL_TQM_FLOW_NOT_EMPTY_STATUS          = 125 /* 0x7d */,
7742	HAL_TQM_GEN_MPDU_LENGTH_LIST           = 126 /* 0x7e */,
7743	HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS    = 127 /* 0x7f */,
7744	HAL_TQM_GEN_MPDUS                      = 128 /* 0x80 */,
7745	HAL_TQM_GEN_MPDUS_STATUS               = 129 /* 0x81 */,
7746	HAL_TQM_REMOVE_MPDU                    = 130 /* 0x82 */,
7747	HAL_TQM_REMOVE_MPDU_STATUS             = 131 /* 0x83 */,
7748	HAL_TQM_REMOVE_MSDU                    = 132 /* 0x84 */,
7749	HAL_TQM_REMOVE_MSDU_STATUS             = 133 /* 0x85 */,
7750	HAL_TQM_UPDATE_TX_MPDU_COUNT           = 134 /* 0x86 */,
7751	HAL_TQM_WRITE_CMD                      = 135 /* 0x87 */,
7752	HAL_OFDMA_TRIGGER_DETAILS              = 136 /* 0x88 */,
7753	HAL_TX_DATA                            = 137 /* 0x89 */,
7754	HAL_TX_FES_SETUP                       = 138 /* 0x8a */,
7755	HAL_RX_PACKET                          = 139 /* 0x8b */,
7756	HAL_EXPECTED_RESPONSE                  = 140 /* 0x8c */,
7757	HAL_TX_MPDU_END                        = 141 /* 0x8d */,
7758	HAL_TX_MPDU_START                      = 142 /* 0x8e */,
7759	HAL_TX_MSDU_END                        = 143 /* 0x8f */,
7760	HAL_TX_MSDU_START                      = 144 /* 0x90 */,
7761	HAL_TX_SW_MODE_SETUP                   = 145 /* 0x91 */,
7762	HAL_TXPCU_BUFFER_STATUS                = 146 /* 0x92 */,
7763	HAL_TXPCU_USER_BUFFER_STATUS           = 147 /* 0x93 */,
7764	HAL_DATA_TO_TIME_CONFIG                = 148 /* 0x94 */,
7765	HAL_EXAMPLE_USER_TLV_32                = 149 /* 0x95 */,
7766	HAL_MPDU_INFO                          = 150 /* 0x96 */,
7767	HAL_PDG_USER_SETUP                     = 151 /* 0x97 */,
7768	HAL_TX_11AH_SETUP                      = 152 /* 0x98 */,
7769	HAL_REO_UPDATE_RX_REO_QUEUE_STATUS     = 153 /* 0x99 */,
7770	HAL_TX_PEER_ENTRY                      = 154 /* 0x9a */,
7771	HAL_TX_RAW_OR_NATIVE_FRAME_SETUP       = 155 /* 0x9b */,
7772	HAL_EXAMPLE_STRUCT_NAME                = 156 /* 0x9c */,
7773	HAL_PCU_PPDU_SETUP_END_INFO            = 157 /* 0x9d */,
7774	HAL_PPDU_RATE_SETTING                  = 158 /* 0x9e */,
7775	HAL_PROT_RATE_SETTING                  = 159 /* 0x9f */,
7776	HAL_RX_MPDU_DETAILS                    = 160 /* 0xa0 */,
7777	HAL_EXAMPLE_USER_TLV_42                = 161 /* 0xa1 */,
7778	HAL_RX_MSDU_LINK                       = 162 /* 0xa2 */,
7779	HAL_RX_REO_QUEUE                       = 163 /* 0xa3 */,
7780	HAL_ADDR_SEARCH_ENTRY                  = 164 /* 0xa4 */,
7781	HAL_SCHEDULER_CMD                      = 165 /* 0xa5 */,
7782	HAL_TX_FLUSH                           = 166 /* 0xa6 */,
7783	HAL_TQM_ENTRANCE_RING                  = 167 /* 0xa7 */,
7784	HAL_TX_DATA_WORD                       = 168 /* 0xa8 */,
7785	HAL_TX_MPDU_DETAILS                    = 169 /* 0xa9 */,
7786	HAL_TX_MPDU_LINK                       = 170 /* 0xaa */,
7787	HAL_TX_MPDU_LINK_PTR                   = 171 /* 0xab */,
7788	HAL_TX_MPDU_QUEUE_HEAD                 = 172 /* 0xac */,
7789	HAL_TX_MPDU_QUEUE_EXT                  = 173 /* 0xad */,
7790	HAL_TX_MPDU_QUEUE_EXT_PTR              = 174 /* 0xae */,
7791	HAL_TX_MSDU_DETAILS                    = 175 /* 0xaf */,
7792	HAL_TX_MSDU_EXTENSION                  = 176 /* 0xb0 */,
7793	HAL_TX_MSDU_FLOW                       = 177 /* 0xb1 */,
7794	HAL_TX_MSDU_LINK                       = 178 /* 0xb2 */,
7795	HAL_TX_MSDU_LINK_ENTRY_PTR             = 179 /* 0xb3 */,
7796	HAL_RESPONSE_RATE_SETTING              = 180 /* 0xb4 */,
7797	HAL_TXPCU_BUFFER_BASICS                = 181 /* 0xb5 */,
7798	HAL_UNIFORM_DESCRIPTOR_HEADER          = 182 /* 0xb6 */,
7799	HAL_UNIFORM_TQM_CMD_HEADER             = 183 /* 0xb7 */,
7800	HAL_UNIFORM_TQM_STATUS_HEADER          = 184 /* 0xb8 */,
7801	HAL_USER_RATE_SETTING                  = 185 /* 0xb9 */,
7802	HAL_WBM_BUFFER_RING                    = 186 /* 0xba */,
7803	HAL_WBM_LINK_DESCRIPTOR_RING           = 187 /* 0xbb */,
7804	HAL_WBM_RELEASE_RING                   = 188 /* 0xbc */,
7805	HAL_TX_FLUSH_REQ                       = 189 /* 0xbd */,
7806	HAL_RX_MSDU_DETAILS                    = 190 /* 0xbe */,
7807	HAL_TQM_WRITE_CMD_STATUS               = 191 /* 0xbf */,
7808	HAL_TQM_GET_MPDU_QUEUE_STATS           = 192 /* 0xc0 */,
7809	HAL_TQM_GET_MSDU_FLOW_STATS            = 193 /* 0xc1 */,
7810	HAL_EXAMPLE_USER_CTLV_32               = 194 /* 0xc2 */,
7811	HAL_TX_FES_STATUS_START                = 195 /* 0xc3 */,
7812	HAL_TX_FES_STATUS_USER_PPDU            = 196 /* 0xc4 */,
7813	HAL_TX_FES_STATUS_USER_RESPONSE        = 197 /* 0xc5 */,
7814	HAL_TX_FES_STATUS_END                  = 198 /* 0xc6 */,
7815	HAL_RX_TRIG_INFO                       = 199 /* 0xc7 */,
7816	HAL_RXPCU_TX_SETUP_CLEAR               = 200 /* 0xc8 */,
7817	HAL_RX_FRAME_BITMAP_REQ                = 201 /* 0xc9 */,
7818	HAL_RX_FRAME_BITMAP_ACK                = 202 /* 0xca */,
7819	HAL_COEX_RX_STATUS                     = 203 /* 0xcb */,
7820	HAL_RX_START_PARAM                     = 204 /* 0xcc */,
7821	HAL_RX_PPDU_START                      = 205 /* 0xcd */,
7822	HAL_RX_PPDU_END                        = 206 /* 0xce */,
7823	HAL_RX_MPDU_START                      = 207 /* 0xcf */,
7824	HAL_RX_MPDU_END                        = 208 /* 0xd0 */,
7825	HAL_RX_MSDU_START                      = 209 /* 0xd1 */,
7826	HAL_RX_MSDU_END                        = 210 /* 0xd2 */,
7827	HAL_RX_ATTENTION                       = 211 /* 0xd3 */,
7828	HAL_RECEIVED_RESPONSE_INFO             = 212 /* 0xd4 */,
7829	HAL_RX_PHY_SLEEP                       = 213 /* 0xd5 */,
7830	HAL_RX_HEADER                          = 214 /* 0xd6 */,
7831	HAL_RX_PEER_ENTRY                      = 215 /* 0xd7 */,
7832	HAL_RX_FLUSH                           = 216 /* 0xd8 */,
7833	HAL_RX_RESPONSE_REQUIRED_INFO          = 217 /* 0xd9 */,
7834	HAL_RX_FRAMELESS_BAR_DETAILS           = 218 /* 0xda */,
7835	HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS    = 219 /* 0xdb */,
7836	HAL_TQM_GET_MSDU_FLOW_STATS_STATUS     = 220 /* 0xdc */,
7837	HAL_TX_CBF_INFO                        = 221 /* 0xdd */,
7838	HAL_PCU_PPDU_SETUP_USER                = 222 /* 0xde */,
7839	HAL_RX_MPDU_PCU_START                  = 223 /* 0xdf */,
7840	HAL_RX_PM_INFO                         = 224 /* 0xe0 */,
7841	HAL_RX_USER_PPDU_END                   = 225 /* 0xe1 */,
7842	HAL_RX_PRE_PPDU_START                  = 226 /* 0xe2 */,
7843	HAL_RX_PREAMBLE                        = 227 /* 0xe3 */,
7844	HAL_TX_FES_SETUP_COMPLETE              = 228 /* 0xe4 */,
7845	HAL_TX_LAST_MPDU_FETCHED               = 229 /* 0xe5 */,
7846	HAL_TXDMA_STOP_REQUEST                 = 230 /* 0xe6 */,
7847	HAL_RXPCU_SETUP                        = 231 /* 0xe7 */,
7848	HAL_RXPCU_USER_SETUP                   = 232 /* 0xe8 */,
7849	HAL_TX_FES_STATUS_ACK_OR_BA            = 233 /* 0xe9 */,
7850	HAL_TQM_ACKED_MPDU                     = 234 /* 0xea */,
7851	HAL_COEX_TX_RESP                       = 235 /* 0xeb */,
7852	HAL_COEX_TX_STATUS                     = 236 /* 0xec */,
7853	HAL_MACTX_COEX_PHY_CTRL                = 237 /* 0xed */,
7854	HAL_COEX_STATUS_BROADCAST              = 238 /* 0xee */,
7855	HAL_RESPONSE_START_STATUS              = 239 /* 0xef */,
7856	HAL_RESPONSE_END_STATUS                = 240 /* 0xf0 */,
7857	HAL_CRYPTO_STATUS                      = 241 /* 0xf1 */,
7858	HAL_RECEIVED_TRIGGER_INFO              = 242 /* 0xf2 */,
7859	HAL_REO_ENTRANCE_RING                  = 243 /* 0xf3 */,
7860	HAL_RX_MPDU_LINK                       = 244 /* 0xf4 */,
7861	HAL_COEX_TX_STOP_CTRL                  = 245 /* 0xf5 */,
7862	HAL_RX_PPDU_ACK_REPORT                 = 246 /* 0xf6 */,
7863	HAL_RX_PPDU_NO_ACK_REPORT              = 247 /* 0xf7 */,
7864	HAL_SCH_COEX_STATUS                    = 248 /* 0xf8 */,
7865	HAL_SCHEDULER_COMMAND_STATUS           = 249 /* 0xf9 */,
7866	HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 250 /* 0xfa */,
7867	HAL_TX_FES_STATUS_PROT                 = 251 /* 0xfb */,
7868	HAL_TX_FES_STATUS_START_PPDU           = 252 /* 0xfc */,
7869	HAL_TX_FES_STATUS_START_PROT           = 253 /* 0xfd */,
7870	HAL_TXPCU_PHYTX_DEBUG32                = 254 /* 0xfe */,
7871	HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32  = 255 /* 0xff */,
7872	HAL_TX_MPDU_COUNT_TRANSFER_END         = 256 /* 0x100 */,
7873	HAL_WHO_ANCHOR_OFFSET                  = 257 /* 0x101 */,
7874	HAL_WHO_ANCHOR_VALUE                   = 258 /* 0x102 */,
7875	HAL_WHO_CCE_INFO                       = 259 /* 0x103 */,
7876	HAL_WHO_COMMIT                         = 260 /* 0x104 */,
7877	HAL_WHO_COMMIT_DONE                    = 261 /* 0x105 */,
7878	HAL_WHO_FLUSH                          = 262 /* 0x106 */,
7879	HAL_WHO_L2_LLC                         = 263 /* 0x107 */,
7880	HAL_WHO_L2_PAYLOAD                     = 264 /* 0x108 */,
7881	HAL_WHO_L3_CHECKSUM                    = 265 /* 0x109 */,
7882	HAL_WHO_L3_INFO                        = 266 /* 0x10a */,
7883	HAL_WHO_L4_CHECKSUM                    = 267 /* 0x10b */,
7884	HAL_WHO_L4_INFO                        = 268 /* 0x10c */,
7885	HAL_WHO_MSDU                           = 269 /* 0x10d */,
7886	HAL_WHO_MSDU_MISC                      = 270 /* 0x10e */,
7887	HAL_WHO_PACKET_DATA                    = 271 /* 0x10f */,
7888	HAL_WHO_PACKET_HDR                     = 272 /* 0x110 */,
7889	HAL_WHO_PPDU_END                       = 273 /* 0x111 */,
7890	HAL_WHO_PPDU_START                     = 274 /* 0x112 */,
7891	HAL_WHO_TSO                            = 275 /* 0x113 */,
7892	HAL_WHO_WMAC_HEADER_PV0                = 276 /* 0x114 */,
7893	HAL_WHO_WMAC_HEADER_PV1                = 277 /* 0x115 */,
7894	HAL_WHO_WMAC_IV                        = 278 /* 0x116 */,
7895	HAL_MPDU_INFO_END                      = 279 /* 0x117 */,
7896	HAL_MPDU_INFO_BITMAP                   = 280 /* 0x118 */,
7897	HAL_TX_QUEUE_EXTENSION                 = 281 /* 0x119 */,
7898	HAL_RX_PEER_ENTRY_DETAILS              = 282 /* 0x11a */,
7899	HAL_RX_REO_QUEUE_REFERENCE             = 283 /* 0x11b */,
7900	HAL_RX_REO_QUEUE_EXT                   = 284 /* 0x11c */,
7901	HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS  = 285 /* 0x11d */,
7902	HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS    = 286 /* 0x11e */,
7903	HAL_TQM_ACKED_MPDU_STATUS              = 287 /* 0x11f */,
7904	HAL_TQM_ADD_MSDU_STATUS                = 288 /* 0x120 */,
7905	HAL_RX_MPDU_LINK_PTR                   = 289 /* 0x121 */,
7906	HAL_REO_DESTINATION_RING               = 290 /* 0x122 */,
7907	HAL_TQM_LIST_GEN_DONE                  = 291 /* 0x123 */,
7908	HAL_WHO_TERMINATE                      = 292 /* 0x124 */,
7909	HAL_TX_LAST_MPDU_END                   = 293 /* 0x125 */,
7910	HAL_TX_CV_DATA                         = 294 /* 0x126 */,
7911	HAL_TCL_ENTRANCE_FROM_PPE_RING         = 295 /* 0x127 */,
7912	HAL_PPDU_TX_END                        = 296 /* 0x128 */,
7913	HAL_PROT_TX_END                        = 297 /* 0x129 */,
7914	HAL_PDG_RESPONSE_RATE_SETTING          = 298 /* 0x12a */,
7915	HAL_MPDU_INFO_GLOBAL_END               = 299 /* 0x12b */,
7916	HAL_TQM_SCH_INSTR_GLOBAL_END           = 300 /* 0x12c */,
7917	HAL_RX_PPDU_END_USER_STATS             = 301 /* 0x12d */,
7918	HAL_RX_PPDU_END_USER_STATS_EXT         = 302 /* 0x12e */,
7919	HAL_NO_ACK_REPORT                      = 303 /* 0x12f */,
7920	HAL_ACK_REPORT                         = 304 /* 0x130 */,
7921	HAL_UNIFORM_REO_CMD_HEADER             = 305 /* 0x131 */,
7922	HAL_REO_GET_QUEUE_STATS                = 306 /* 0x132 */,
7923	HAL_REO_FLUSH_QUEUE                    = 307 /* 0x133 */,
7924	HAL_REO_FLUSH_CACHE                    = 308 /* 0x134 */,
7925	HAL_REO_UNBLOCK_CACHE                  = 309 /* 0x135 */,
7926	HAL_UNIFORM_REO_STATUS_HEADER          = 310 /* 0x136 */,
7927	HAL_REO_GET_QUEUE_STATS_STATUS         = 311 /* 0x137 */,
7928	HAL_REO_FLUSH_QUEUE_STATUS             = 312 /* 0x138 */,
7929	HAL_REO_FLUSH_CACHE_STATUS             = 313 /* 0x139 */,
7930	HAL_REO_UNBLOCK_CACHE_STATUS           = 314 /* 0x13a */,
7931	HAL_TQM_FLUSH_CACHE                    = 315 /* 0x13b */,
7932	HAL_TQM_UNBLOCK_CACHE                  = 316 /* 0x13c */,
7933	HAL_TQM_FLUSH_CACHE_STATUS             = 317 /* 0x13d */,
7934	HAL_TQM_UNBLOCK_CACHE_STATUS           = 318 /* 0x13e */,
7935	HAL_RX_PPDU_END_STATUS_DONE            = 319 /* 0x13f */,
7936	HAL_RX_STATUS_BUFFER_DONE              = 320 /* 0x140 */,
7937	HAL_BUFFER_ADDR_INFO                   = 321 /* 0x141 */,
7938	HAL_RX_MSDU_DESC_INFO                  = 322 /* 0x142 */,
7939	HAL_RX_MPDU_DESC_INFO                  = 323 /* 0x143 */,
7940	HAL_TCL_DATA_CMD                       = 324 /* 0x144 */,
7941	HAL_TCL_GSE_CMD                        = 325 /* 0x145 */,
7942	HAL_TCL_EXIT_BASE                      = 326 /* 0x146 */,
7943	HAL_TCL_COMPACT_EXIT_RING              = 327 /* 0x147 */,
7944	HAL_TCL_REGULAR_EXIT_RING              = 328 /* 0x148 */,
7945	HAL_TCL_EXTENDED_EXIT_RING             = 329 /* 0x149 */,
7946	HAL_UPLINK_COMMON_INFO                 = 330 /* 0x14a */,
7947	HAL_UPLINK_USER_SETUP_INFO             = 331 /* 0x14b */,
7948	HAL_TX_DATA_SYNC                       = 332 /* 0x14c */,
7949	HAL_PHYRX_CBF_READ_REQUEST_ACK         = 333 /* 0x14d */,
7950	HAL_TCL_STATUS_RING                    = 334 /* 0x14e */,
7951	HAL_TQM_GET_MPDU_HEAD_INFO             = 335 /* 0x14f */,
7952	HAL_TQM_SYNC_CMD                       = 336 /* 0x150 */,
7953	HAL_TQM_GET_MPDU_HEAD_INFO_STATUS      = 337 /* 0x151 */,
7954	HAL_TQM_SYNC_CMD_STATUS                = 338 /* 0x152 */,
7955	HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 339 /* 0x153 */,
7956	HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 340 /* 0x154 */,
7957	HAL_REO_FLUSH_TIMEOUT_LIST             = 341 /* 0x155 */,
7958	HAL_REO_FLUSH_TIMEOUT_LIST_STATUS      = 342 /* 0x156 */,
7959	HAL_REO_TO_PPE_RING                    = 343 /* 0x157 */,
7960	HAL_RX_MPDU_INFO                       = 344 /* 0x158 */,
7961	HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 345 /* 0x159 */,
7962	HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 346 /* 0x15a */,
7963	HAL_EXAMPLE_USER_TLV_32_NAME           = 347 /* 0x15b */,
7964	HAL_RX_PPDU_START_USER_INFO            = 348 /* 0x15c */,
7965	HAL_RX_RXPCU_CLASSIFICATION_OVERVIEW   = 349 /* 0x15d */,
7966	HAL_RX_RING_MASK                       = 350 /* 0x15e */,
7967	HAL_WHO_CLASSIFY_INFO                  = 351 /* 0x15f */,
7968	HAL_TXPT_CLASSIFY_INFO                 = 352 /* 0x160 */,
7969	HAL_RXPT_CLASSIFY_INFO                 = 353 /* 0x161 */,
7970	HAL_TX_FLOW_SEARCH_ENTRY               = 354 /* 0x162 */,
7971	HAL_RX_FLOW_SEARCH_ENTRY               = 355 /* 0x163 */,
7972	HAL_RECEIVED_TRIGGER_INFO_DETAILS      = 356 /* 0x164 */,
7973	HAL_COEX_MAC_NAP                       = 357 /* 0x165 */,
7974	HAL_MACRX_ABORT_REQUEST_INFO           = 358 /* 0x166 */,
7975	HAL_MACTX_ABORT_REQUEST_INFO           = 359 /* 0x167 */,
7976	HAL_PHYRX_ABORT_REQUEST_INFO           = 360 /* 0x168 */,
7977	HAL_PHYTX_ABORT_REQUEST_INFO           = 361 /* 0x169 */,
7978	HAL_RXPCU_PPDU_END_INFO                = 362 /* 0x16a */,
7979	HAL_WHO_MESH_CONTROL                   = 363 /* 0x16b */,
7980	HAL_L_SIG_A_INFO                       = 364 /* 0x16c */,
7981	HAL_L_SIG_B_INFO                       = 365 /* 0x16d */,
7982	HAL_HT_SIG_INFO                        = 366 /* 0x16e */,
7983	HAL_VHT_SIG_A_INFO                     = 367 /* 0x16f */,
7984	HAL_VHT_SIG_B_SU20_INFO                = 368 /* 0x170 */,
7985	HAL_VHT_SIG_B_SU40_INFO                = 369 /* 0x171 */,
7986	HAL_VHT_SIG_B_SU80_INFO                = 370 /* 0x172 */,
7987	HAL_VHT_SIG_B_SU160_INFO               = 371 /* 0x173 */,
7988	HAL_VHT_SIG_B_MU20_INFO                = 372 /* 0x174 */,
7989	HAL_VHT_SIG_B_MU40_INFO                = 373 /* 0x175 */,
7990	HAL_VHT_SIG_B_MU80_INFO                = 374 /* 0x176 */,
7991	HAL_VHT_SIG_B_MU160_INFO               = 375 /* 0x177 */,
7992	HAL_SERVICE_INFO                       = 376 /* 0x178 */,
7993	HAL_HE_SIG_A_SU_INFO                   = 377 /* 0x179 */,
7994	HAL_HE_SIG_A_MU_DL_INFO                = 378 /* 0x17a */,
7995	HAL_HE_SIG_A_MU_UL_INFO                = 379 /* 0x17b */,
7996	HAL_HE_SIG_B1_MU_INFO                  = 380 /* 0x17c */,
7997	HAL_HE_SIG_B2_MU_INFO                  = 381 /* 0x17d */,
7998	HAL_HE_SIG_B2_OFDMA_INFO               = 382 /* 0x17e */,
7999	HAL_PDG_SW_MODE_BW_START               = 383 /* 0x17f */,
8000	HAL_PDG_SW_MODE_BW_END                 = 384 /* 0x180 */,
8001	HAL_PDG_WAIT_FOR_MAC_REQUEST           = 385 /* 0x181 */,
8002	HAL_PDG_WAIT_FOR_PHY_REQUEST           = 386 /* 0x182 */,
8003	HAL_SCHEDULER_END                      = 387 /* 0x183 */,
8004	HAL_PEER_TABLE_ENTRY                   = 388 /* 0x184 */,
8005	HAL_SW_PEER_INFO                       = 389 /* 0x185 */,
8006	HAL_RXOLE_CCE_CLASSIFY_INFO            = 390 /* 0x186 */,
8007	HAL_TCL_CCE_CLASSIFY_INFO              = 391 /* 0x187 */,
8008	HAL_RXOLE_CCE_INFO                     = 392 /* 0x188 */,
8009	HAL_TCL_CCE_INFO                       = 393 /* 0x189 */,
8010	HAL_TCL_CCE_SUPERRULE                  = 394 /* 0x18a */,
8011	HAL_CCE_RULE                           = 395 /* 0x18b */,
8012	HAL_RX_PPDU_START_DROPPED              = 396 /* 0x18c */,
8013	HAL_RX_PPDU_END_DROPPED                = 397 /* 0x18d */,
8014	HAL_RX_PPDU_END_STATUS_DONE_DROPPED    = 398 /* 0x18e */,
8015	HAL_RX_MPDU_START_DROPPED              = 399 /* 0x18f */,
8016	HAL_RX_MSDU_START_DROPPED              = 400 /* 0x190 */,
8017	HAL_RX_MSDU_END_DROPPED                = 401 /* 0x191 */,
8018	HAL_RX_MPDU_END_DROPPED                = 402 /* 0x192 */,
8019	HAL_RX_ATTENTION_DROPPED               = 403 /* 0x193 */,
8020	HAL_TXPCU_USER_SETUP                   = 404 /* 0x194 */,
8021	HAL_RXPCU_USER_SETUP_EXT               = 405 /* 0x195 */,
8022	HAL_CE_SRC_DESC                        = 406 /* 0x196 */,
8023	HAL_CE_STAT_DESC                       = 407 /* 0x197 */,
8024	HAL_RXOLE_CCE_SUPERRULE                = 408 /* 0x198 */,
8025	HAL_TX_RATE_STATS_INFO                 = 409 /* 0x199 */,
8026	HAL_CMD_PART_0_END                     = 410 /* 0x19a */,
8027	HAL_MACTX_SYNTH_ON                     = 411 /* 0x19b */,
8028	HAL_SCH_CRITICAL_TLV_REFERENCE         = 412 /* 0x19c */,
8029	HAL_TQM_MPDU_GLOBAL_START              = 413 /* 0x19d */,
8030	HAL_EXAMPLE_TLV_32                     = 414 /* 0x19e */,
8031	HAL_TQM_UPDATE_TX_MSDU_FLOW            = 415 /* 0x19f */,
8032	HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD      = 416 /* 0x1a0 */,
8033	HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS     = 417 /* 0x1a1 */,
8034	HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 418 /* 0x1a2 */,
8035	HAL_REO_UPDATE_RX_REO_QUEUE            = 419 /* 0x1a3 */,
8036	HAL_CE_DST_DESC			       = 420 /* 0x1a4 */,
8037	HAL_TLV_BASE                           = 511 /* 0x1ff */,
8038};
8039
8040#define HAL_TLV_HDR_TAG		GENMASK(9, 1)
8041#define HAL_TLV_HDR_LEN		GENMASK(25, 10)
8042#define HAL_TLV_USR_ID		GENMASK(31, 26)
8043
8044#define HAL_TLV_ALIGN	4
8045
8046struct hal_tlv_hdr {
8047	uint32_t tl;
8048	uint8_t value[];
8049} __packed;
8050
8051#define HAL_TLV_64_HDR_TAG	GENMASK(9, 1)
8052#define HAL_TLV_64_HDR_LEN	GENMASK(21, 10)
8053
8054struct hal_tlv_64_hdr {
8055	uint64_t tl;
8056	uint8_t value[];
8057} __packed;
8058
8059#define RX_MPDU_DESC_INFO0_MSDU_COUNT		0xff
8060#define RX_MPDU_DESC_INFO0_SEQ_NUM		0xfff00
8061#define RX_MPDU_DESC_INFO0_FRAG_FLAG		(1 << 20)
8062#define RX_MPDU_DESC_INFO0_MPDU_RETRY		(1 << 21)
8063#define RX_MPDU_DESC_INFO0_AMPDU_FLAG		(1 << 22)
8064#define RX_MPDU_DESC_INFO0_BAR_FRAME		(1 << 23)
8065#define RX_MPDU_DESC_INFO0_VALID_PN		(1 << 24)
8066#define RX_MPDU_DESC_INFO0_VALID_SA		(1 << 25)
8067#define RX_MPDU_DESC_INFO0_SA_IDX_TIMEOUT	(1 << 26)
8068#define RX_MPDU_DESC_INFO0_VALID_DA		(1 << 27)
8069#define RX_MPDU_DESC_INFO0_DA_MCBC		(1 << 28)
8070#define RX_MPDU_DESC_INFO0_DA_IDX_TIMEOUT	(1 << 29)
8071#define RX_MPDU_DESC_INFO0_RAW_MPDU		(1 << 30)
8072
8073#define RX_MPDU_DESC_META_DATA_PEER_ID		0xffff
8074
8075struct rx_mpdu_desc {
8076	uint32_t info0; /* %RX_MPDU_DESC_INFO */
8077	uint32_t meta_data;
8078} __packed;
8079
8080/* rx_mpdu_desc
8081 *		Producer: RXDMA
8082 *		Consumer: REO/SW/FW
8083 *
8084 * msdu_count
8085 *		The number of MSDUs within the MPDU
8086 *
8087 * mpdu_sequence_number
8088 *		The field can have two different meanings based on the setting
8089 *		of field 'bar_frame'. If 'bar_frame' is set, it means the MPDU
8090 *		start sequence number from the BAR frame otherwise it means
8091 *		the MPDU sequence number of the received frame.
8092 *
8093 * fragment_flag
8094 *		When set, this MPDU is a fragment and REO should forward this
8095 *		fragment MPDU to the REO destination ring without any reorder
8096 *		checks, pn checks or bitmap update. This implies that REO is
8097 *		forwarding the pointer to the MSDU link descriptor.
8098 *
8099 * mpdu_retry_bit
8100 *		The retry bit setting from the MPDU header of the received frame
8101 *
8102 * ampdu_flag
8103 *		Indicates the MPDU was received as part of an A-MPDU.
8104 *
8105 * bar_frame
8106 *		Indicates the received frame is a BAR frame. After processing,
8107 *		this frame shall be pushed to SW or deleted.
8108 *
8109 * valid_pn
8110 *		When not set, REO will not perform a PN sequence number check.
8111 *
8112 * valid_sa
8113 *		Indicates OLE found a valid SA entry for all MSDUs in this MPDU.
8114 *
8115 * sa_idx_timeout
8116 *		Indicates, at least 1 MSDU within the MPDU has an unsuccessful
8117 *		MAC source address search due to the expiration of search timer.
8118 *
8119 * valid_da
8120 *		When set, OLE found a valid DA entry for all MSDUs in this MPDU.
8121 *
8122 * da_mcbc
8123 *		Field Only valid if valid_da is set. Indicates at least one of
8124 *		the DA addresses is a Multicast or Broadcast address.
8125 *
8126 * da_idx_timeout
8127 *		Indicates, at least 1 MSDU within the MPDU has an unsuccessful
8128 *		MAC destination address search due to the expiration of search
8129 *		timer.
8130 *
8131 * raw_mpdu
8132 *		Field only valid when first_msdu_in_mpdu_flag is set. Indicates
8133 *		the contents in the MSDU buffer contains a 'RAW' MPDU.
8134 */
8135
8136enum hal_rx_msdu_desc_reo_dest_ind {
8137	HAL_RX_MSDU_DESC_REO_DEST_IND_TCL,
8138	HAL_RX_MSDU_DESC_REO_DEST_IND_SW1,
8139	HAL_RX_MSDU_DESC_REO_DEST_IND_SW2,
8140	HAL_RX_MSDU_DESC_REO_DEST_IND_SW3,
8141	HAL_RX_MSDU_DESC_REO_DEST_IND_SW4,
8142	HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE,
8143	HAL_RX_MSDU_DESC_REO_DEST_IND_FW,
8144};
8145
8146#define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU	(1 << 0)
8147#define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU	(1 << 1)
8148#define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION	(1 << 2)
8149#define RX_MSDU_DESC_INFO0_MSDU_LENGTH		GENMASK(16, 3)
8150#define RX_MSDU_DESC_INFO0_REO_DEST_IND		GENMASK(21, 17)
8151#define RX_MSDU_DESC_INFO0_MSDU_DROP		(1 << 22)
8152#define RX_MSDU_DESC_INFO0_VALID_SA		(1 << 23)
8153#define RX_MSDU_DESC_INFO0_SA_IDX_TIMEOUT	(1 << 24)
8154#define RX_MSDU_DESC_INFO0_VALID_DA		(1 << 25)
8155#define RX_MSDU_DESC_INFO0_DA_MCBC		(1 << 26)
8156#define RX_MSDU_DESC_INFO0_DA_IDX_TIMEOUT	(1 << 27)
8157
8158#define HAL_RX_MSDU_PKT_LENGTH_GET(val)		\
8159	(FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val)))
8160
8161struct rx_msdu_desc {
8162	uint32_t info0;
8163	uint32_t rsvd0;
8164} __packed;
8165
8166/* rx_msdu_desc
8167 *
8168 * first_msdu_in_mpdu
8169 *		Indicates first msdu in mpdu.
8170 *
8171 * last_msdu_in_mpdu
8172 *		Indicates last msdu in mpdu. This flag can be true only when
8173 *		'Msdu_continuation' set to 0. This implies that when an msdu
8174 *		is spread out over multiple buffers and thus msdu_continuation
8175 *		is set, only for the very last buffer of the msdu, can the
8176 *		'last_msdu_in_mpdu' be set.
8177 *
8178 *		When both first_msdu_in_mpdu and last_msdu_in_mpdu are set,
8179 *		the MPDU that this MSDU belongs to only contains a single MSDU.
8180 *
8181 * msdu_continuation
8182 *		When set, this MSDU buffer was not able to hold the entire MSDU.
8183 *		The next buffer will therefore contain additional information
8184 *		related to this MSDU.
8185 *
8186 * msdu_length
8187 *		Field is only valid in combination with the 'first_msdu_in_mpdu'
8188 *		being set. Full MSDU length in bytes after decapsulation. This
8189 *		field is still valid for MPDU frames without A-MSDU. It still
8190 *		represents MSDU length after decapsulation Or in case of RAW
8191 *		MPDUs, it indicates the length of the entire MPDU (without FCS
8192 *		field).
8193 *
8194 * reo_destination_indication
8195 *		The id of the reo exit ring where the msdu frame shall push
8196 *		after (MPDU level) reordering has finished. Values are defined
8197 *		in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_.
8198 *
8199 * msdu_drop
8200 *		Indicates that REO shall drop this MSDU and not forward it to
8201 *		any other ring.
8202 *
8203 * valid_sa
8204 *		Indicates OLE found a valid SA entry for this MSDU.
8205 *
8206 * sa_idx_timeout
8207 *		Indicates, an unsuccessful MAC source address search due to
8208 *		the expiration of search timer for this MSDU.
8209 *
8210 * valid_da
8211 *		When set, OLE found a valid DA entry for this MSDU.
8212 *
8213 * da_mcbc
8214 *		Field Only valid if valid_da is set. Indicates the DA address
8215 *		is a Multicast or Broadcast address for this MSDU.
8216 *
8217 * da_idx_timeout
8218 *		Indicates, an unsuccessful MAC destination address search due
8219 *		to the expiration of search timer for this MSDU.
8220 */
8221
8222struct ath12k_rx_msdu_desc {
8223	uint32_t info0;
8224} __packed;
8225
8226/* rx_msdu_desc
8227 *
8228 * first_msdu_in_mpdu
8229 *		Indicates first msdu in mpdu.
8230 *
8231 * last_msdu_in_mpdu
8232 *		Indicates last msdu in mpdu. This flag can be true only when
8233 *		'Msdu_continuation' set to 0. This implies that when an msdu
8234 *		is spread out over multiple buffers and thus msdu_continuation
8235 *		is set, only for the very last buffer of the msdu, can the
8236 *		'last_msdu_in_mpdu' be set.
8237 *
8238 *		When both first_msdu_in_mpdu and last_msdu_in_mpdu are set,
8239 *		the MPDU that this MSDU belongs to only contains a single MSDU.
8240 *
8241 * msdu_continuation
8242 *		When set, this MSDU buffer was not able to hold the entire MSDU.
8243 *		The next buffer will therefore contain additional information
8244 *		related to this MSDU.
8245 *
8246 * msdu_length
8247 *		Field is only valid in combination with the 'first_msdu_in_mpdu'
8248 *		being set. Full MSDU length in bytes after decapsulation. This
8249 *		field is still valid for MPDU frames without A-MSDU. It still
8250 *		represents MSDU length after decapsulation Or in case of RAW
8251 *		MPDUs, it indicates the length of the entire MPDU (without FCS
8252 *		field).
8253 *
8254 * msdu_drop
8255 *		Indicates that REO shall drop this MSDU and not forward it to
8256 *		any other ring.
8257 *
8258 * valid_sa
8259 *		Indicates OLE found a valid SA entry for this MSDU.
8260 *
8261 * valid_da
8262 *		When set, OLE found a valid DA entry for this MSDU.
8263 *
8264 * da_mcbc
8265 *		Field Only valid if valid_da is set. Indicates the DA address
8266 *		is a Multicast or Broadcast address for this MSDU.
8267 *
8268 * l3_header_padding_msb
8269 *		Passed on from 'RX_MSDU_END' TLV (only the MSB is reported as
8270 *		the LSB is always zero). Number of bytes padded to make sure
8271 *		that the L3 header will always start of a Dword boundary
8272 *
8273 * tcp_udp_checksum_fail
8274 *		Passed on from 'RX_ATTENTION' TLV
8275 *		Indicates that the computed checksum did not match the checksum
8276 *		in the TCP/UDP header.
8277 *
8278 * ip_checksum_fail
8279 *		Passed on from 'RX_ATTENTION' TLV
8280 *		Indicates that the computed checksum did not match the checksum
8281 *		in the IP header.
8282 *
8283 * from_DS
8284 *		Set if the 'from DS' bit is set in the frame control.
8285 *
8286 * to_DS
8287 *		Set if the 'to DS' bit is set in the frame control.
8288 *
8289 * intra_bss
8290 *		This packet needs intra-BSS routing by SW as the 'vdev_id'
8291 *		for the destination is the same as the 'vdev_id' that this
8292 *		MSDU was got in.
8293 *
8294 * dest_chip_id
8295 *		If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY'
8296 *		to support intra-BSS routing with multi-chip multi-link operation.
8297 *		This indicates into which chip's TCL the packet should be queued.
8298 *
8299 * decap_format
8300 *		Indicates the format after decapsulation:
8301 */
8302
8303
8304enum hal_reo_dest_ring_buffer_type {
8305	HAL_REO_DEST_RING_BUFFER_TYPE_MSDU,
8306	HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC,
8307};
8308
8309enum hal_reo_dest_ring_push_reason {
8310	HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED,
8311	HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION,
8312};
8313
8314enum hal_reo_dest_ring_error_code {
8315	HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO,
8316	HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID,
8317	HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA,
8318	HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE,
8319	HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE,
8320	HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP,
8321	HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP,
8322	HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR,
8323	HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR,
8324	HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION,
8325	HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN,
8326	HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED,
8327	HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET,
8328	HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET,
8329	HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED,
8330	HAL_REO_DEST_RING_ERROR_CODE_MAX,
8331};
8332
8333#define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI		GENMASK(7, 0)
8334#define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE		(1 << 8)
8335#define HAL_REO_DEST_RING_INFO0_PUSH_REASON		GENMASK(10, 9)
8336#define HAL_REO_DEST_RING_INFO0_ERROR_CODE		GENMASK(15, 11)
8337#define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM		GENMASK(31, 16)
8338
8339#define HAL_REO_DEST_RING_INFO1_REORDER_INFO_VALID	(1 << 0)
8340#define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE		GENMASK(4, 1)
8341#define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX	GENMASK(12, 5)
8342
8343#define HAL_REO_DEST_RING_INFO2_RING_ID			GENMASK(27, 20)
8344#define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT		GENMASK(31, 28)
8345
8346struct hal_reo_dest_ring {
8347	struct ath12k_buffer_addr buf_addr_info;
8348	struct rx_mpdu_desc rx_mpdu_info;
8349	struct rx_msdu_desc rx_msdu_info;
8350	uint32_t queue_addr_lo;
8351	uint32_t info0; /* %HAL_REO_DEST_RING_INFO0_ */
8352	uint32_t info1; /* %HAL_REO_DEST_RING_INFO1_ */
8353	uint32_t rsvd0;
8354	uint32_t rsvd1;
8355	uint32_t rsvd2;
8356	uint32_t rsvd3;
8357	uint32_t rsvd4;
8358	uint32_t rsvd5;
8359	uint32_t info2; /* %HAL_REO_DEST_RING_INFO2_ */
8360} __packed;
8361
8362/* hal_reo_dest_ring
8363 *
8364 *		Producer: RXDMA
8365 *		Consumer: REO/SW/FW
8366 *
8367 * buf_addr_info
8368 *		Details of the physical address of a buffer or MSDU
8369 *		link descriptor.
8370 *
8371 * rx_mpdu_info
8372 *		General information related to the MPDU that is passed
8373 *		on from REO entrance ring to the REO destination ring.
8374 *
8375 * rx_msdu_info
8376 *		General information related to the MSDU that is passed
8377 *		on from RXDMA all the way to the REO destination ring.
8378 *
8379 * queue_addr_lo
8380 *		Address (lower 32 bits) of the REO queue descriptor.
8381 *
8382 * queue_addr_hi
8383 *		Address (upper 8 bits) of the REO queue descriptor.
8384 *
8385 * buffer_type
8386 *		Indicates the type of address provided in the buf_addr_info.
8387 *		Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_.
8388 *
8389 * push_reason
8390 *		Reason for pushing this frame to this exit ring. Values are
8391 *		defined in enum %HAL_REO_DEST_RING_PUSH_REASON_.
8392 *
8393 * error_code
8394 *		Valid only when 'push_reason' is set. All error codes are
8395 *		defined in enum %HAL_REO_DEST_RING_ERROR_CODE_.
8396 *
8397 * rx_queue_num
8398 *		Indicates the REO MPDU reorder queue id from which this frame
8399 *		originated.
8400 *
8401 * reorder_info_valid
8402 *		When set, REO has been instructed to not perform the actual
8403 *		re-ordering of frames for this queue, but just to insert
8404 *		the reorder opcodes.
8405 *
8406 * reorder_opcode
8407 *		Field is valid when 'reorder_info_valid' is set. This field is
8408 *		always valid for debug purpose as well.
8409 *
8410 * reorder_slot_idx
8411 *		Valid only when 'reorder_info_valid' is set.
8412 *
8413 * ring_id
8414 *		The buffer pointer ring id.
8415 *		0 - Idle ring
8416 *		1 - N refers to other rings.
8417 *
8418 * looping_count
8419 *		Indicates the number of times the producer of entries into
8420 *		this ring has looped around the ring.
8421 */
8422
8423struct ath12k_hal_reo_dest_ring {
8424	struct ath12k_buffer_addr buf_addr_info;
8425	struct rx_mpdu_desc rx_mpdu_info;
8426	struct ath12k_rx_msdu_desc rx_msdu_info;
8427	uint32_t buf_va_lo;
8428	uint32_t buf_va_hi;
8429	uint32_t info0; /* %HAL_REO_DEST_RING_INFO0_ */
8430} __packed;
8431
8432/* hal_reo_dest_ring
8433 *
8434 *		Producer: RXDMA
8435 *		Consumer: REO/SW/FW
8436 *
8437 * buf_addr_info
8438 *		Details of the physical address of a buffer or MSDU
8439 *		link descriptor.
8440 *
8441 * rx_mpdu_info
8442 *		General information related to the MPDU that is passed
8443 *		on from REO entrance ring to the REO destination ring.
8444 *
8445 * rx_msdu_info
8446 *		General information related to the MSDU that is passed
8447 *		on from RXDMA all the way to the REO destination ring.
8448 *
8449 * buf_va_lo
8450 *		Field only valid if Reo_dest_buffer_type is set to
8451 *              MSDU_buf_address.
8452 *		Lower 32 bits of the 64-bit virtual address corresponding
8453 *		to Buf_or_link_desc_addr_info
8454 *
8455 * buf_va_hi
8456 *		Address (upper 32 bits) of the REO queue descriptor.
8457 *		Upper 32 bits of the 64-bit virtual address corresponding
8458 *		to Buf_or_link_desc_addr_info
8459 *
8460 * buffer_type
8461 *		Indicates the type of address provided in the buf_addr_info.
8462 *		Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_.
8463 *
8464 * push_reason
8465 *		Reason for pushing this frame to this exit ring. Values are
8466 *		defined in enum %HAL_REO_DEST_RING_PUSH_REASON_.
8467 *
8468 * error_code
8469 *		Valid only when 'push_reason' is set. All error codes are
8470 *		defined in enum %HAL_REO_DEST_RING_ERROR_CODE_.
8471 *
8472 * captured_msdu_data_size
8473 *		The number of following REO_DESTINATION STRUCTs that have
8474 *		been replaced with msdu_data extracted from the msdu_buffer
8475 *		and copied into the ring for easy FW/SW access.
8476 *
8477 * sw_exception
8478 *		This field has the same setting as the SW_exception field
8479 *		in the corresponding REO_entrance_ring descriptor.
8480 *		When set, the REO entrance descriptor is generated by FW,
8481 *		and the MPDU was processed in the following way:
8482 *		- NO re-order function is needed.
8483 *		- MPDU delinking is determined by the setting of Entrance
8484 *		  ring field: SW_exception_mpdu_delink
8485 *		- Destination ring selection is based on the setting of
8486 *		  the Entrance ring field SW_exception_destination _ring_valid
8487 *
8488 * src_link_id
8489 *		Set to the link ID of the PMAC that received the frame
8490 *
8491 * signature
8492 *		Set to value 0x8 when msdu capture mode is enabled for this ring
8493 *
8494 * ring_id
8495 *		The buffer pointer ring id.
8496 *		0 - Idle ring
8497 *		1 - N refers to other rings.
8498 *
8499 * looping_count
8500 *		Indicates the number of times the producer of entries into
8501 *		this ring has looped around the ring.
8502 */
8503
8504enum hal_reo_entr_rxdma_ecode {
8505	HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR,
8506	HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR,
8507	HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR,
8508	HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR,
8509	HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR,
8510	HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR,
8511	HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR,
8512	HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR,
8513	HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR,
8514	HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR,
8515	HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR,
8516	HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR,
8517	HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR,
8518	HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR,
8519	HAL_REO_ENTR_RING_RXDMA_ECODE_MAX,
8520};
8521
8522#define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI		GENMASK(7, 0)
8523#define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT		GENMASK(21, 8)
8524#define HAL_REO_ENTR_RING_INFO0_DEST_IND		GENMASK(26, 22)
8525#define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR		BIT(27)
8526
8527#define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON	GENMASK(1, 0)
8528#define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE	GENMASK(6, 2)
8529
8530struct hal_reo_entrance_ring {
8531	struct ath12k_buffer_addr buf_addr_info;
8532	struct rx_mpdu_desc rx_mpdu_info;
8533	uint32_t queue_addr_lo;
8534	uint32_t info0; /* %HAL_REO_ENTR_RING_INFO0_ */
8535	uint32_t info1; /* %HAL_REO_ENTR_RING_INFO1_ */
8536	uint32_t info2; /* %HAL_REO_DEST_RING_INFO2_ */
8537} __packed;
8538
8539/* hal_reo_entrance_ring
8540 *
8541 *		Producer: RXDMA
8542 *		Consumer: REO
8543 *
8544 * buf_addr_info
8545 *		Details of the physical address of a buffer or MSDU
8546 *		link descriptor.
8547 *
8548 * rx_mpdu_info
8549 *		General information related to the MPDU that is passed
8550 *		on from REO entrance ring to the REO destination ring.
8551 *
8552 * queue_addr_lo
8553 *		Address (lower 32 bits) of the REO queue descriptor.
8554 *
8555 * queue_addr_hi
8556 *		Address (upper 8 bits) of the REO queue descriptor.
8557 *
8558 * mpdu_byte_count
8559 *		An approximation of the number of bytes received in this MPDU.
8560 *		Used to keeps stats on the amount of data flowing
8561 *		through a queue.
8562 *
8563 * reo_destination_indication
8564 *		The id of the reo exit ring where the msdu frame shall push
8565 *		after (MPDU level) reordering has finished. Values are defined
8566 *		in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_.
8567 *
8568 * frameless_bar
8569 *		Indicates that this REO entrance ring struct contains BAR info
8570 *		from a multi TID BAR frame. The original multi TID BAR frame
8571 *		itself contained all the REO info for the first TID, but all
8572 *		the subsequent TID info and their linkage to the REO descriptors
8573 *		is passed down as 'frameless' BAR info.
8574 *
8575 *		The only fields valid in this descriptor when this bit is set
8576 *		are queue_addr_lo, queue_addr_hi, mpdu_sequence_number,
8577 *		bar_frame and peer_meta_data.
8578 *
8579 * rxdma_push_reason
8580 *		Reason for pushing this frame to this exit ring. Values are
8581 *		defined in enum %HAL_REO_DEST_RING_PUSH_REASON_.
8582 *
8583 * rxdma_error_code
8584 *		Valid only when 'push_reason' is set. All error codes are
8585 *		defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_.
8586 *
8587 * ring_id
8588 *		The buffer pointer ring id.
8589 *		0 - Idle ring
8590 *		1 - N refers to other rings.
8591 *
8592 * looping_count
8593 *		Indicates the number of times the producer of entries into
8594 *		this ring has looped around the ring.
8595 */
8596
8597#define HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON	GENMASK(1, 0)
8598#define HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE	GENMASK(6, 2)
8599#define HAL_SW_MON_RING_INFO0_MPDU_FRAG_NUMBER	GENMASK(10, 7)
8600#define HAL_SW_MON_RING_INFO0_FRAMELESS_BAR	BIT(11)
8601#define HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT	GENMASK(15, 12)
8602#define HAL_SW_MON_RING_INFO0_END_OF_PPDU	BIT(16)
8603
8604#define HAL_SW_MON_RING_INFO1_PHY_PPDU_ID	GENMASK(15, 0)
8605#define HAL_SW_MON_RING_INFO1_RING_ID		GENMASK(27, 20)
8606#define HAL_SW_MON_RING_INFO1_LOOPING_COUNT	GENMASK(31, 28)
8607
8608struct hal_sw_monitor_ring {
8609	struct ath12k_buffer_addr buf_addr_info;
8610	struct rx_mpdu_desc rx_mpdu_info;
8611	struct ath12k_buffer_addr status_buf_addr_info;
8612	uint32_t info0;
8613	uint32_t info1;
8614} __packed;
8615
8616#define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER	GENMASK(15, 0)
8617#define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED	BIT(16)
8618
8619struct hal_reo_cmd_hdr {
8620	uint32_t info0;
8621} __packed;
8622
8623
8624#define HAL_SRNG_DESC_LOOP_CNT		0xf0000000
8625
8626#define HAL_REO_CMD_FLG_NEED_STATUS		BIT(0)
8627#define HAL_REO_CMD_FLG_STATS_CLEAR		BIT(1)
8628#define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER	BIT(2)
8629#define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING	BIT(3)
8630#define HAL_REO_CMD_FLG_FLUSH_NO_INVAL		BIT(4)
8631#define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS	BIT(5)
8632#define HAL_REO_CMD_FLG_FLUSH_ALL		BIT(6)
8633#define HAL_REO_CMD_FLG_UNBLK_RESOURCE		BIT(7)
8634#define HAL_REO_CMD_FLG_UNBLK_CACHE		BIT(8)
8635
8636/* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* fields */
8637#define HAL_REO_CMD_UPD0_RX_QUEUE_NUM		BIT(8)
8638#define HAL_REO_CMD_UPD0_VLD			BIT(9)
8639#define HAL_REO_CMD_UPD0_ALDC			BIT(10)
8640#define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION	BIT(11)
8641#define HAL_REO_CMD_UPD0_SOFT_REORDER_EN	BIT(12)
8642#define HAL_REO_CMD_UPD0_AC			BIT(13)
8643#define HAL_REO_CMD_UPD0_BAR			BIT(14)
8644#define HAL_REO_CMD_UPD0_RETRY			BIT(15)
8645#define HAL_REO_CMD_UPD0_CHECK_2K_MODE		BIT(16)
8646#define HAL_REO_CMD_UPD0_OOR_MODE		BIT(17)
8647#define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE		BIT(18)
8648#define HAL_REO_CMD_UPD0_PN_CHECK		BIT(19)
8649#define HAL_REO_CMD_UPD0_EVEN_PN		BIT(20)
8650#define HAL_REO_CMD_UPD0_UNEVEN_PN		BIT(21)
8651#define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE	BIT(22)
8652#define HAL_REO_CMD_UPD0_PN_SIZE		BIT(23)
8653#define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG	BIT(24)
8654#define HAL_REO_CMD_UPD0_SVLD			BIT(25)
8655#define HAL_REO_CMD_UPD0_SSN			BIT(26)
8656#define HAL_REO_CMD_UPD0_SEQ_2K_ERR		BIT(27)
8657#define HAL_REO_CMD_UPD0_PN_ERR			BIT(28)
8658#define HAL_REO_CMD_UPD0_PN_VALID		BIT(29)
8659#define HAL_REO_CMD_UPD0_PN			BIT(30)
8660
8661/* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* fields */
8662#define HAL_REO_CMD_UPD1_VLD			BIT(16)
8663#define HAL_REO_CMD_UPD1_ALDC			GENMASK(18, 17)
8664#define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION	BIT(19)
8665#define HAL_REO_CMD_UPD1_SOFT_REORDER_EN	BIT(20)
8666#define HAL_REO_CMD_UPD1_AC			GENMASK(22, 21)
8667#define HAL_REO_CMD_UPD1_BAR			BIT(23)
8668#define HAL_REO_CMD_UPD1_RETRY			BIT(24)
8669#define HAL_REO_CMD_UPD1_CHECK_2K_MODE		BIT(25)
8670#define HAL_REO_CMD_UPD1_OOR_MODE		BIT(26)
8671#define HAL_REO_CMD_UPD1_PN_CHECK		BIT(27)
8672#define HAL_REO_CMD_UPD1_EVEN_PN		BIT(28)
8673#define HAL_REO_CMD_UPD1_UNEVEN_PN		BIT(29)
8674#define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE	BIT(30)
8675#define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG	BIT(31)
8676
8677/* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* fields */
8678#define HAL_REO_CMD_UPD2_SVLD			BIT(10)
8679#define HAL_REO_CMD_UPD2_SSN			GENMASK(22, 11)
8680#define HAL_REO_CMD_UPD2_SEQ_2K_ERR		BIT(23)
8681#define HAL_REO_CMD_UPD2_PN_ERR			BIT(24)
8682
8683#define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP	GENMASK(31, 8)
8684
8685struct ath12k_hal_reo_cmd {
8686	uint32_t addr_lo;
8687	uint32_t flag;
8688	uint32_t upd0;
8689	uint32_t upd1;
8690	uint32_t upd2;
8691	uint32_t pn[4];
8692	uint16_t rx_queue_num;
8693	uint16_t min_rel;
8694	uint16_t min_fwd;
8695	uint8_t addr_hi;
8696	uint8_t ac_list;
8697	uint8_t blocking_idx;
8698	uint16_t ba_window_size;
8699	uint8_t pn_size;
8700};
8701
8702#define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI	GENMASK(7, 0)
8703#define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS	BIT(8)
8704
8705struct hal_reo_get_queue_stats {
8706	struct hal_reo_cmd_hdr cmd;
8707	uint32_t queue_addr_lo;
8708	uint32_t info0;
8709	uint32_t rsvd0[6];
8710	uint32_t tlv64_pad;
8711} __packed;
8712
8713/* hal_reo_get_queue_stats
8714 *		Producer: SW
8715 *		Consumer: REO
8716 *
8717 * cmd
8718 *		Details for command execution tracking purposes.
8719 *
8720 * queue_addr_lo
8721 *		Address (lower 32 bits) of the REO queue descriptor.
8722 *
8723 * queue_addr_hi
8724 *		Address (upper 8 bits) of the REO queue descriptor.
8725 *
8726 * clear_stats
8727 *		Clear stats settings. When set, Clear the stats after
8728 *		generating the status.
8729 *
8730 *		Following stats will be cleared.
8731 *		Timeout_count
8732 *		Forward_due_to_bar_count
8733 *		Duplicate_count
8734 *		Frames_in_order_count
8735 *		BAR_received_count
8736 *		MPDU_Frames_processed_count
8737 *		MSDU_Frames_processed_count
8738 *		Total_processed_byte_count
8739 *		Late_receive_MPDU_count
8740 *		window_jump_2k
8741 *		Hole_count
8742 */
8743
8744#define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI		GENMASK(7, 0)
8745#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR	BIT(8)
8746#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX	GENMASK(10, 9)
8747
8748struct hal_reo_flush_queue {
8749	struct hal_reo_cmd_hdr cmd;
8750	uint32_t desc_addr_lo;
8751	uint32_t info0;
8752	uint32_t rsvd0[6];
8753} __packed;
8754
8755#define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI		GENMASK(7, 0)
8756#define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS		BIT(8)
8757#define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX	BIT(9)
8758#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX	GENMASK(11, 10)
8759#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE	BIT(12)
8760#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE	BIT(13)
8761#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL		BIT(14)
8762
8763struct hal_reo_flush_cache {
8764	struct hal_reo_cmd_hdr cmd;
8765	uint32_t cache_addr_lo;
8766	uint32_t info0;
8767	uint32_t rsvd0[6];
8768} __packed;
8769
8770#define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE	BIT(0)
8771#define HAL_TCL_DATA_CMD_INFO0_EPD		BIT(1)
8772#define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE	GENMASK(3, 2)
8773#define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE	GENMASK(7, 4)
8774#define HAL_TCL_DATA_CMD_INFO0_SRC_BUF_SWAP	BIT(8)
8775#define HAL_TCL_DATA_CMD_INFO0_LNK_META_SWAP	BIT(9)
8776#define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE	GENMASK(13, 12)
8777#define HAL_TCL_DATA_CMD_INFO0_ADDR_EN		GENMASK(15, 14)
8778#define HAL_TCL_DATA_CMD_INFO0_CMD_NUM		GENMASK(31, 16)
8779
8780#define HAL_TCL_DATA_CMD_INFO1_DATA_LEN		GENMASK(15, 0)
8781#define HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN	BIT(16)
8782#define HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN	BIT(17)
8783#define HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN	BIT(18)
8784#define HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN	BIT(19)
8785#define HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN	BIT(20)
8786#define HAL_TCL_DATA_CMD_INFO1_TO_FW		BIT(21)
8787#define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET	GENMASK(31, 23)
8788
8789#define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP		GENMASK(18, 0)
8790#define HAL_TCL_DATA_CMD_INFO2_BUF_T_VALID		BIT(19)
8791#define HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE	BIT(20)
8792#define HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE		BIT(21)
8793#define HAL_TCL_DATA_CMD_INFO2_TID			GENMASK(25, 22)
8794#define HAL_TCL_DATA_CMD_INFO2_LMAC_ID			GENMASK(27, 26)
8795
8796#define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX	GENMASK(5, 0)
8797#define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX		GENMASK(25, 6)
8798#define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM		GENMASK(29, 26)
8799#define HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE	GENMASK(31, 30)
8800
8801#define HAL_TCL_DATA_CMD_INFO4_RING_ID			GENMASK(27, 20)
8802#define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT		GENMASK(31, 28)
8803
8804enum hal_encrypt_type {
8805	HAL_ENCRYPT_TYPE_WEP_40,
8806	HAL_ENCRYPT_TYPE_WEP_104,
8807	HAL_ENCRYPT_TYPE_TKIP_NO_MIC,
8808	HAL_ENCRYPT_TYPE_WEP_128,
8809	HAL_ENCRYPT_TYPE_TKIP_MIC,
8810	HAL_ENCRYPT_TYPE_WAPI,
8811	HAL_ENCRYPT_TYPE_CCMP_128,
8812	HAL_ENCRYPT_TYPE_OPEN,
8813	HAL_ENCRYPT_TYPE_CCMP_256,
8814	HAL_ENCRYPT_TYPE_GCMP_128,
8815	HAL_ENCRYPT_TYPE_AES_GCMP_256,
8816	HAL_ENCRYPT_TYPE_WAPI_GCM_SM4,
8817};
8818
8819enum hal_tcl_encap_type {
8820	HAL_TCL_ENCAP_TYPE_RAW,
8821	HAL_TCL_ENCAP_TYPE_NATIVE_WIFI,
8822	HAL_TCL_ENCAP_TYPE_ETHERNET,
8823	HAL_TCL_ENCAP_TYPE_802_3 = 3,
8824};
8825
8826enum hal_tcl_desc_type {
8827	HAL_TCL_DESC_TYPE_BUFFER,
8828	HAL_TCL_DESC_TYPE_EXT_DESC,
8829};
8830
8831enum hal_wbm_htt_tx_comp_status {
8832	HAL_WBM_REL_HTT_TX_COMP_STATUS_OK,
8833	HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP,
8834	HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL,
8835	HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ,
8836	HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT,
8837	HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY,
8838};
8839
8840struct hal_tcl_data_cmd {
8841	struct ath12k_buffer_addr buf_addr_info;
8842	uint32_t info0;
8843	uint32_t info1;
8844	uint32_t info2;
8845	uint32_t info3;
8846	uint32_t info4;
8847	uint32_t info5;
8848} __packed;
8849
8850/* hal_tcl_data_cmd
8851 *
8852 * buf_addr_info
8853 *		Details of the physical address of a buffer or MSDU
8854 *		link descriptor.
8855 *
8856 * tcl_cmd_type
8857 *		used to select the type of TCL Command descriptor
8858 *
8859 * desc_type
8860 *		Indicates the type of address provided in the buf_addr_info.
8861 *		Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_.
8862 *
8863 * bank_id
8864 *		used to select one of the TCL register banks for fields removed
8865 *		from 'TCL_DATA_CMD' that do not change often within one virtual
8866 *		device or a set of virtual devices:
8867 *
8868 * tx_notify_frame
8869 *		TCL copies this value to 'TQM_ENTRANCE_RING' field FW_tx_notify_frame.
8870 *
8871 * hdr_length_read_sel
8872 *		used to select the per 'encap_type' register set for MSDU header
8873 *		read length
8874 *
8875 * buffer_timestamp
8876 * buffer_timestamp_valid
8877 *		Frame system entrance timestamp. It shall be filled by first
8878 *		module (SW, TCL or TQM) that sees the frames first.
8879 *
8880 * cmd_num
8881 *		This number can be used to match against status.
8882 *
8883 * data_length
8884 *		MSDU length in case of direct descriptor. Length of link
8885 *		extension descriptor in case of Link extension descriptor.
8886 *
8887 * *_checksum_en
8888 *		Enable checksum replacement for ipv4, udp_over_ipv4, ipv6,
8889 *		udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6.
8890 *
8891 * to_fw
8892 *		Forward packet to FW along with classification result. The
8893 *		packet will not be forward to TQM when this bit is set.
8894 *		1'b0: Use classification result to forward the packet.
8895 *		1'b1: Override classification result & forward packet only to fw
8896 *
8897 * packet_offset
8898 *		Packet offset from Metadata in case of direct buffer descriptor.
8899 *
8900 * hlos_tid_overwrite
8901 *
8902 *		When set, TCL shall ignore the IP DSCP and VLAN PCP
8903 *		fields and use HLOS_TID as the final TID. Otherwise TCL
8904 *		shall consider the DSCP and PCP fields as well as HLOS_TID
8905 *		and choose a final TID based on the configured priority
8906 *
8907 * flow_override_enable
8908 *		TCL uses this to select the flow pointer from the peer table,
8909 *		which can be overridden by SW for pre-encrypted raw WiFi packets
8910 *		that cannot be parsed for UDP or for other MLO
8911 *		0 - FP_PARSE_IP: Use the flow-pointer based on parsing the IPv4
8912 *				 or IPv6 header.
8913 *		1 - FP_USE_OVERRIDE: Use the who_classify_info_sel and
8914 *				     flow_override fields to select the flow-pointer
8915 *
8916 * who_classify_info_sel
8917 *		Field only valid when flow_override_enable is set to FP_USE_OVERRIDE.
8918 *		This field is used to select  one of the 'WHO_CLASSIFY_INFO's in the
8919 *		peer table in case more than 2 flows are mapped to a single TID.
8920 *		0: To choose Flow 0 and 1 of any TID use this value.
8921 *		1: To choose Flow 2 and 3 of any TID use this value.
8922 *		2: To choose Flow 4 and 5 of any TID use this value.
8923 *		3: To choose Flow 6 and 7 of any TID use this value.
8924 *
8925 *		If who_classify_info sel is not in sync with the num_tx_classify_info
8926 *		field from address search, then TCL will set 'who_classify_info_sel'
8927 *		to 0 use flows 0 and 1.
8928 *
8929 * hlos_tid
8930 *		HLOS MSDU priority
8931 *		Field is used when HLOS_TID_overwrite is set.
8932 *
8933 * flow_override
8934 *		Field only valid when flow_override_enable is set to FP_USE_OVERRIDE
8935 *		TCL uses this to select the flow pointer from the peer table,
8936 *		which can be overridden by SW for pre-encrypted raw WiFi packets
8937 *		that cannot be parsed for UDP or for other MLO
8938 *		0 - FP_USE_NON_UDP: Use the non-UDP flow pointer (flow 0)
8939 *		1 - FP_USE_UDP: Use the UDP flow pointer (flow 1)
8940 *
8941 * pmac_id
8942 *		TCL uses this PMAC_ID in address search, i.e, while
8943 *		finding matching entry for the packet in AST corresponding
8944 *		to given PMAC_ID
8945 *
8946 *		If PMAC ID is all 1s (=> value 3), it indicates wildcard
8947 *		match for any PMAC
8948 *
8949 * vdev_id
8950 *		Virtual device ID to check against the address search entry to
8951 *		avoid security issues from transmitting packets from an incorrect
8952 *		virtual device
8953 *
8954 * search_index
8955 *		The index that will be used for index based address or
8956 *		flow search. The field is valid when 'search_type' is  1 or 2.
8957 *
8958 * cache_set_num
8959 *
8960 *		Cache set number that should be used to cache the index
8961 *		based search results, for address and flow search. This
8962 *		value should be equal to LSB four bits of the hash value of
8963 *		match data, in case of search index points to an entry which
8964 *		may be used in content based search also. The value can be
8965 *		anything when the entry pointed by search index will not be
8966 *		used for content based search.
8967 *
8968 * index_loop_override
8969 *		When set, address search and packet routing is forced to use
8970 *		'search_index' instead of following the register configuration
8971 *		selected by Bank_id.
8972 *
8973 * ring_id
8974 *		The buffer pointer ring ID.
8975 *		0 refers to the IDLE ring
8976 *		1 - N refers to other rings
8977 *
8978 * looping_count
8979 *
8980 *		A count value that indicates the number of times the
8981 *		producer of entries into the Ring has looped around the
8982 *		ring.
8983 *
8984 *		At initialization time, this value is set to 0. On the
8985 *		first loop, this value is set to 1. After the max value is
8986 *		reached allowed by the number of bits for this field, the
8987 *		count value continues with 0 again.
8988 *
8989 *		In case SW is the consumer of the ring entries, it can
8990 *		use this field to figure out up to where the producer of
8991 *		entries has created new entries. This eliminates the need to
8992 *		check where the head pointer' of the ring is located once
8993 *		the SW starts processing an interrupt indicating that new
8994 *		entries have been put into this ring...
8995 *
8996 *		Also note that SW if it wants only needs to look at the
8997 *		LSB bit of this count value.
8998 */
8999
9000#define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd)
9001
9002enum hal_tcl_gse_ctrl {
9003	HAL_TCL_GSE_CTRL_RD_STAT,
9004	HAL_TCL_GSE_CTRL_SRCH_DIS,
9005	HAL_TCL_GSE_CTRL_WR_BK_SINGLE,
9006	HAL_TCL_GSE_CTRL_WR_BK_ALL,
9007	HAL_TCL_GSE_CTRL_INVAL_SINGLE,
9008	HAL_TCL_GSE_CTRL_INVAL_ALL,
9009	HAL_TCL_GSE_CTRL_WR_BK_INVAL_SINGLE,
9010	HAL_TCL_GSE_CTRL_WR_BK_INVAL_ALL,
9011	HAL_TCL_GSE_CTRL_CLR_STAT_SINGLE,
9012};
9013
9014/* hal_tcl_gse_ctrl
9015 *
9016 * rd_stat
9017 *		Report or Read statistics
9018 * srch_dis
9019 *		Search disable. Report only Hash.
9020 * wr_bk_single
9021 *		Write Back single entry
9022 * wr_bk_all
9023 *		Write Back entire cache entry
9024 * inval_single
9025 *		Invalidate single cache entry
9026 * inval_all
9027 *		Invalidate entire cache
9028 * wr_bk_inval_single
9029 *		Write back and invalidate single entry in cache
9030 * wr_bk_inval_all
9031 *		Write back and invalidate entire cache
9032 * clr_stat_single
9033 *		Clear statistics for single entry
9034 */
9035
9036#define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI		GENMASK(7, 0)
9037#define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL			GENMASK(11, 8)
9038#define HAL_TCL_GSE_CMD_INFO0_GSE_SEL			BIT(12)
9039#define HAL_TCL_GSE_CMD_INFO0_STATUS_DEST_RING_ID	BIT(13)
9040#define HAL_TCL_GSE_CMD_INFO0_SWAP			BIT(14)
9041
9042#define HAL_TCL_GSE_CMD_INFO1_RING_ID			GENMASK(27, 20)
9043#define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT		GENMASK(31, 28)
9044
9045struct hal_tcl_gse_cmd {
9046	uint32_t ctrl_buf_addr_lo;
9047	uint32_t info0;
9048	uint32_t meta_data[2];
9049	uint32_t rsvd0[2];
9050	uint32_t info1;
9051} __packed;
9052
9053/* hal_tcl_gse_cmd
9054 *
9055 * ctrl_buf_addr_lo, ctrl_buf_addr_hi
9056 *		Address of a control buffer containing additional info needed
9057 *		for this command execution.
9058 *
9059 * gse_ctrl
9060 *		GSE control operations. This includes cache operations and table
9061 *		entry statistics read/clear operation. Values are defined in
9062 *		enum %HAL_TCL_GSE_CTRL.
9063 *
9064 * gse_sel
9065 *		To select the ASE/FSE to do the operation mention by GSE_ctrl.
9066 *		0: FSE select 1: ASE select
9067 *
9068 * status_destination_ring_id
9069 *		TCL status ring to which the GSE status needs to be send.
9070 *
9071 * swap
9072 *		Bit to enable byte swapping of contents of buffer.
9073 *
9074 * meta_data
9075 *		Meta data to be returned in the status descriptor
9076 */
9077
9078enum hal_tcl_cache_op_res {
9079	HAL_TCL_CACHE_OP_RES_DONE,
9080	HAL_TCL_CACHE_OP_RES_NOT_FOUND,
9081	HAL_TCL_CACHE_OP_RES_TIMEOUT,
9082};
9083
9084#define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL		GENMASK(3, 0)
9085#define HAL_TCL_STATUS_RING_INFO0_GSE_SEL		BIT(4)
9086#define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES		GENMASK(6, 5)
9087#define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT		GENMASK(31, 8)
9088
9089#define HAL_TCL_STATUS_RING_INFO1_HASH_IDX		GENMASK(19, 0)
9090
9091#define HAL_TCL_STATUS_RING_INFO2_RING_ID		GENMASK(27, 20)
9092#define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT		GENMASK(31, 28)
9093
9094struct hal_tcl_status_ring {
9095	uint32_t info0;
9096	uint32_t msdu_byte_count;
9097	uint32_t msdu_timestamp;
9098	uint32_t meta_data[2];
9099	uint32_t info1;
9100	uint32_t rsvd0;
9101	uint32_t info2;
9102} __packed;
9103
9104/* hal_tcl_status_ring
9105 *
9106 * gse_ctrl
9107 *		GSE control operations. This includes cache operations and table
9108 *		entry statistics read/clear operation. Values are defined in
9109 *		enum %HAL_TCL_GSE_CTRL.
9110 *
9111 * gse_sel
9112 *		To select the ASE/FSE to do the operation mention by GSE_ctrl.
9113 *		0: FSE select 1: ASE select
9114 *
9115 * cache_op_res
9116 *		Cache operation result. Values are defined in enum
9117 *		%HAL_TCL_CACHE_OP_RES_.
9118 *
9119 * msdu_cnt
9120 * msdu_byte_count
9121 *		MSDU count of Entry and MSDU byte count for entry 1.
9122 *
9123 * hash_indx
9124 *		Hash value of the entry in case of search failed or disabled.
9125 */
9126
9127#define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI	GENMASK(7, 0)
9128#define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN	BIT(8)
9129#define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP	BIT(9)
9130#define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP	BIT(10)
9131#define HAL_CE_SRC_DESC_ADDR_INFO_GATHER	BIT(11)
9132#define HAL_CE_SRC_DESC_ADDR_INFO_LEN		GENMASK(31, 16)
9133
9134#define HAL_CE_SRC_DESC_META_INFO_DATA		GENMASK(15, 0)
9135
9136#define HAL_CE_SRC_DESC_FLAGS_RING_ID		GENMASK(27, 20)
9137#define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT		HAL_SRNG_DESC_LOOP_CNT
9138
9139struct hal_ce_srng_src_desc {
9140	uint32_t buffer_addr_low;
9141	uint32_t buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */
9142	uint32_t meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */
9143	uint32_t flags; /* %HAL_CE_SRC_DESC_FLAGS_ */
9144} __packed;
9145
9146/*
9147 * hal_ce_srng_src_desc
9148 *
9149 * buffer_addr_lo
9150 *		LSB 32 bits of the 40 Bit Pointer to the source buffer
9151 *
9152 * buffer_addr_hi
9153 *		MSB 8 bits of the 40 Bit Pointer to the source buffer
9154 *
9155 * toeplitz_en
9156 *		Enable generation of 32-bit Toeplitz-LFSR hash for
9157 *		data transfer. In case of gather field in first source
9158 *		ring entry of the gather copy cycle in taken into account.
9159 *
9160 * src_swap
9161 *		Treats source memory organization as big-endian. For
9162 *		each dword read (4 bytes), the byte 0 is swapped with byte 3
9163 *		and byte 1 is swapped with byte 2.
9164 *		In case of gather field in first source ring entry of
9165 *		the gather copy cycle in taken into account.
9166 *
9167 * dest_swap
9168 *		Treats destination memory organization as big-endian.
9169 *		For each dword write (4 bytes), the byte 0 is swapped with
9170 *		byte 3 and byte 1 is swapped with byte 2.
9171 *		In case of gather field in first source ring entry of
9172 *		the gather copy cycle in taken into account.
9173 *
9174 * gather
9175 *		Enables gather of multiple copy engine source
9176 *		descriptors to one destination.
9177 *
9178 * ce_res_0
9179 *		Reserved
9180 *
9181 *
9182 * length
9183 *		Length of the buffer in units of octets of the current
9184 *		descriptor
9185 *
9186 * fw_metadata
9187 *		Meta data used by FW.
9188 *		In case of gather field in first source ring entry of
9189 *		the gather copy cycle in taken into account.
9190 *
9191 * ce_res_1
9192 *		Reserved
9193 *
9194 * ce_res_2
9195 *		Reserved
9196 *
9197 * ring_id
9198 *		The buffer pointer ring ID.
9199 *		0 refers to the IDLE ring
9200 *		1 - N refers to other rings
9201 *		Helps with debugging when dumping ring contents.
9202 *
9203 * looping_count
9204 *		A count value that indicates the number of times the
9205 *		producer of entries into the Ring has looped around the
9206 *		ring.
9207 *
9208 *		At initialization time, this value is set to 0. On the
9209 *		first loop, this value is set to 1. After the max value is
9210 *		reached allowed by the number of bits for this field, the
9211 *		count value continues with 0 again.
9212 *
9213 *		In case SW is the consumer of the ring entries, it can
9214 *		use this field to figure out up to where the producer of
9215 *		entries has created new entries. This eliminates the need to
9216 *		check where the head pointer' of the ring is located once
9217 *		the SW starts processing an interrupt indicating that new
9218 *		entries have been put into this ring...
9219 *
9220 *		Also note that SW if it wants only needs to look at the
9221 *		LSB bit of this count value.
9222 */
9223
9224#define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI		GENMASK(7, 0)
9225#define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID		GENMASK(27, 20)
9226#define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT		HAL_SRNG_DESC_LOOP_CNT
9227
9228struct hal_ce_srng_dest_desc {
9229	uint32_t buffer_addr_low;
9230	uint32_t buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */
9231} __packed;
9232
9233/* hal_ce_srng_dest_desc
9234 *
9235 * dst_buffer_low
9236 *		LSB 32 bits of the 40 Bit Pointer to the Destination
9237 *		buffer
9238 *
9239 * dst_buffer_high
9240 *		MSB 8 bits of the 40 Bit Pointer to the Destination
9241 *		buffer
9242 *
9243 * ce_res_4
9244 *		Reserved
9245 *
9246 * ring_id
9247 *		The buffer pointer ring ID.
9248 *		0 refers to the IDLE ring
9249 *		1 - N refers to other rings
9250 *		Helps with debugging when dumping ring contents.
9251 *
9252 * looping_count
9253 *		A count value that indicates the number of times the
9254 *		producer of entries into the Ring has looped around the
9255 *		ring.
9256 *
9257 *		At initialization time, this value is set to 0. On the
9258 *		first loop, this value is set to 1. After the max value is
9259 *		reached allowed by the number of bits for this field, the
9260 *		count value continues with 0 again.
9261 *
9262 *		In case SW is the consumer of the ring entries, it can
9263 *		use this field to figure out up to where the producer of
9264 *		entries has created new entries. This eliminates the need to
9265 *		check where the head pointer' of the ring is located once
9266 *		the SW starts processing an interrupt indicating that new
9267 *		entries have been put into this ring...
9268 *
9269 *		Also note that SW if it wants only needs to look at the
9270 *		LSB bit of this count value.
9271 */
9272
9273#define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN		BIT(8)
9274#define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP		BIT(9)
9275#define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP		BIT(10)
9276#define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER		BIT(11)
9277#define HAL_CE_DST_STATUS_DESC_FLAGS_LEN		GENMASK(31, 16)
9278
9279#define HAL_CE_DST_STATUS_DESC_META_INFO_DATA		GENMASK(15, 0)
9280#define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID	GENMASK(27, 20)
9281#define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT	HAL_SRNG_DESC_LOOP_CNT
9282
9283struct hal_ce_srng_dst_status_desc {
9284	uint32_t flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */
9285	uint32_t toeplitz_hash0;
9286	uint32_t toeplitz_hash1;
9287	uint32_t meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */
9288} __packed;
9289
9290/* hal_ce_srng_dst_status_desc
9291 *
9292 * ce_res_5
9293 *		Reserved
9294 *
9295 * toeplitz_en
9296 *
9297 * src_swap
9298 *		Source memory buffer swapped
9299 *
9300 * dest_swap
9301 *		Destination  memory buffer swapped
9302 *
9303 * gather
9304 *		Gather of multiple copy engine source descriptors to one
9305 *		destination enabled
9306 *
9307 * ce_res_6
9308 *		Reserved
9309 *
9310 * length
9311 *		Sum of all the Lengths of the source descriptor in the
9312 *		gather chain
9313 *
9314 * toeplitz_hash_0
9315 *		32 LS bits of 64 bit Toeplitz LFSR hash result
9316 *
9317 * toeplitz_hash_1
9318 *		32 MS bits of 64 bit Toeplitz LFSR hash result
9319 *
9320 * fw_metadata
9321 *		Meta data used by FW
9322 *		In case of gather field in first source ring entry of
9323 *		the gather copy cycle in taken into account.
9324 *
9325 * ce_res_7
9326 *		Reserved
9327 *
9328 * ring_id
9329 *		The buffer pointer ring ID.
9330 *		0 refers to the IDLE ring
9331 *		1 - N refers to other rings
9332 *		Helps with debugging when dumping ring contents.
9333 *
9334 * looping_count
9335 *		A count value that indicates the number of times the
9336 *		producer of entries into the Ring has looped around the
9337 *		ring.
9338 *
9339 *		At initialization time, this value is set to 0. On the
9340 *		first loop, this value is set to 1. After the max value is
9341 *		reached allowed by the number of bits for this field, the
9342 *		count value continues with 0 again.
9343 *
9344 *		In case SW is the consumer of the ring entries, it can
9345 *		use this field to figure out up to where the producer of
9346 *		entries has created new entries. This eliminates the need to
9347 *		check where the head pointer' of the ring is located once
9348 *		the SW starts processing an interrupt indicating that new
9349 *		entries have been put into this ring...
9350 *
9351 *		Also note that SW if it wants only needs to look at the
9352 *			LSB bit of this count value.
9353 */
9354
9355#define HAL_TX_RATE_STATS_INFO0_VALID		BIT(0)
9356#define HAL_TX_RATE_STATS_INFO0_BW		GENMASK(2, 1)
9357#define HAL_TX_RATE_STATS_INFO0_PKT_TYPE	GENMASK(6, 3)
9358#define HAL_TX_RATE_STATS_INFO0_STBC		BIT(7)
9359#define HAL_TX_RATE_STATS_INFO0_LDPC		BIT(8)
9360#define HAL_TX_RATE_STATS_INFO0_SGI		GENMASK(10, 9)
9361#define HAL_TX_RATE_STATS_INFO0_MCS		GENMASK(14, 11)
9362#define HAL_TX_RATE_STATS_INFO0_OFDMA_TX	BIT(15)
9363#define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU	GENMASK(27, 16)
9364
9365enum hal_tx_rate_stats_bw {
9366	HAL_TX_RATE_STATS_BW_20,
9367	HAL_TX_RATE_STATS_BW_40,
9368	HAL_TX_RATE_STATS_BW_80,
9369	HAL_TX_RATE_STATS_BW_160,
9370};
9371
9372enum hal_tx_rate_stats_pkt_type {
9373	HAL_TX_RATE_STATS_PKT_TYPE_11A,
9374	HAL_TX_RATE_STATS_PKT_TYPE_11B,
9375	HAL_TX_RATE_STATS_PKT_TYPE_11N,
9376	HAL_TX_RATE_STATS_PKT_TYPE_11AC,
9377	HAL_TX_RATE_STATS_PKT_TYPE_11AX,
9378};
9379
9380enum hal_tx_rate_stats_sgi {
9381	HAL_TX_RATE_STATS_SGI_08US,
9382	HAL_TX_RATE_STATS_SGI_04US,
9383	HAL_TX_RATE_STATS_SGI_16US,
9384	HAL_TX_RATE_STATS_SGI_32US,
9385};
9386
9387struct hal_tx_rate_stats {
9388	uint32_t info0;
9389	uint32_t tsf;
9390} __packed;
9391
9392struct hal_wbm_link_desc {
9393	struct ath12k_buffer_addr buf_addr_info;
9394} __packed;
9395
9396/* hal_wbm_link_desc
9397 *
9398 *	Producer: WBM
9399 *	Consumer: WBM
9400 *
9401 * buf_addr_info
9402 *		Details of the physical address of a buffer or MSDU
9403 *		link descriptor.
9404 */
9405
9406enum hal_wbm_rel_src_module {
9407	HAL_WBM_REL_SRC_MODULE_TQM,
9408	HAL_WBM_REL_SRC_MODULE_RXDMA,
9409	HAL_WBM_REL_SRC_MODULE_REO,
9410	HAL_WBM_REL_SRC_MODULE_FW,
9411	HAL_WBM_REL_SRC_MODULE_SW,
9412};
9413
9414enum hal_wbm_rel_desc_type {
9415	HAL_WBM_REL_DESC_TYPE_REL_MSDU,
9416	HAL_WBM_REL_DESC_TYPE_MSDU_LINK,
9417	HAL_WBM_REL_DESC_TYPE_MPDU_LINK,
9418	HAL_WBM_REL_DESC_TYPE_MSDU_EXT,
9419	HAL_WBM_REL_DESC_TYPE_QUEUE_EXT,
9420};
9421
9422/* hal_wbm_rel_desc_type
9423 *
9424 * msdu_buffer
9425 *	The address points to an MSDU buffer
9426 *
9427 * msdu_link_descriptor
9428 *	The address points to an Tx MSDU link descriptor
9429 *
9430 * mpdu_link_descriptor
9431 *	The address points to an MPDU link descriptor
9432 *
9433 * msdu_ext_descriptor
9434 *	The address points to an MSDU extension descriptor
9435 *
9436 * queue_ext_descriptor
9437 *	The address points to an TQM queue extension descriptor. WBM should
9438 *	treat this is the same way as a link descriptor.
9439 */
9440
9441enum hal_wbm_rel_bm_act {
9442	HAL_WBM_REL_BM_ACT_PUT_IN_IDLE,
9443	HAL_WBM_REL_BM_ACT_REL_MSDU,
9444};
9445
9446/* hal_wbm_rel_bm_act
9447 *
9448 * put_in_idle_list
9449 *	Put the buffer or descriptor back in the idle list. In case of MSDU or
9450 *	MDPU link descriptor, BM does not need to check to release any
9451 *	individual MSDU buffers.
9452 *
9453 * release_msdu_list
9454 *	This BM action can only be used in combination with desc_type being
9455 *	msdu_link_descriptor. Field first_msdu_index points out which MSDU
9456 *	pointer in the MSDU link descriptor is the first of an MPDU that is
9457 *	released. BM shall release all the MSDU buffers linked to this first
9458 *	MSDU buffer pointer. All related MSDU buffer pointer entries shall be
9459 *	set to value 0, which represents the 'NULL' pointer. When all MSDU
9460 *	buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link
9461 *	descriptor itself shall also be released.
9462 */
9463
9464#define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE		GENMASK(2, 0)
9465#define HAL_WBM_RELEASE_INFO0_BM_ACTION			GENMASK(5, 3)
9466#define HAL_WBM_RELEASE_INFO0_DESC_TYPE			GENMASK(8, 6)
9467#define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX		GENMASK(12, 9)
9468#define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON	GENMASK(16, 13)
9469#define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON		GENMASK(18, 17)
9470#define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE		GENMASK(23, 19)
9471#define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON		GENMASK(25, 24)
9472#define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE		GENMASK(30, 26)
9473#define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR	BIT(31)
9474
9475#define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER		GENMASK(23, 0)
9476#define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT		GENMASK(30, 24)
9477
9478#define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI		GENMASK(7, 0)
9479#define HAL_WBM_RELEASE_INFO2_SW_REL_DETAILS_VALID	BIT(8)
9480#define HAL_WBM_RELEASE_INFO2_FIRST_MSDU		BIT(9)
9481#define HAL_WBM_RELEASE_INFO2_LAST_MSDU			BIT(10)
9482#define HAL_WBM_RELEASE_INFO2_MSDU_IN_AMSDU		BIT(11)
9483#define HAL_WBM_RELEASE_INFO2_FW_TX_NOTIF_FRAME		BIT(12)
9484#define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP		GENMASK(31, 13)
9485
9486#define HAL_WBM_RELEASE_INFO3_PEER_ID			GENMASK(15, 0)
9487#define HAL_WBM_RELEASE_INFO3_TID			GENMASK(19, 16)
9488#define HAL_WBM_RELEASE_INFO3_RING_ID			GENMASK(27, 20)
9489#define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT		GENMASK(31, 28)
9490
9491#define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS		GENMASK(12, 9)
9492#define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON	GENMASK(16, 13)
9493#define HAL_WBM_REL_HTT_TX_COMP_INFO0_EXP_FRAME		BIT(17)
9494
9495struct hal_wbm_release_ring {
9496	struct ath12k_buffer_addr buf_addr_info;
9497	uint32_t info0;
9498	uint32_t info1;
9499	uint32_t info2;
9500	struct hal_tx_rate_stats rate_stats;
9501	uint32_t info3;
9502} __packed;
9503
9504/* hal_wbm_release_ring
9505 *
9506 *	Producer: SW/TQM/RXDMA/REO/SWITCH
9507 *	Consumer: WBM/SW/FW
9508 *
9509 * HTT tx status is overlaid on wbm_release ring on 4-byte words 2, 3, 4 and 5
9510 * for software based completions.
9511 *
9512 * buf_addr_info
9513 *	Details of the physical address of the buffer or link descriptor.
9514 *
9515 * release_source_module
9516 *	Indicates which module initiated the release of this buffer/descriptor.
9517 *	Values are defined in enum %HAL_WBM_REL_SRC_MODULE_.
9518 *
9519 * bm_action
9520 *	Field only valid when the field return_buffer_manager in
9521 *	Released_buff_or_desc_addr_info indicates:
9522 *		WBM_IDLE_BUF_LIST / WBM_IDLE_DESC_LIST
9523 *	Values are defined in enum %HAL_WBM_REL_BM_ACT_.
9524 *
9525 * buffer_or_desc_type
9526 *	Field only valid when WBM is marked as the return_buffer_manager in
9527 *	the Released_Buffer_address_info. Indicates that type of buffer or
9528 *	descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE.
9529 *
9530 * first_msdu_index
9531 *	Field only valid for the bm_action release_msdu_list. The index of the
9532 *	first MSDU in an MSDU link descriptor all belonging to the same MPDU.
9533 *
9534 * tqm_release_reason
9535 *	Field only valid when Release_source_module is set to release_source_TQM
9536 *	Release reasons are defined in enum %HAL_WBM_TQM_REL_REASON_.
9537 *
9538 * rxdma_push_reason
9539 * reo_push_reason
9540 *	Indicates why rxdma/reo pushed the frame to this ring and values are
9541 *	defined in enum %HAL_REO_DEST_RING_PUSH_REASON_.
9542 *
9543 * rxdma_error_code
9544 *	Field only valid when 'rxdma_push_reason' set to 'error_detected'.
9545 *	Values are defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_.
9546 *
9547 * reo_error_code
9548 *	Field only valid when 'reo_push_reason' set to 'error_detected'. Values
9549 *	are defined in enum %HAL_REO_DEST_RING_ERROR_CODE_.
9550 *
9551 * wbm_internal_error
9552 *	Is set when WBM got a buffer pointer but the action was to push it to
9553 *	the idle link descriptor ring or do link related activity OR
9554 *	Is set when WBM got a link buffer pointer but the action was to push it
9555 *	to the buffer descriptor ring.
9556 *
9557 * tqm_status_number
9558 *	The value in this field is equal to tqm_cmd_number in TQM command. It is
9559 *	used to correlate the statu with TQM commands. Only valid when
9560 *	release_source_module is TQM.
9561 *
9562 * transmit_count
9563 *	The number of times the frame has been transmitted, valid only when
9564 *	release source in TQM.
9565 *
9566 * ack_frame_rssi
9567 *	This field is only valid when the source is TQM. If this frame is
9568 *	removed as the result of the reception of an ACK or BA, this field
9569 *	indicates the RSSI of the received ACK or BA frame.
9570 *
9571 * sw_release_details_valid
9572 *	This is set when WMB got a 'release_msdu_list' command from TQM and
9573 *	return buffer manager is not WMB. WBM will then de-aggregate all MSDUs
9574 *	and pass them one at a time on to the 'buffer owner'.
9575 *
9576 * first_msdu
9577 *	Field only valid when SW_release_details_valid is set.
9578 *	When set, this MSDU is the first MSDU pointed to in the
9579 *	'release_msdu_list' command.
9580 *
9581 * last_msdu
9582 *	Field only valid when SW_release_details_valid is set.
9583 *	When set, this MSDU is the last MSDU pointed to in the
9584 *	'release_msdu_list' command.
9585 *
9586 * msdu_part_of_amsdu
9587 *	Field only valid when SW_release_details_valid is set.
9588 *	When set, this MSDU was part of an A-MSDU in MPDU
9589 *
9590 * fw_tx_notify_frame
9591 *	Field only valid when SW_release_details_valid is set.
9592 *
9593 * buffer_timestamp
9594 *	Field only valid when SW_release_details_valid is set.
9595 *	This is the Buffer_timestamp field from the
9596 *	Timestamp in units of 1024 us
9597 *
9598 * struct hal_tx_rate_stats rate_stats
9599 *	Details for command execution tracking purposes.
9600 *
9601 * sw_peer_id
9602 * tid
9603 *	Field only valid when Release_source_module is set to
9604 *	release_source_TQM
9605 *
9606 *	1) Release of msdu buffer due to drop_frame = 1. Flow is
9607 *	not fetched and hence sw_peer_id and tid = 0
9608 *
9609 *	buffer_or_desc_type = e_num 0
9610 *	MSDU_rel_buffertqm_release_reason = e_num 1
9611 *	tqm_rr_rem_cmd_rem
9612 *
9613 *	2) Release of msdu buffer due to Flow is not fetched and
9614 *	hence sw_peer_id and tid = 0
9615 *
9616 *	buffer_or_desc_type = e_num 0
9617 *	MSDU_rel_buffertqm_release_reason = e_num 1
9618 *	tqm_rr_rem_cmd_rem
9619 *
9620 *	3) Release of msdu link due to remove_mpdu or acked_mpdu
9621 *	command.
9622 *
9623 *	buffer_or_desc_type = e_num1
9624 *	msdu_link_descriptortqm_release_reason can be:e_num 1
9625 *	tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx
9626 *	e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged
9627 *
9628 *	This field represents the TID from the TX_MSDU_FLOW
9629 *	descriptor or TX_MPDU_QUEUE descriptor
9630 *
9631 * rind_id
9632 *	For debugging.
9633 *	This field is filled in by the SRNG module.
9634 *	It help to identify the ring that is being looked
9635 *
9636 * looping_count
9637 *	A count value that indicates the number of times the
9638 *	producer of entries into the Buffer Manager Ring has looped
9639 *	around the ring.
9640 *
9641 *	At initialization time, this value is set to 0. On the
9642 *	first loop, this value is set to 1. After the max value is
9643 *	reached allowed by the number of bits for this field, the
9644 *	count value continues with 0 again.
9645 *
9646 *	In case SW is the consumer of the ring entries, it can
9647 *	use this field to figure out up to where the producer of
9648 *	entries has created new entries. This eliminates the need to
9649 *	check where the head pointer' of the ring is located once
9650 *	the SW starts processing an interrupt indicating that new
9651 *	entries have been put into this ring...
9652 *
9653 *	Also note that SW if it wants only needs to look at the
9654 *	LSB bit of this count value.
9655 */
9656
9657/**
9658 * enum hal_wbm_tqm_rel_reason - TQM release reason code
9659 * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame
9660 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW
9661 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus
9662 *	initiated by sw.
9663 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus
9664 *	initiated by sw.
9665 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or
9666 *	mpdus.
9667 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by
9668 *	fw with fw_reason1.
9669 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by
9670 *	fw with fw_reason2.
9671 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by
9672 *	fw with fw_reason3.
9673 */
9674enum hal_wbm_tqm_rel_reason {
9675	HAL_WBM_TQM_REL_REASON_FRAME_ACKED,
9676	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU,
9677	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX,
9678	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX,
9679	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES,
9680	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1,
9681	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2,
9682	HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3,
9683};
9684
9685struct hal_wbm_buffer_ring {
9686	struct ath12k_buffer_addr buf_addr_info;
9687};
9688
9689enum hal_desc_owner {
9690	HAL_DESC_OWNER_WBM,
9691	HAL_DESC_OWNER_SW,
9692	HAL_DESC_OWNER_TQM,
9693	HAL_DESC_OWNER_RXDMA,
9694	HAL_DESC_OWNER_REO,
9695	HAL_DESC_OWNER_SWITCH,
9696};
9697
9698enum hal_desc_buf_type {
9699	HAL_DESC_BUF_TYPE_TX_MSDU_LINK,
9700	HAL_DESC_BUF_TYPE_TX_MPDU_LINK,
9701	HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD,
9702	HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT,
9703	HAL_DESC_BUF_TYPE_TX_FLOW,
9704	HAL_DESC_BUF_TYPE_TX_BUFFER,
9705	HAL_DESC_BUF_TYPE_RX_MSDU_LINK,
9706	HAL_DESC_BUF_TYPE_RX_MPDU_LINK,
9707	HAL_DESC_BUF_TYPE_RX_REO_QUEUE,
9708	HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT,
9709	HAL_DESC_BUF_TYPE_RX_BUFFER,
9710	HAL_DESC_BUF_TYPE_IDLE_LINK,
9711};
9712
9713#define HAL_DESC_REO_OWNED		4
9714#define HAL_DESC_REO_QUEUE_DESC		8
9715#define HAL_DESC_REO_QUEUE_EXT_DESC	9
9716#define HAL_DESC_REO_NON_QOS_TID	16
9717
9718#define HAL_DESC_HDR_INFO0_OWNER	GENMASK(3, 0)
9719#define HAL_DESC_HDR_INFO0_BUF_TYPE	GENMASK(7, 4)
9720#define HAL_DESC_HDR_INFO0_DBG_RESERVED	GENMASK(31, 8)
9721
9722struct hal_desc_header {
9723	uint32_t info0;
9724} __packed;
9725
9726struct hal_rx_mpdu_link_ptr {
9727	struct ath12k_buffer_addr addr_info;
9728} __packed;
9729
9730struct hal_rx_msdu_details {
9731	struct ath12k_buffer_addr buf_addr_info;
9732	struct rx_msdu_desc rx_msdu_info;
9733} __packed;
9734
9735#define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER		GENMASK(15, 0)
9736#define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK		BIT(16)
9737
9738struct hal_rx_msdu_link {
9739	struct hal_desc_header desc_hdr;
9740	struct ath12k_buffer_addr buf_addr_info;
9741	uint32_t info0;
9742	uint32_t pn[4];
9743	struct hal_rx_msdu_details msdu_link[6];
9744} __packed;
9745
9746struct hal_rx_reo_queue_ext {
9747	struct hal_desc_header desc_hdr;
9748	uint32_t rsvd;
9749	struct hal_rx_mpdu_link_ptr mpdu_link[15];
9750} __packed;
9751
9752/* hal_rx_reo_queue_ext
9753 *	Consumer: REO
9754 *	Producer: REO
9755 *
9756 * descriptor_header
9757 *	Details about which module owns this struct.
9758 *
9759 * mpdu_link
9760 *	Pointer to the next MPDU_link descriptor in the MPDU queue.
9761 */
9762
9763enum hal_rx_reo_queue_pn_size {
9764	HAL_RX_REO_QUEUE_PN_SIZE_24,
9765	HAL_RX_REO_QUEUE_PN_SIZE_48,
9766	HAL_RX_REO_QUEUE_PN_SIZE_128,
9767};
9768
9769#define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER		GENMASK(15, 0)
9770
9771#define HAL_RX_REO_QUEUE_INFO0_VLD			BIT(0)
9772#define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER	GENMASK(2, 1)
9773#define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION	BIT(3)
9774#define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN		BIT(4)
9775#define HAL_RX_REO_QUEUE_INFO0_AC			GENMASK(6, 5)
9776#define HAL_RX_REO_QUEUE_INFO0_BAR			BIT(7)
9777#define HAL_RX_REO_QUEUE_INFO0_RETRY			BIT(8)
9778#define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE		BIT(9)
9779#define HAL_RX_REO_QUEUE_INFO0_OOR_MODE			BIT(10)
9780#define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE		GENMASK(18, 11)
9781#define HAL_RX_REO_QUEUE_INFO0_PN_CHECK			BIT(19)
9782#define HAL_RX_REO_QUEUE_INFO0_EVEN_PN			BIT(20)
9783#define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN		BIT(21)
9784#define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE		BIT(22)
9785#define HAL_RX_REO_QUEUE_INFO0_PN_SIZE			GENMASK(24, 23)
9786#define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG		BIT(25)
9787
9788#define HAL_RX_REO_QUEUE_INFO1_SVLD			BIT(0)
9789#define HAL_RX_REO_QUEUE_INFO1_SSN			GENMASK(12, 1)
9790#define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX		GENMASK(20, 13)
9791#define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR		BIT(21)
9792#define HAL_RX_REO_QUEUE_INFO1_PN_ERR			BIT(22)
9793#define HAL_RX_REO_QUEUE_INFO1_PN_VALID			BIT(31)
9794
9795#define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT		GENMASK(6, 0)
9796#define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT		(31, 7)
9797
9798#define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT		GENMASK(9, 4)
9799#define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT	GENMASK(15, 10)
9800#define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT		GENMASK(31, 16)
9801
9802#define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT	GENMASK(23, 0)
9803#define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT		GENMASK(31, 24)
9804
9805#define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT	GENMASK(11, 0)
9806#define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K		GENMASK(15, 12)
9807#define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT		GENMASK(31, 16)
9808
9809struct hal_rx_reo_queue {
9810	struct hal_desc_header desc_hdr;
9811	uint32_t rx_queue_num;
9812	uint32_t info0;
9813	uint32_t info1;
9814	uint32_t pn[4];
9815	uint32_t last_rx_enqueue_timestamp;
9816	uint32_t last_rx_dequeue_timestamp;
9817	uint32_t next_aging_queue[2];
9818	uint32_t prev_aging_queue[2];
9819	uint32_t rx_bitmap[8];
9820	uint32_t info2;
9821	uint32_t info3;
9822	uint32_t info4;
9823	uint32_t processed_mpdus;
9824	uint32_t processed_msdus;
9825	uint32_t processed_total_bytes;
9826	uint32_t info5;
9827	uint32_t rsvd[3];
9828	struct hal_rx_reo_queue_ext ext_desc[];
9829} __packed;
9830
9831/* hal_rx_reo_queue
9832 *
9833 * descriptor_header
9834 *	Details about which module owns this struct. Note that sub field
9835 *	Buffer_type shall be set to receive_reo_queue_descriptor.
9836 *
9837 * receive_queue_number
9838 *	Indicates the MPDU queue ID to which this MPDU link descriptor belongs.
9839 *
9840 * vld
9841 *	Valid bit indicating a session is established and the queue descriptor
9842 *	is valid.
9843 * associated_link_descriptor_counter
9844 *	Indicates which of the 3 link descriptor counters shall be incremented
9845 *	or decremented when link descriptors are added or removed from this
9846 *	flow queue.
9847 * disable_duplicate_detection
9848 *	When set, do not perform any duplicate detection.
9849 * soft_reorder_enable
9850 *	When set, REO has been instructed to not perform the actual re-ordering
9851 *	of frames for this queue, but just to insert the reorder opcodes.
9852 * ac
9853 *	Indicates the access category of the queue descriptor.
9854 * bar
9855 *	Indicates if BAR has been received.
9856 * retry
9857 *	Retry bit is checked if this bit is set.
9858 * chk_2k_mode
9859 *	Indicates what type of operation is expected from Reo when the received
9860 *	frame SN falls within the 2K window.
9861 * oor_mode
9862 *	Indicates what type of operation is expected when the received frame
9863 *	falls within the OOR window.
9864 * ba_window_size
9865 *	Indicates the negotiated (window size + 1). Max of 256 bits.
9866 *
9867 *	A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA
9868 *	session, with window size of 0). The 3 values here are the main values
9869 *	validated, but other values should work as well.
9870 *
9871 *	A BA window size of 0 (=> one frame entry bitmat), means that there is
9872 *	no additional rx_reo_queue_ext desc. following rx_reo_queue in memory.
9873 *	A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext.
9874 *	A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext.
9875 *	A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext.
9876 * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable,
9877 * pn_size
9878 *	REO shall perform the PN increment check, even number check, uneven
9879 *	number check, PN error check and size of the PN field check.
9880 * ignore_ampdu_flag
9881 *	REO shall ignore the ampdu_flag on entrance descriptor for this queue.
9882 *
9883 * svld
9884 *	Sequence number in next field is valid one.
9885 * ssn
9886 *	 Starting Sequence number of the session.
9887 * current_index
9888 *	Points to last forwarded packet
9889 * seq_2k_error_detected_flag
9890 *	REO has detected a 2k error jump in the sequence number and from that
9891 *	moment forward, all new frames are forwarded directly to FW, without
9892 *	duplicate detect, reordering, etc.
9893 * pn_error_detected_flag
9894 *	REO has detected a PN error.
9895 */
9896
9897#define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI		GENMASK(7, 0)
9898#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM		BIT(8)
9899#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD			BIT(9)
9900#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT	BIT(10)
9901#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION	BIT(11)
9902#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN		BIT(12)
9903#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC			BIT(13)
9904#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR			BIT(14)
9905#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY			BIT(15)
9906#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE		BIT(16)
9907#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE			BIT(17)
9908#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE		BIT(18)
9909#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK			BIT(19)
9910#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN			BIT(20)
9911#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN		BIT(21)
9912#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE		BIT(22)
9913#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE			BIT(23)
9914#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG		BIT(24)
9915#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD			BIT(25)
9916#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN			BIT(26)
9917#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR		BIT(27)
9918#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR			BIT(28)
9919#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID			BIT(29)
9920#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN			BIT(30)
9921
9922#define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER		GENMASK(15, 0)
9923#define HAL_REO_UPD_RX_QUEUE_INFO1_VLD				BIT(16)
9924#define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER	GENMASK(18, 17)
9925#define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION		BIT(19)
9926#define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN		BIT(20)
9927#define HAL_REO_UPD_RX_QUEUE_INFO1_AC				GENMASK(22, 21)
9928#define HAL_REO_UPD_RX_QUEUE_INFO1_BAR				BIT(23)
9929#define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY			BIT(24)
9930#define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE		BIT(25)
9931#define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE			BIT(26)
9932#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK			BIT(27)
9933#define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN			BIT(28)
9934#define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN			BIT(29)
9935#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE		BIT(30)
9936#define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG		BIT(31)
9937
9938#define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE		GENMASK(7, 0)
9939#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE			GENMASK(9, 8)
9940#define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD				BIT(10)
9941#define HAL_REO_UPD_RX_QUEUE_INFO2_SSN				GENMASK(22, 11)
9942#define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR			BIT(23)
9943#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR			BIT(24)
9944#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID			BIT(25)
9945
9946struct hal_reo_update_rx_queue {
9947	struct hal_reo_cmd_hdr cmd;
9948	uint32_t queue_addr_lo;
9949	uint32_t info0;
9950	uint32_t info1;
9951	uint32_t info2;
9952	uint32_t pn[4];
9953} __packed;
9954
9955#define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE		BIT(0)
9956#define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX	GENMASK(2, 1)
9957
9958struct hal_reo_unblock_cache {
9959	struct hal_reo_cmd_hdr cmd;
9960	uint32_t info0;
9961	uint32_t rsvd[7];
9962} __packed;
9963
9964enum hal_reo_exec_status {
9965	HAL_REO_EXEC_STATUS_SUCCESS,
9966	HAL_REO_EXEC_STATUS_BLOCKED,
9967	HAL_REO_EXEC_STATUS_FAILED,
9968	HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED,
9969};
9970
9971#define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM	GENMASK(15, 0)
9972#define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME	GENMASK(25, 16)
9973#define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS	GENMASK(27, 26)
9974
9975#define HAL_HASH_ROUTING_RING_TCL 0
9976#define HAL_HASH_ROUTING_RING_SW1 1
9977#define HAL_HASH_ROUTING_RING_SW2 2
9978#define HAL_HASH_ROUTING_RING_SW3 3
9979#define HAL_HASH_ROUTING_RING_SW4 4
9980#define HAL_HASH_ROUTING_RING_REL 5
9981#define HAL_HASH_ROUTING_RING_FW  6
9982
9983struct hal_reo_status_hdr {
9984	uint32_t info0;
9985	uint32_t timestamp;
9986} __packed;
9987
9988/* hal_reo_status_hdr
9989 *		Producer: REO
9990 *		Consumer: SW
9991 *
9992 * status_num
9993 *		The value in this field is equal to value of the reo command
9994 *		number. This field helps to correlate the statuses with the REO
9995 *		commands.
9996 *
9997 * execution_time (in us)
9998 *		The amount of time REO took to execute the command. Note that
9999 *		this time does not include the duration of the command waiting
10000 *		in the command ring, before the execution started.
10001 *
10002 * execution_status
10003 *		Execution status of the command. Values are defined in
10004 *		enum %HAL_REO_EXEC_STATUS_.
10005 */
10006#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN		GENMASK(11, 0)
10007#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX		GENMASK(19, 12)
10008
10009#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT		GENMASK(6, 0)
10010#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT		GENMASK(31, 7)
10011
10012#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT	GENMASK(9, 4)
10013#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT		GENMASK(15, 10)
10014#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT	GENMASK(31, 16)
10015
10016#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT		GENMASK(23, 0)
10017#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT	GENMASK(31, 24)
10018
10019#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU	GENMASK(11, 0)
10020#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K	GENMASK(15, 12)
10021#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT		GENMASK(31, 16)
10022
10023#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT	GENMASK(31, 28)
10024
10025struct hal_reo_get_queue_stats_status {
10026	struct hal_reo_status_hdr hdr;
10027	uint32_t info0;
10028	uint32_t pn[4];
10029	uint32_t last_rx_enqueue_timestamp;
10030	uint32_t last_rx_dequeue_timestamp;
10031	uint32_t rx_bitmap[8];
10032	uint32_t info1;
10033	uint32_t info2;
10034	uint32_t info3;
10035	uint32_t num_mpdu_frames;
10036	uint32_t num_msdu_frames;
10037	uint32_t total_bytes;
10038	uint32_t info4;
10039	uint32_t info5;
10040} __packed;
10041
10042/* hal_reo_get_queue_stats_status
10043 *		Producer: REO
10044 *		Consumer: SW
10045 *
10046 * status_hdr
10047 *		Details that can link this status with the original command. It
10048 *		also contains info on how long REO took to execute this command.
10049 *
10050 * ssn
10051 *		Starting Sequence number of the session, this changes whenever
10052 *		window moves (can be filled by SW then maintained by REO).
10053 *
10054 * current_index
10055 *		Points to last forwarded packet.
10056 *
10057 * pn
10058 *		Bits of the PN number.
10059 *
10060 * last_rx_enqueue_timestamp
10061 * last_rx_dequeue_timestamp
10062 *		Timestamp of arrival of the last MPDU for this queue and
10063 *		Timestamp of forwarding an MPDU accordingly.
10064 *
10065 * rx_bitmap
10066 *		When a bit is set, the corresponding frame is currently held
10067 *		in the re-order queue. The bitmap  is Fully managed by HW.
10068 *
10069 * current_mpdu_count
10070 * current_msdu_count
10071 *		The number of MPDUs and MSDUs in the queue.
10072 *
10073 * timeout_count
10074 *		The number of times REO started forwarding frames even though
10075 *		there is a hole in the bitmap. Forwarding reason is timeout.
10076 *
10077 * forward_due_to_bar_count
10078 *		The number of times REO started forwarding frames even though
10079 *		there is a hole in the bitmap. Fwd reason is reception of BAR.
10080 *
10081 * duplicate_count
10082 *		The number of duplicate frames that have been detected.
10083 *
10084 * frames_in_order_count
10085 *		The number of frames that have been received in order (without
10086 *		a hole that prevented them from being forwarded immediately).
10087 *
10088 * bar_received_count
10089 *		The number of times a BAR frame is received.
10090 *
10091 * mpdu_frames_processed_count
10092 * msdu_frames_processed_count
10093 *		The total number of MPDU/MSDU frames that have been processed.
10094 *
10095 * total_bytes
10096 *		An approximation of the number of bytes received for this queue.
10097 *
10098 * late_receive_mpdu_count
10099 *		The number of MPDUs received after the window had already moved
10100 *		on. The 'late' sequence window is defined as
10101 *		(Window SSN - 256) - (Window SSN - 1).
10102 *
10103 * window_jump_2k
10104 *		The number of times the window moved more than 2K
10105 *
10106 * hole_count
10107 *		The number of times a hole was created in the receive bitmap.
10108 *
10109 * looping_count
10110 *		A count value that indicates the number of times the producer of
10111 *		entries into this Ring has looped around the ring.
10112 */
10113
10114#define HAL_REO_STATUS_LOOP_CNT			GENMASK(31, 28)
10115
10116#define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED	BIT(0)
10117#define HAL_REO_FLUSH_QUEUE_INFO0_RSVD		GENMASK(31, 1)
10118#define HAL_REO_FLUSH_QUEUE_INFO1_RSVD		GENMASK(27, 0)
10119
10120struct hal_reo_flush_queue_status {
10121	struct hal_reo_status_hdr hdr;
10122	uint32_t info0;
10123	uint32_t rsvd0[21];
10124	uint32_t info1;
10125} __packed;
10126
10127/* hal_reo_flush_queue_status
10128 *		Producer: REO
10129 *		Consumer: SW
10130 *
10131 * status_hdr
10132 *		Details that can link this status with the original command. It
10133 *		also contains info on how long REO took to execute this command.
10134 *
10135 * error_detected
10136 *		Status of blocking resource
10137 *
10138 *		0 - No error has been detected while executing this command
10139 *		1 - Error detected. The resource to be used for blocking was
10140 *		    already in use.
10141 *
10142 * looping_count
10143 *		A count value that indicates the number of times the producer of
10144 *		entries into this Ring has looped around the ring.
10145 */
10146
10147#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR			BIT(0)
10148#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE		GENMASK(2, 1)
10149#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT	BIT(8)
10150#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE	GENMASK(11, 9)
10151#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID	GENMASK(15, 12)
10152#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR		GENMASK(17, 16)
10153#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT		GENMASK(25, 18)
10154
10155struct hal_reo_flush_cache_status {
10156	struct hal_reo_status_hdr hdr;
10157	uint32_t info0;
10158	uint32_t rsvd0[21];
10159	uint32_t info1;
10160} __packed;
10161
10162/* hal_reo_flush_cache_status
10163 *		Producer: REO
10164 *		Consumer: SW
10165 *
10166 * status_hdr
10167 *		Details that can link this status with the original command. It
10168 *		also contains info on how long REO took to execute this command.
10169 *
10170 * error_detected
10171 *		Status for blocking resource handling
10172 *
10173 *		0 - No error has been detected while executing this command
10174 *		1 - An error in the blocking resource management was detected
10175 *
10176 * block_error_details
10177 *		only valid when error_detected is set
10178 *
10179 *		0 - No blocking related errors found
10180 *		1 - Blocking resource is already in use
10181 *		2 - Resource requested to be unblocked, was not blocked
10182 *
10183 * cache_controller_flush_status_hit
10184 *		The status that the cache controller returned on executing the
10185 *		flush command.
10186 *
10187 *		0 - miss; 1 - hit
10188 *
10189 * cache_controller_flush_status_desc_type
10190 *		Flush descriptor type
10191 *
10192 * cache_controller_flush_status_client_id
10193 *		Module who made the flush request
10194 *
10195 *		In REO, this is always 0
10196 *
10197 * cache_controller_flush_status_error
10198 *		Error condition
10199 *
10200 *		0 - No error found
10201 *		1 - HW interface is still busy
10202 *		2 - Line currently locked. Used for one line flush command
10203 *		3 - At least one line is still locked.
10204 *		    Used for cache flush command.
10205 *
10206 * cache_controller_flush_count
10207 *		The number of lines that were actually flushed out
10208 *
10209 * looping_count
10210 *		A count value that indicates the number of times the producer of
10211 *		entries into this Ring has looped around the ring.
10212 */
10213
10214#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR	BIT(0)
10215#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE		BIT(1)
10216
10217struct hal_reo_unblock_cache_status {
10218	struct hal_reo_status_hdr hdr;
10219	uint32_t info0;
10220	uint32_t rsvd0[21];
10221	uint32_t info1;
10222} __packed;
10223
10224/* hal_reo_unblock_cache_status
10225 *		Producer: REO
10226 *		Consumer: SW
10227 *
10228 * status_hdr
10229 *		Details that can link this status with the original command. It
10230 *		also contains info on how long REO took to execute this command.
10231 *
10232 * error_detected
10233 *		0 - No error has been detected while executing this command
10234 *		1 - The blocking resource was not in use, and therefore it could
10235 *		    not be unblocked.
10236 *
10237 * unblock_type
10238 *		Reference to the type of unblock command
10239 *		0 - Unblock a blocking resource
10240 *		1 - The entire cache usage is unblock
10241 *
10242 * looping_count
10243 *		A count value that indicates the number of times the producer of
10244 *		entries into this Ring has looped around the ring.
10245 */
10246
10247#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR		BIT(0)
10248#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY		BIT(1)
10249
10250#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT	GENMASK(15, 0)
10251#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT	GENMASK(31, 16)
10252
10253struct hal_reo_flush_timeout_list_status {
10254	struct hal_reo_status_hdr hdr;
10255	uint32_t info0;
10256	uint32_t info1;
10257	uint32_t rsvd0[20];
10258	uint32_t info2;
10259} __packed;
10260
10261/* hal_reo_flush_timeout_list_status
10262 *		Producer: REO
10263 *		Consumer: SW
10264 *
10265 * status_hdr
10266 *		Details that can link this status with the original command. It
10267 *		also contains info on how long REO took to execute this command.
10268 *
10269 * error_detected
10270 *		0 - No error has been detected while executing this command
10271 *		1 - Command not properly executed and returned with error
10272 *
10273 * timeout_list_empty
10274 *		When set, REO has depleted the timeout list and all entries are
10275 *		gone.
10276 *
10277 * release_desc_count
10278 *		Producer: SW; Consumer: REO
10279 *		The number of link descriptor released
10280 *
10281 * forward_buf_count
10282 *		Producer: SW; Consumer: REO
10283 *		The number of buffers forwarded to the REO destination rings
10284 *
10285 * looping_count
10286 *		A count value that indicates the number of times the producer of
10287 *		entries into this Ring has looped around the ring.
10288 */
10289
10290#define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX		GENMASK(1, 0)
10291#define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0	GENMASK(23, 0)
10292#define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1	GENMASK(23, 0)
10293#define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2	GENMASK(23, 0)
10294#define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM	GENMASK(25, 0)
10295
10296struct hal_reo_desc_thresh_reached_status {
10297	struct hal_reo_status_hdr hdr;
10298	uint32_t info0;
10299	uint32_t info1;
10300	uint32_t info2;
10301	uint32_t info3;
10302	uint32_t info4;
10303	uint32_t rsvd0[17];
10304	uint32_t info5;
10305} __packed;
10306
10307/* hal_reo_desc_thresh_reached_status
10308 *		Producer: REO
10309 *		Consumer: SW
10310 *
10311 * status_hdr
10312 *		Details that can link this status with the original command. It
10313 *		also contains info on how long REO took to execute this command.
10314 *
10315 * threshold_index
10316 *		The index of the threshold register whose value got reached
10317 *
10318 * link_descriptor_counter0
10319 * link_descriptor_counter1
10320 * link_descriptor_counter2
10321 * link_descriptor_counter_sum
10322 *		Value of the respective counters at generation of this message
10323 *
10324 * looping_count
10325 *		A count value that indicates the number of times the producer of
10326 *		entries into this Ring has looped around the ring.
10327 */
10328
10329struct hal_tcl_entrance_from_ppe_ring {
10330	uint32_t buffer_addr;
10331	uint32_t info0;
10332} __packed;
10333
10334struct hal_mon_buf_ring {
10335	uint32_t paddr_lo;
10336	uint32_t paddr_hi;
10337	uint64_t cookie;
10338};
10339
10340/* hal_mon_buf_ring
10341 *	Producer : SW
10342 *	Consumer : Monitor
10343 *
10344 * paddr_lo
10345 *	Lower 32-bit physical address of the buffer pointer from the source ring.
10346 * paddr_hi
10347 *	bit range 7-0 : upper 8 bit of the physical address.
10348 *	bit range 31-8 : reserved.
10349 * cookie
10350 *	Consumer: RxMon/TxMon 64 bit cookie of the buffers.
10351 */
10352
10353struct hal_mon_dest_desc {
10354	uint32_t cookie;
10355	uint32_t reserved;
10356	uint32_t ppdu_id;
10357	uint32_t info0;
10358};
10359
10360/* hal_mon_dest_ring
10361 *	Producer : TxMon/RxMon
10362 *	Consumer : SW
10363 * cookie
10364 *	bit 0 -17 buf_id to track the skb's vaddr.
10365 * ppdu_id
10366 *	Phy ppdu_id
10367 * end_offset
10368 *	The offset into status buffer where DMA ended, ie., offset to the last
10369 *	TLV + last TLV size.
10370 * flush_detected
10371 *	Indicates whether 'tx_flush' or 'rx_flush' occurred.
10372 * end_of_ppdu
10373 *	Indicates end of ppdu.
10374 * pmac_id
10375 *	Indicates PMAC that received from frame.
10376 * empty_descriptor
10377 *	This descriptor is written on flush or end of ppdu or end of status
10378 *	buffer.
10379 * ring_id
10380 *	updated by SRNG.
10381 * looping_count
10382 *	updated by SRNG.
10383 */
10384
10385#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
10386#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
10387#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
10388#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
10389
10390#define HAL_TX_ADDRX_EN			1
10391#define HAL_TX_ADDRY_EN			2
10392
10393#define HAL_TX_ADDR_SEARCH_DEFAULT	0
10394#define HAL_TX_ADDR_SEARCH_INDEX	1
10395
10396/*
10397 * Copy Engine
10398 */
10399
10400#define CE_COUNT_MAX 16
10401
10402/* Byte swap data words */
10403#define CE_ATTR_BYTE_SWAP_DATA 2
10404
10405/* no interrupt on copy completion */
10406#define CE_ATTR_DIS_INTR		8
10407
10408/* Host software's Copy Engine configuration. */
10409#ifdef __BIG_ENDIAN
10410#define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA
10411#else
10412#define CE_ATTR_FLAGS 0
10413#endif
10414
10415/* Threshold to poll for tx completion in case of Interrupt disabled CE's */
10416#define ATH12K_CE_USAGE_THRESHOLD 32
10417
10418/*
10419 * Directions for interconnect pipe configuration.
10420 * These definitions may be used during configuration and are shared
10421 * between Host and Target.
10422 *
10423 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
10424 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
10425 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
10426 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
10427 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
10428 * over the interconnect.
10429 */
10430#define PIPEDIR_NONE		0
10431#define PIPEDIR_IN		1 /* Target-->Host, WiFi Rx direction */
10432#define PIPEDIR_OUT		2 /* Host->Target, WiFi Tx direction */
10433#define PIPEDIR_INOUT		3 /* bidirectional */
10434#define PIPEDIR_INOUT_H2H	4 /* bidirectional, host to host */
10435
10436/* CE address/mask */
10437#define CE_HOST_IE_ADDRESS	0x00A1803C
10438#define CE_HOST_IE_2_ADDRESS	0x00A18040
10439#define CE_HOST_IE_3_ADDRESS	CE_HOST_IE_ADDRESS
10440
10441/* CE IE registers are different for IPQ5018 */
10442#define CE_HOST_IPQ5018_IE_ADDRESS		0x0841804C
10443#define CE_HOST_IPQ5018_IE_2_ADDRESS		0x08418050
10444#define CE_HOST_IPQ5018_IE_3_ADDRESS		CE_HOST_IPQ5018_IE_ADDRESS
10445
10446#define CE_HOST_IE_3_SHIFT	0xC
10447
10448#define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
10449
10450/*
10451 * Establish a mapping between a service/direction and a pipe.
10452 * Configuration information for a Copy Engine pipe and services.
10453 * Passed from Host to Target through QMI message and must be in
10454 * little endian format.
10455 */
10456struct service_to_pipe {
10457	uint32_t service_id;
10458	uint32_t pipedir;
10459	uint32_t pipenum;
10460};
10461
10462/*
10463 * Configuration information for a Copy Engine pipe.
10464 * Passed from Host to Target through QMI message during startup (one per CE).
10465 *
10466 * NOTE: Structure is shared between Host software and Target firmware!
10467 */
10468struct ce_pipe_config {
10469	uint32_t pipenum;
10470	uint32_t pipedir;
10471	uint32_t nentries;
10472	uint32_t nbytes_max;
10473	uint32_t flags;
10474	uint32_t reserved;
10475};
10476
10477/*
10478 * HTC
10479 */
10480
10481#define HTC_HDR_ENDPOINTID                       GENMASK(7, 0)
10482#define HTC_HDR_FLAGS                            GENMASK(15, 8)
10483#define HTC_HDR_PAYLOADLEN                       GENMASK(31, 16)
10484#define HTC_HDR_CONTROLBYTES0                    GENMASK(7, 0)
10485#define HTC_HDR_CONTROLBYTES1                    GENMASK(15, 8)
10486#define HTC_HDR_RESERVED                         GENMASK(31, 16)
10487
10488#define HTC_SVC_MSG_SERVICE_ID                   GENMASK(31, 16)
10489#define HTC_SVC_MSG_CONNECTIONFLAGS              GENMASK(15, 0)
10490#define HTC_SVC_MSG_SERVICEMETALENGTH            GENMASK(23, 16)
10491#define HTC_READY_MSG_CREDITCOUNT                GENMASK(31, 16)
10492#define HTC_READY_MSG_CREDITSIZE                 GENMASK(15, 0)
10493#define HTC_READY_MSG_MAXENDPOINTS               GENMASK(23, 16)
10494
10495#define HTC_READY_EX_MSG_HTCVERSION              GENMASK(7, 0)
10496#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE     GENMASK(15, 8)
10497
10498#define HTC_SVC_RESP_MSG_SERVICEID           GENMASK(31, 16)
10499#define HTC_SVC_RESP_MSG_STATUS              GENMASK(7, 0)
10500#define HTC_SVC_RESP_MSG_ENDPOINTID          GENMASK(15, 8)
10501#define HTC_SVC_RESP_MSG_MAXMSGSIZE          GENMASK(31, 16)
10502#define HTC_SVC_RESP_MSG_SERVICEMETALENGTH   GENMASK(7, 0)
10503
10504#define HTC_MSG_MESSAGEID                        GENMASK(15, 0)
10505#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS     GENMASK(31, 0)
10506#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV      GENMASK(7, 0)
10507#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0          GENMASK(15, 8)
10508#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1          GENMASK(23, 16)
10509#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2          GENMASK(31, 24)
10510
10511enum ath12k_htc_tx_flags {
10512	ATH12K_HTC_FLAG_NEED_CREDIT_UPDATE = 0x01,
10513	ATH12K_HTC_FLAG_SEND_BUNDLE        = 0x02
10514};
10515
10516enum ath12k_htc_rx_flags {
10517	ATH12K_HTC_FLAG_TRAILER_PRESENT = 0x02,
10518	ATH12K_HTC_FLAG_BUNDLE_MASK     = 0xF0
10519};
10520
10521
10522struct ath12k_htc_hdr {
10523	uint32_t htc_info;
10524	uint32_t ctrl_info;
10525} __packed __aligned(4);
10526
10527enum ath12k_htc_msg_id {
10528	ATH12K_HTC_MSG_READY_ID                = 1,
10529	ATH12K_HTC_MSG_CONNECT_SERVICE_ID      = 2,
10530	ATH12K_HTC_MSG_CONNECT_SERVICE_RESP_ID = 3,
10531	ATH12K_HTC_MSG_SETUP_COMPLETE_ID       = 4,
10532	ATH12K_HTC_MSG_SETUP_COMPLETE_EX_ID    = 5,
10533	ATH12K_HTC_MSG_SEND_SUSPEND_COMPLETE   = 6,
10534	ATH12K_HTC_MSG_NACK_SUSPEND	       = 7,
10535	ATH12K_HTC_MSG_WAKEUP_FROM_SUSPEND_ID  = 8,
10536};
10537
10538enum ath12k_htc_version {
10539	ATH12K_HTC_VERSION_2P0 = 0x00, /* 2.0 */
10540	ATH12K_HTC_VERSION_2P1 = 0x01, /* 2.1 */
10541};
10542
10543#define ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_MASK GENMASK(1, 0)
10544#define ATH12K_HTC_CONN_FLAGS_RECV_ALLOC GENMASK(15, 8)
10545
10546enum ath12k_htc_conn_flags {
10547	ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH    = 0x0,
10548	ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_ONE_HALF      = 0x1,
10549	ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS = 0x2,
10550	ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_UNITY         = 0x3,
10551	ATH12K_HTC_CONN_FLAGS_REDUCE_CREDIT_DRIBBLE	    = 0x4,
10552	ATH12K_HTC_CONN_FLAGS_DISABLE_CREDIT_FLOW_CTRL	    = 0x8,
10553};
10554
10555enum ath12k_htc_conn_svc_status {
10556	ATH12K_HTC_CONN_SVC_STATUS_SUCCESS      = 0,
10557	ATH12K_HTC_CONN_SVC_STATUS_NOT_FOUND    = 1,
10558	ATH12K_HTC_CONN_SVC_STATUS_FAILED       = 2,
10559	ATH12K_HTC_CONN_SVC_STATUS_NO_RESOURCES = 3,
10560	ATH12K_HTC_CONN_SVC_STATUS_NO_MORE_EP   = 4
10561};
10562
10563struct ath12k_htc_ready {
10564	uint32_t id_credit_count;
10565	uint32_t size_ep;
10566} __packed;
10567
10568struct ath12k_htc_ready_extended {
10569	struct ath12k_htc_ready base;
10570	uint32_t ver_bundle;
10571} __packed;
10572
10573struct ath12k_htc_conn_svc {
10574	uint32_t msg_svc_id;
10575	uint32_t flags_len;
10576} __packed;
10577
10578struct ath12k_htc_conn_svc_resp {
10579	uint32_t msg_svc_id;
10580	uint32_t flags_len;
10581	uint32_t svc_meta_pad;
10582} __packed;
10583
10584#define ATH12K_GLOBAL_DISABLE_CREDIT_FLOW BIT(1)
10585
10586struct ath12k_htc_setup_complete_extended {
10587	uint32_t msg_id;
10588	uint32_t flags;
10589	uint32_t max_msgs_per_bundled_recv;
10590} __packed;
10591
10592struct ath12k_htc_msg {
10593	uint32_t msg_svc_id;
10594	uint32_t flags_len;
10595} __packed __aligned(4);
10596
10597enum ath12k_htc_record_id {
10598	ATH12K_HTC_RECORD_NULL    = 0,
10599	ATH12K_HTC_RECORD_CREDITS = 1
10600};
10601
10602struct ath12k_htc_record_hdr {
10603	uint8_t id; /* @enum ath12k_htc_record_id */
10604	uint8_t len;
10605	uint8_t pad0;
10606	uint8_t pad1;
10607} __packed;
10608
10609struct ath12k_htc_credit_report {
10610	uint8_t eid; /* @enum ath12k_htc_ep_id */
10611	uint8_t credits;
10612	uint8_t pad0;
10613	uint8_t pad1;
10614} __packed;
10615
10616struct ath12k_htc_record {
10617	struct ath12k_htc_record_hdr hdr;
10618	union {
10619		struct ath12k_htc_credit_report credit_report[0];
10620		uint8_t payload[0];
10621	};
10622} __packed __aligned(4);
10623
10624/* note: the trailer offset is dynamic depending
10625 * on payload length. this is only a struct layout draft
10626 */
10627struct ath12k_htc_frame {
10628	struct ath12k_htc_hdr hdr;
10629	union {
10630		struct ath12k_htc_msg msg;
10631		uint8_t payload[0];
10632	};
10633	struct ath12k_htc_record trailer[0];
10634} __packed __aligned(4);
10635
10636enum ath12k_htc_svc_gid {
10637	ATH12K_HTC_SVC_GRP_RSVD = 0,
10638	ATH12K_HTC_SVC_GRP_WMI = 1,
10639	ATH12K_HTC_SVC_GRP_NMI = 2,
10640	ATH12K_HTC_SVC_GRP_HTT = 3,
10641	ATH12K_HTC_SVC_GRP_CFG = 4,
10642	ATH12K_HTC_SVC_GRP_IPA = 5,
10643	ATH12K_HTC_SVC_GRP_PKTLOG = 6,
10644
10645	ATH12K_HTC_SVC_GRP_TEST = 254,
10646	ATH12K_HTC_SVC_GRP_LAST = 255,
10647};
10648
10649#define SVC(group, idx) \
10650	(int)(((int)(group) << 8) | (int)(idx))
10651
10652enum ath12k_htc_svc_id {
10653	/* NOTE: service ID of 0x0000 is reserved and should never be used */
10654	ATH12K_HTC_SVC_ID_RESERVED	= 0x0000,
10655	ATH12K_HTC_SVC_ID_UNUSED	= ATH12K_HTC_SVC_ID_RESERVED,
10656
10657	ATH12K_HTC_SVC_ID_RSVD_CTRL	= SVC(ATH12K_HTC_SVC_GRP_RSVD, 1),
10658	ATH12K_HTC_SVC_ID_WMI_CONTROL	= SVC(ATH12K_HTC_SVC_GRP_WMI, 0),
10659	ATH12K_HTC_SVC_ID_WMI_DATA_BE	= SVC(ATH12K_HTC_SVC_GRP_WMI, 1),
10660	ATH12K_HTC_SVC_ID_WMI_DATA_BK	= SVC(ATH12K_HTC_SVC_GRP_WMI, 2),
10661	ATH12K_HTC_SVC_ID_WMI_DATA_VI	= SVC(ATH12K_HTC_SVC_GRP_WMI, 3),
10662	ATH12K_HTC_SVC_ID_WMI_DATA_VO	= SVC(ATH12K_HTC_SVC_GRP_WMI, 4),
10663	ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1 = SVC(ATH12K_HTC_SVC_GRP_WMI, 5),
10664	ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC2 = SVC(ATH12K_HTC_SVC_GRP_WMI, 6),
10665	ATH12K_HTC_SVC_ID_WMI_CONTROL_DIAG = SVC(ATH12K_HTC_SVC_GRP_WMI, 7),
10666
10667	ATH12K_HTC_SVC_ID_NMI_CONTROL	= SVC(ATH12K_HTC_SVC_GRP_NMI, 0),
10668	ATH12K_HTC_SVC_ID_NMI_DATA	= SVC(ATH12K_HTC_SVC_GRP_NMI, 1),
10669
10670	ATH12K_HTC_SVC_ID_HTT_DATA_MSG	= SVC(ATH12K_HTC_SVC_GRP_HTT, 0),
10671
10672	/* raw stream service (i.e. flash, tcmd, calibration apps) */
10673	ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS = SVC(ATH12K_HTC_SVC_GRP_TEST, 0),
10674	ATH12K_HTC_SVC_ID_IPA_TX = SVC(ATH12K_HTC_SVC_GRP_IPA, 0),
10675	ATH12K_HTC_SVC_ID_PKT_LOG = SVC(ATH12K_HTC_SVC_GRP_PKTLOG, 0),
10676};
10677
10678#undef SVC
10679
10680enum ath12k_htc_ep_id {
10681	ATH12K_HTC_EP_UNUSED = -1,
10682	ATH12K_HTC_EP_0 = 0,
10683	ATH12K_HTC_EP_1 = 1,
10684	ATH12K_HTC_EP_2,
10685	ATH12K_HTC_EP_3,
10686	ATH12K_HTC_EP_4,
10687	ATH12K_HTC_EP_5,
10688	ATH12K_HTC_EP_6,
10689	ATH12K_HTC_EP_7,
10690	ATH12K_HTC_EP_8,
10691	ATH12K_HTC_EP_COUNT,
10692};
10693
10694/*
10695 * hw.h
10696 */
10697
10698/* Target configuration defines */
10699
10700/* Num VDEVS per radio */
10701#define TARGET_NUM_VDEVS(sc)	(sc->hw_params.num_vdevs)
10702
10703#define TARGET_NUM_PEERS_PDEV(sc) (sc->hw_params.num_peers + TARGET_NUM_VDEVS(sc))
10704
10705/* Num of peers for Single Radio mode */
10706#define TARGET_NUM_PEERS_SINGLE(sc) (TARGET_NUM_PEERS_PDEV(sc))
10707
10708/* Num of peers for DBS */
10709#define TARGET_NUM_PEERS_DBS(sc) (2 * TARGET_NUM_PEERS_PDEV(sc))
10710
10711/* Num of peers for DBS_SBS */
10712#define TARGET_NUM_PEERS_DBS_SBS(sc)	(3 * TARGET_NUM_PEERS_PDEV(sc))
10713
10714/* Max num of stations (per radio) */
10715#define TARGET_NUM_STATIONS(sc)	(sc->hw_params.num_peers)
10716
10717#define TARGET_NUM_PEERS(sc, x)	TARGET_NUM_PEERS_##x(sc)
10718#define TARGET_NUM_PEER_KEYS	2
10719#define TARGET_NUM_TIDS(sc, x)	(2 * TARGET_NUM_PEERS(sc, x) +	\
10720				 4 * TARGET_NUM_VDEVS(sc) + 8)
10721
10722#define TARGET_AST_SKID_LIMIT	16
10723#define TARGET_NUM_OFFLD_PEERS	4
10724#define TARGET_NUM_OFFLD_REORDER_BUFFS 4
10725
10726#define TARGET_TX_CHAIN_MASK	(BIT(0) | BIT(1) | BIT(2) | BIT(4))
10727#define TARGET_RX_CHAIN_MASK	(BIT(0) | BIT(1) | BIT(2) | BIT(4))
10728#define TARGET_RX_TIMEOUT_LO_PRI	100
10729#define TARGET_RX_TIMEOUT_HI_PRI	40
10730
10731#define TARGET_DECAP_MODE_RAW		0
10732#define TARGET_DECAP_MODE_NATIVE_WIFI	1
10733#define TARGET_DECAP_MODE_ETH		2
10734
10735#define TARGET_SCAN_MAX_PENDING_REQS	4
10736#define TARGET_BMISS_OFFLOAD_MAX_VDEV	3
10737#define TARGET_ROAM_OFFLOAD_MAX_VDEV	3
10738#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES	8
10739#define TARGET_GTK_OFFLOAD_MAX_VDEV	3
10740#define TARGET_NUM_MCAST_GROUPS		12
10741#define TARGET_NUM_MCAST_TABLE_ELEMS	64
10742#define TARGET_MCAST2UCAST_MODE		2
10743#define TARGET_TX_DBG_LOG_SIZE		1024
10744#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
10745#define TARGET_VOW_CONFIG		0
10746#define TARGET_NUM_MSDU_DESC		(2500)
10747#define TARGET_MAX_FRAG_ENTRIES		6
10748#define TARGET_MAX_BCN_OFFLD		16
10749#define TARGET_NUM_WDS_ENTRIES		32
10750#define TARGET_DMA_BURST_SIZE		1
10751#define TARGET_RX_BATCHMODE		1
10752#define TARGET_EMA_MAX_PROFILE_PERIOD	8
10753
10754#define ATH12K_HW_MAX_QUEUES		4
10755#define ATH12K_QUEUE_LEN		4096
10756
10757#define ATH12k_HW_RATECODE_CCK_SHORT_PREAM_MASK  0x4
10758
10759enum ath12k_hw_rate_cck {
10760	ATH12K_HW_RATE_CCK_LP_11M = 0,
10761	ATH12K_HW_RATE_CCK_LP_5_5M,
10762	ATH12K_HW_RATE_CCK_LP_2M,
10763	ATH12K_HW_RATE_CCK_LP_1M,
10764	ATH12K_HW_RATE_CCK_SP_11M,
10765	ATH12K_HW_RATE_CCK_SP_5_5M,
10766	ATH12K_HW_RATE_CCK_SP_2M,
10767};
10768
10769enum ath12k_hw_rate_ofdm {
10770	ATH12K_HW_RATE_OFDM_48M = 0,
10771	ATH12K_HW_RATE_OFDM_24M,
10772	ATH12K_HW_RATE_OFDM_12M,
10773	ATH12K_HW_RATE_OFDM_6M,
10774	ATH12K_HW_RATE_OFDM_54M,
10775	ATH12K_HW_RATE_OFDM_36M,
10776	ATH12K_HW_RATE_OFDM_18M,
10777	ATH12K_HW_RATE_OFDM_9M,
10778};
10779
10780enum ath12k_bus {
10781	ATH12K_BUS_AHB,
10782	ATH12K_BUS_PCI,
10783};
10784
10785#define ATH12K_EXT_IRQ_GRP_NUM_MAX 11
10786
10787/*
10788 * rx_desc.h
10789 */
10790
10791enum rx_desc_rxpcu_filter {
10792	RX_DESC_RXPCU_FILTER_PASS,
10793	RX_DESC_RXPCU_FILTER_MONITOR_CLIENT,
10794	RX_DESC_RXPCU_FILTER_MONITOR_OTHER,
10795};
10796
10797/* rxpcu_filter_pass
10798 *		This MPDU passed the normal frame filter programming of rxpcu.
10799 *
10800 * rxpcu_filter_monitor_client
10801 *		 This MPDU did not pass the regular frame filter and would
10802 *		 have been dropped, were it not for the frame fitting into the
10803 *		 'monitor_client' category.
10804 *
10805 * rxpcu_filter_monitor_other
10806 *		This MPDU did not pass the regular frame filter and also did
10807 *		not pass the rxpcu_monitor_client filter. It would have been
10808 *		dropped accept that it did pass the 'monitor_other' category.
10809 */
10810
10811#define RX_DESC_INFO0_RXPCU_MPDU_FITLER	GENMASK(1, 0)
10812#define RX_DESC_INFO0_SW_FRAME_GRP_ID	GENMASK(8, 2)
10813
10814enum rx_desc_sw_frame_grp_id {
10815	RX_DESC_SW_FRAME_GRP_ID_NDP_FRAME,
10816	RX_DESC_SW_FRAME_GRP_ID_MCAST_DATA,
10817	RX_DESC_SW_FRAME_GRP_ID_UCAST_DATA,
10818	RX_DESC_SW_FRAME_GRP_ID_NULL_DATA,
10819	RX_DESC_SW_FRAME_GRP_ID_MGMT_0000,
10820	RX_DESC_SW_FRAME_GRP_ID_MGMT_0001,
10821	RX_DESC_SW_FRAME_GRP_ID_MGMT_0010,
10822	RX_DESC_SW_FRAME_GRP_ID_MGMT_0011,
10823	RX_DESC_SW_FRAME_GRP_ID_MGMT_0100,
10824	RX_DESC_SW_FRAME_GRP_ID_MGMT_0101,
10825	RX_DESC_SW_FRAME_GRP_ID_MGMT_0110,
10826	RX_DESC_SW_FRAME_GRP_ID_MGMT_0111,
10827	RX_DESC_SW_FRAME_GRP_ID_MGMT_1000,
10828	RX_DESC_SW_FRAME_GRP_ID_MGMT_1001,
10829	RX_DESC_SW_FRAME_GRP_ID_MGMT_1010,
10830	RX_DESC_SW_FRAME_GRP_ID_MGMT_1011,
10831	RX_DESC_SW_FRAME_GRP_ID_MGMT_1100,
10832	RX_DESC_SW_FRAME_GRP_ID_MGMT_1101,
10833	RX_DESC_SW_FRAME_GRP_ID_MGMT_1110,
10834	RX_DESC_SW_FRAME_GRP_ID_MGMT_1111,
10835	RX_DESC_SW_FRAME_GRP_ID_CTRL_0000,
10836	RX_DESC_SW_FRAME_GRP_ID_CTRL_0001,
10837	RX_DESC_SW_FRAME_GRP_ID_CTRL_0010,
10838	RX_DESC_SW_FRAME_GRP_ID_CTRL_0011,
10839	RX_DESC_SW_FRAME_GRP_ID_CTRL_0100,
10840	RX_DESC_SW_FRAME_GRP_ID_CTRL_0101,
10841	RX_DESC_SW_FRAME_GRP_ID_CTRL_0110,
10842	RX_DESC_SW_FRAME_GRP_ID_CTRL_0111,
10843	RX_DESC_SW_FRAME_GRP_ID_CTRL_1000,
10844	RX_DESC_SW_FRAME_GRP_ID_CTRL_1001,
10845	RX_DESC_SW_FRAME_GRP_ID_CTRL_1010,
10846	RX_DESC_SW_FRAME_GRP_ID_CTRL_1011,
10847	RX_DESC_SW_FRAME_GRP_ID_CTRL_1100,
10848	RX_DESC_SW_FRAME_GRP_ID_CTRL_1101,
10849	RX_DESC_SW_FRAME_GRP_ID_CTRL_1110,
10850	RX_DESC_SW_FRAME_GRP_ID_CTRL_1111,
10851	RX_DESC_SW_FRAME_GRP_ID_UNSUPPORTED,
10852	RX_DESC_SW_FRAME_GRP_ID_PHY_ERR,
10853};
10854
10855#define DP_MAX_NWIFI_HDR_LEN	30
10856
10857#define DP_RX_MPDU_ERR_FCS			BIT(0)
10858#define DP_RX_MPDU_ERR_DECRYPT			BIT(1)
10859#define DP_RX_MPDU_ERR_TKIP_MIC			BIT(2)
10860#define DP_RX_MPDU_ERR_AMSDU_ERR		BIT(3)
10861#define DP_RX_MPDU_ERR_OVERFLOW			BIT(4)
10862#define DP_RX_MPDU_ERR_MSDU_LEN			BIT(5)
10863#define DP_RX_MPDU_ERR_MPDU_LEN			BIT(6)
10864#define DP_RX_MPDU_ERR_UNENCRYPTED_FRAME	BIT(7)
10865
10866enum dp_rx_decap_type {
10867	DP_RX_DECAP_TYPE_RAW,
10868	DP_RX_DECAP_TYPE_NATIVE_WIFI,
10869	DP_RX_DECAP_TYPE_ETHERNET2_DIX,
10870	DP_RX_DECAP_TYPE_8023,
10871};
10872
10873enum rx_desc_decap_type {
10874	RX_DESC_DECAP_TYPE_RAW,
10875	RX_DESC_DECAP_TYPE_NATIVE_WIFI,
10876	RX_DESC_DECAP_TYPE_ETHERNET2_DIX,
10877	RX_DESC_DECAP_TYPE_8023,
10878};
10879
10880enum rx_desc_decrypt_status_code {
10881	RX_DESC_DECRYPT_STATUS_CODE_OK,
10882	RX_DESC_DECRYPT_STATUS_CODE_UNPROTECTED_FRAME,
10883	RX_DESC_DECRYPT_STATUS_CODE_DATA_ERR,
10884	RX_DESC_DECRYPT_STATUS_CODE_KEY_INVALID,
10885	RX_DESC_DECRYPT_STATUS_CODE_PEER_ENTRY_INVALID,
10886	RX_DESC_DECRYPT_STATUS_CODE_OTHER,
10887};
10888
10889#define RX_ATTENTION_INFO1_FIRST_MPDU		BIT(0)
10890#define RX_ATTENTION_INFO1_RSVD_1A		BIT(1)
10891#define RX_ATTENTION_INFO1_MCAST_BCAST		BIT(2)
10892#define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND	BIT(3)
10893#define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT	BIT(4)
10894#define RX_ATTENTION_INFO1_POWER_MGMT		BIT(5)
10895#define RX_ATTENTION_INFO1_NON_QOS		BIT(6)
10896#define RX_ATTENTION_INFO1_NULL_DATA		BIT(7)
10897#define RX_ATTENTION_INFO1_MGMT_TYPE		BIT(8)
10898#define RX_ATTENTION_INFO1_CTRL_TYPE		BIT(9)
10899#define RX_ATTENTION_INFO1_MORE_DATA		BIT(10)
10900#define RX_ATTENTION_INFO1_EOSP			BIT(11)
10901#define RX_ATTENTION_INFO1_A_MSDU_ERROR		BIT(12)
10902#define RX_ATTENTION_INFO1_FRAGMENT		BIT(13)
10903#define RX_ATTENTION_INFO1_ORDER		BIT(14)
10904#define RX_ATTENTION_INFO1_CCE_MATCH		BIT(15)
10905#define RX_ATTENTION_INFO1_OVERFLOW_ERR		BIT(16)
10906#define RX_ATTENTION_INFO1_MSDU_LEN_ERR		BIT(17)
10907#define RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL	BIT(18)
10908#define RX_ATTENTION_INFO1_IP_CKSUM_FAIL	BIT(19)
10909#define RX_ATTENTION_INFO1_SA_IDX_INVALID	BIT(20)
10910#define RX_ATTENTION_INFO1_DA_IDX_INVALID	BIT(21)
10911#define RX_ATTENTION_INFO1_RSVD_1B		BIT(22)
10912#define RX_ATTENTION_INFO1_RX_IN_TX_DECRYPT_BYP	BIT(23)
10913#define RX_ATTENTION_INFO1_ENCRYPT_REQUIRED	BIT(24)
10914#define RX_ATTENTION_INFO1_DIRECTED		BIT(25)
10915#define RX_ATTENTION_INFO1_BUFFER_FRAGMENT	BIT(26)
10916#define RX_ATTENTION_INFO1_MPDU_LEN_ERR		BIT(27)
10917#define RX_ATTENTION_INFO1_TKIP_MIC_ERR		BIT(28)
10918#define RX_ATTENTION_INFO1_DECRYPT_ERR		BIT(29)
10919#define RX_ATTENTION_INFO1_UNDECRYPT_FRAME_ERR	BIT(30)
10920#define RX_ATTENTION_INFO1_FCS_ERR		BIT(31)
10921
10922#define RX_ATTENTION_INFO2_FLOW_IDX_TIMEOUT	BIT(0)
10923#define RX_ATTENTION_INFO2_FLOW_IDX_INVALID	BIT(1)
10924#define RX_ATTENTION_INFO2_WIFI_PARSER_ERR	BIT(2)
10925#define RX_ATTENTION_INFO2_AMSDU_PARSER_ERR	BIT(3)
10926#define RX_ATTENTION_INFO2_SA_IDX_TIMEOUT	BIT(4)
10927#define RX_ATTENTION_INFO2_DA_IDX_TIMEOUT	BIT(5)
10928#define RX_ATTENTION_INFO2_MSDU_LIMIT_ERR	BIT(6)
10929#define RX_ATTENTION_INFO2_DA_IS_VALID		BIT(7)
10930#define RX_ATTENTION_INFO2_DA_IS_MCBC		BIT(8)
10931#define RX_ATTENTION_INFO2_SA_IS_VALID		BIT(9)
10932#define RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE	GENMASK(12, 10)
10933#define RX_ATTENTION_INFO2_RX_BITMAP_NOT_UPDED	BIT(13)
10934#define RX_ATTENTION_INFO2_MSDU_DONE		BIT(31)
10935
10936struct rx_attention {
10937	uint16_t info0;
10938	uint16_t phy_ppdu_id;
10939	uint32_t info1;
10940	uint32_t info2;
10941} __packed;
10942
10943/* rx_attention
10944 *
10945 * rxpcu_mpdu_filter_in_category
10946 *		Field indicates what the reason was that this mpdu frame
10947 *		was allowed to come into the receive path by rxpcu. Values
10948 *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
10949 *
10950 * sw_frame_group_id
10951 *		SW processes frames based on certain classifications. Values
10952 *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
10953 *
10954 * phy_ppdu_id
10955 *		A ppdu counter value that PHY increments for every PPDU
10956 *		received. The counter value wraps around.
10957 *
10958 * first_mpdu
10959 *		Indicates the first MSDU of the PPDU.  If both first_mpdu
10960 *		and last_mpdu are set in the MSDU then this is a not an
10961 *		A-MPDU frame but a stand alone MPDU.  Interior MPDU in an
10962 *		A-MPDU shall have both first_mpdu and last_mpdu bits set to
10963 *		0.  The PPDU start status will only be valid when this bit
10964 *		is set.
10965 *
10966 * mcast_bcast
10967 *		Multicast / broadcast indicator.  Only set when the MAC
10968 *		address 1 bit 0 is set indicating mcast/bcast and the BSSID
10969 *		matches one of the 4 BSSID registers. Only set when
10970 *		first_msdu is set.
10971 *
10972 * ast_index_not_found
10973 *		Only valid when first_msdu is set. Indicates no AST matching
10974 *		entries within the max search count.
10975 *
10976 * ast_index_timeout
10977 *		Only valid when first_msdu is set. Indicates an unsuccessful
10978 *		search in the address search table due to timeout.
10979 *
10980 * power_mgmt
10981 *		Power management bit set in the 802.11 header.  Only set
10982 *		when first_msdu is set.
10983 *
10984 * non_qos
10985 *		Set if packet is not a non-QoS data frame.  Only set when
10986 *		first_msdu is set.
10987 *
10988 * null_data
10989 *		Set if frame type indicates either null data or QoS null
10990 *		data format.  Only set when first_msdu is set.
10991 *
10992 * mgmt_type
10993 *		Set if packet is a management packet.  Only set when
10994 *		first_msdu is set.
10995 *
10996 * ctrl_type
10997 *		Set if packet is a control packet.  Only set when first_msdu
10998 *		is set.
10999 *
11000 * more_data
11001 *		Set if more bit in frame control is set.  Only set when
11002 *		first_msdu is set.
11003 *
11004 * eosp
11005 *		Set if the EOSP (end of service period) bit in the QoS
11006 *		control field is set.  Only set when first_msdu is set.
11007 *
11008 * a_msdu_error
11009 *		Set if number of MSDUs in A-MSDU is above a threshold or if the
11010 *		size of the MSDU is invalid. This receive buffer will contain
11011 *		all of the remainder of MSDUs in this MPDU w/o decapsulation.
11012 *
11013 * fragment
11014 *		Indicates that this is an 802.11 fragment frame.  This is
11015 *		set when either the more_frag bit is set in the frame
11016 *		control or the fragment number is not zero.  Only set when
11017 *		first_msdu is set.
11018 *
11019 * order
11020 *		Set if the order bit in the frame control is set.  Only set
11021 *		when first_msdu is set.
11022 *
11023 * cce_match
11024 *		Indicates that this status has a corresponding MSDU that
11025 *		requires FW processing. The OLE will have classification
11026 *		ring mask registers which will indicate the ring(s) for
11027 *		packets and descriptors which need FW attention.
11028 *
11029 * overflow_err
11030 *		PCU Receive FIFO does not have enough space to store the
11031 *		full receive packet.  Enough space is reserved in the
11032 *		receive FIFO for the status is written.  This MPDU remaining
11033 *		packets in the PPDU will be filtered and no Ack response
11034 *		will be transmitted.
11035 *
11036 * msdu_length_err
11037 *		Indicates that the MSDU length from the 802.3 encapsulated
11038 *		length field extends beyond the MPDU boundary.
11039 *
11040 * tcp_udp_chksum_fail
11041 *		Indicates that the computed checksum (tcp_udp_chksum) did
11042 *		not match the checksum in the TCP/UDP header.
11043 *
11044 * ip_chksum_fail
11045 *		Indicates that the computed checksum did not match the
11046 *		checksum in the IP header.
11047 *
11048 * sa_idx_invalid
11049 *		Indicates no matching entry was found in the address search
11050 *		table for the source MAC address.
11051 *
11052 * da_idx_invalid
11053 *		Indicates no matching entry was found in the address search
11054 *		table for the destination MAC address.
11055 *
11056 * rx_in_tx_decrypt_byp
11057 *		Indicates that RX packet is not decrypted as Crypto is busy
11058 *		with TX packet processing.
11059 *
11060 * encrypt_required
11061 *		Indicates that this data type frame is not encrypted even if
11062 *		the policy for this MPDU requires encryption as indicated in
11063 *		the peer table key type.
11064 *
11065 * directed
11066 *		MPDU is a directed packet which means that the RA matched
11067 *		our STA addresses.  In proxySTA it means that the TA matched
11068 *		an entry in our address search table with the corresponding
11069 *		'no_ack' bit is the address search entry cleared.
11070 *
11071 * buffer_fragment
11072 *		Indicates that at least one of the rx buffers has been
11073 *		fragmented.  If set the FW should look at the rx_frag_info
11074 *		descriptor described below.
11075 *
11076 * mpdu_length_err
11077 *		Indicates that the MPDU was pre-maturely terminated
11078 *		resulting in a truncated MPDU.  Don't trust the MPDU length
11079 *		field.
11080 *
11081 * tkip_mic_err
11082 *		Indicates that the MPDU Michael integrity check failed
11083 *
11084 * decrypt_err
11085 *		Indicates that the MPDU decrypt integrity check failed
11086 *
11087 * fcs_err
11088 *		Indicates that the MPDU FCS check failed
11089 *
11090 * flow_idx_timeout
11091 *		Indicates an unsuccessful flow search due to the expiring of
11092 *		the search timer.
11093 *
11094 * flow_idx_invalid
11095 *		flow id is not valid.
11096 *
11097 * amsdu_parser_error
11098 *		A-MSDU could not be properly de-agregated.
11099 *
11100 * sa_idx_timeout
11101 *		Indicates an unsuccessful search for the source MAC address
11102 *		due to the expiring of the search timer.
11103 *
11104 * da_idx_timeout
11105 *		Indicates an unsuccessful search for the destination MAC
11106 *		address due to the expiring of the search timer.
11107 *
11108 * msdu_limit_error
11109 *		Indicates that the MSDU threshold was exceeded and thus
11110 *		all the rest of the MSDUs will not be scattered and will not
11111 *		be decapsulated but will be DMA'ed in RAW format as a single
11112 *		MSDU buffer.
11113 *
11114 * da_is_valid
11115 *		Indicates that OLE found a valid DA entry.
11116 *
11117 * da_is_mcbc
11118 *		Field Only valid if da_is_valid is set. Indicates the DA address
11119 *		was a Multicast or Broadcast address.
11120 *
11121 * sa_is_valid
11122 *		Indicates that OLE found a valid SA entry.
11123 *
11124 * decrypt_status_code
11125 *		Field provides insight into the decryption performed. Values are
11126 *		defined in enum %RX_DESC_DECRYPT_STATUS_CODE*.
11127 *
11128 * rx_bitmap_not_updated
11129 *		Frame is received, but RXPCU could not update the receive bitmap
11130 *		due to (temporary) fifo constraints.
11131 *
11132 * msdu_done
11133 *		If set indicates that the RX packet data, RX header data, RX
11134 *		PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU
11135 *		start/end descriptors and RX Attention descriptor are all
11136 *		valid.  This bit must be in the last octet of the
11137 *		descriptor.
11138 */
11139
11140#define RX_MPDU_START_INFO0_NDP_FRAME		BIT(9)
11141#define RX_MPDU_START_INFO0_PHY_ERR		BIT(10)
11142#define RX_MPDU_START_INFO0_PHY_ERR_MPDU_HDR	BIT(11)
11143#define RX_MPDU_START_INFO0_PROTO_VER_ERR	BIT(12)
11144#define RX_MPDU_START_INFO0_AST_LOOKUP_VALID	BIT(13)
11145
11146#define RX_MPDU_START_INFO1_MPDU_FCTRL_VALID	BIT(0)
11147#define RX_MPDU_START_INFO1_MPDU_DUR_VALID	BIT(1)
11148#define RX_MPDU_START_INFO1_MAC_ADDR1_VALID	BIT(2)
11149#define RX_MPDU_START_INFO1_MAC_ADDR2_VALID	BIT(3)
11150#define RX_MPDU_START_INFO1_MAC_ADDR3_VALID	BIT(4)
11151#define RX_MPDU_START_INFO1_MAC_ADDR4_VALID	BIT(5)
11152#define RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID	BIT(6)
11153#define RX_MPDU_START_INFO1_MPDU_QOS_CTRL_VALID	BIT(7)
11154#define RX_MPDU_START_INFO1_MPDU_HT_CTRL_VALID	BIT(8)
11155#define RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID	BIT(9)
11156#define RX_MPDU_START_INFO1_MPDU_FRAG_NUMBER	GENMASK(13, 10)
11157#define RX_MPDU_START_INFO1_MORE_FRAG_FLAG	BIT(14)
11158#define RX_MPDU_START_INFO1_FROM_DS		BIT(16)
11159#define RX_MPDU_START_INFO1_TO_DS		BIT(17)
11160#define RX_MPDU_START_INFO1_ENCRYPTED		BIT(18)
11161#define RX_MPDU_START_INFO1_MPDU_RETRY		BIT(19)
11162#define RX_MPDU_START_INFO1_MPDU_SEQ_NUM	GENMASK(31, 20)
11163
11164#define RX_MPDU_START_INFO2_EPD_EN		BIT(0)
11165#define RX_MPDU_START_INFO2_ALL_FRAME_ENCPD	BIT(1)
11166#define RX_MPDU_START_INFO2_ENC_TYPE		GENMASK(5, 2)
11167#define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH	GENMASK(7, 6)
11168#define RX_MPDU_START_INFO2_MESH_STA		BIT(8)
11169#define RX_MPDU_START_INFO2_BSSID_HIT		BIT(9)
11170#define RX_MPDU_START_INFO2_BSSID_NUM		GENMASK(13, 10)
11171#define RX_MPDU_START_INFO2_TID			GENMASK(17, 14)
11172#define RX_MPDU_START_INFO2_TID_WCN6855		GENMASK(18, 15)
11173
11174#define RX_MPDU_START_INFO3_REO_DEST_IND		GENMASK(4, 0)
11175#define RX_MPDU_START_INFO3_FLOW_ID_TOEPLITZ		BIT(7)
11176#define RX_MPDU_START_INFO3_PKT_SEL_FP_UCAST_DATA	BIT(8)
11177#define RX_MPDU_START_INFO3_PKT_SEL_FP_MCAST_DATA	BIT(9)
11178#define RX_MPDU_START_INFO3_PKT_SEL_FP_CTRL_BAR		BIT(10)
11179#define RX_MPDU_START_INFO3_RXDMA0_SRC_RING_SEL		GENMASK(12, 11)
11180#define RX_MPDU_START_INFO3_RXDMA0_DST_RING_SEL		GENMASK(14, 13)
11181
11182#define RX_MPDU_START_INFO4_REO_QUEUE_DESC_HI	GENMASK(7, 0)
11183#define RX_MPDU_START_INFO4_RECV_QUEUE_NUM	GENMASK(23, 8)
11184#define RX_MPDU_START_INFO4_PRE_DELIM_ERR_WARN	BIT(24)
11185#define RX_MPDU_START_INFO4_FIRST_DELIM_ERR	BIT(25)
11186
11187#define RX_MPDU_START_INFO5_KEY_ID		GENMASK(7, 0)
11188#define RX_MPDU_START_INFO5_NEW_PEER_ENTRY	BIT(8)
11189#define RX_MPDU_START_INFO5_DECRYPT_NEEDED	BIT(9)
11190#define RX_MPDU_START_INFO5_DECAP_TYPE		GENMASK(11, 10)
11191#define RX_MPDU_START_INFO5_VLAN_TAG_C_PADDING	BIT(12)
11192#define RX_MPDU_START_INFO5_VLAN_TAG_S_PADDING	BIT(13)
11193#define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_C	BIT(14)
11194#define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_S	BIT(15)
11195#define RX_MPDU_START_INFO5_PRE_DELIM_COUNT	GENMASK(27, 16)
11196#define RX_MPDU_START_INFO5_AMPDU_FLAG		BIT(28)
11197#define RX_MPDU_START_INFO5_BAR_FRAME		BIT(29)
11198
11199#define RX_MPDU_START_INFO6_MPDU_LEN		GENMASK(13, 0)
11200#define RX_MPDU_START_INFO6_FIRST_MPDU		BIT(14)
11201#define RX_MPDU_START_INFO6_MCAST_BCAST		BIT(15)
11202#define RX_MPDU_START_INFO6_AST_IDX_NOT_FOUND	BIT(16)
11203#define RX_MPDU_START_INFO6_AST_IDX_TIMEOUT	BIT(17)
11204#define RX_MPDU_START_INFO6_POWER_MGMT		BIT(18)
11205#define RX_MPDU_START_INFO6_NON_QOS		BIT(19)
11206#define RX_MPDU_START_INFO6_NULL_DATA		BIT(20)
11207#define RX_MPDU_START_INFO6_MGMT_TYPE		BIT(21)
11208#define RX_MPDU_START_INFO6_CTRL_TYPE		BIT(22)
11209#define RX_MPDU_START_INFO6_MORE_DATA		BIT(23)
11210#define RX_MPDU_START_INFO6_EOSP		BIT(24)
11211#define RX_MPDU_START_INFO6_FRAGMENT		BIT(25)
11212#define RX_MPDU_START_INFO6_ORDER		BIT(26)
11213#define RX_MPDU_START_INFO6_UAPSD_TRIGGER	BIT(27)
11214#define RX_MPDU_START_INFO6_ENCRYPT_REQUIRED	BIT(28)
11215#define RX_MPDU_START_INFO6_DIRECTED		BIT(29)
11216
11217#define RX_MPDU_START_RAW_MPDU			BIT(0)
11218
11219struct rx_mpdu_start_ipq8074 {
11220	uint16_t info0;
11221	uint16_t phy_ppdu_id;
11222	uint16_t ast_index;
11223	uint16_t sw_peer_id;
11224	uint32_t info1;
11225	uint32_t info2;
11226	uint32_t pn[4];
11227	uint32_t peer_meta_data;
11228	uint32_t info3;
11229	uint32_t reo_queue_desc_lo;
11230	uint32_t info4;
11231	uint32_t info5;
11232	uint32_t info6;
11233	uint16_t frame_ctrl;
11234	uint16_t duration;
11235	uint8_t addr1[IEEE80211_ADDR_LEN];
11236	uint8_t addr2[IEEE80211_ADDR_LEN];
11237	uint8_t addr3[IEEE80211_ADDR_LEN];
11238	uint16_t seq_ctrl;
11239	uint8_t addr4[IEEE80211_ADDR_LEN];
11240	uint16_t qos_ctrl;
11241	uint32_t ht_ctrl;
11242	uint32_t raw;
11243} __packed;
11244
11245#define RX_MPDU_START_INFO7_REO_DEST_IND		GENMASK(4, 0)
11246#define RX_MPDU_START_INFO7_LMAC_PEER_ID_MSB		GENMASK(6, 5)
11247#define RX_MPDU_START_INFO7_FLOW_ID_TOEPLITZ		BIT(7)
11248#define RX_MPDU_START_INFO7_PKT_SEL_FP_UCAST_DATA	BIT(8)
11249#define RX_MPDU_START_INFO7_PKT_SEL_FP_MCAST_DATA	BIT(9)
11250#define RX_MPDU_START_INFO7_PKT_SEL_FP_CTRL_BAR		BIT(10)
11251#define RX_MPDU_START_INFO7_RXDMA0_SRC_RING_SEL		GENMASK(12, 11)
11252#define RX_MPDU_START_INFO7_RXDMA0_DST_RING_SEL		GENMASK(14, 13)
11253
11254#define RX_MPDU_START_INFO8_REO_QUEUE_DESC_HI		GENMASK(7, 0)
11255#define RX_MPDU_START_INFO8_RECV_QUEUE_NUM		GENMASK(23, 8)
11256#define RX_MPDU_START_INFO8_PRE_DELIM_ERR_WARN		BIT(24)
11257#define RX_MPDU_START_INFO8_FIRST_DELIM_ERR		BIT(25)
11258
11259#define RX_MPDU_START_INFO9_EPD_EN			BIT(0)
11260#define RX_MPDU_START_INFO9_ALL_FRAME_ENCPD		BIT(1)
11261#define RX_MPDU_START_INFO9_ENC_TYPE			GENMASK(5, 2)
11262#define RX_MPDU_START_INFO9_VAR_WEP_KEY_WIDTH		GENMASK(7, 6)
11263#define RX_MPDU_START_INFO9_MESH_STA			GENMASK(9, 8)
11264#define RX_MPDU_START_INFO9_BSSID_HIT			BIT(10)
11265#define RX_MPDU_START_INFO9_BSSID_NUM			GENMASK(14, 11)
11266#define RX_MPDU_START_INFO9_TID				GENMASK(18, 15)
11267
11268#define RX_MPDU_START_INFO10_RXPCU_MPDU_FLTR		GENMASK(1, 0)
11269#define RX_MPDU_START_INFO10_SW_FRAME_GRP_ID		GENMASK(8, 2)
11270#define RX_MPDU_START_INFO10_NDP_FRAME			BIT(9)
11271#define RX_MPDU_START_INFO10_PHY_ERR			BIT(10)
11272#define RX_MPDU_START_INFO10_PHY_ERR_MPDU_HDR		BIT(11)
11273#define RX_MPDU_START_INFO10_PROTO_VER_ERR		BIT(12)
11274#define RX_MPDU_START_INFO10_AST_LOOKUP_VALID		BIT(13)
11275
11276#define RX_MPDU_START_INFO11_MPDU_FCTRL_VALID		BIT(0)
11277#define RX_MPDU_START_INFO11_MPDU_DUR_VALID		BIT(1)
11278#define RX_MPDU_START_INFO11_MAC_ADDR1_VALID		BIT(2)
11279#define RX_MPDU_START_INFO11_MAC_ADDR2_VALID		BIT(3)
11280#define RX_MPDU_START_INFO11_MAC_ADDR3_VALID		BIT(4)
11281#define RX_MPDU_START_INFO11_MAC_ADDR4_VALID		BIT(5)
11282#define RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID	BIT(6)
11283#define RX_MPDU_START_INFO11_MPDU_QOS_CTRL_VALID	BIT(7)
11284#define RX_MPDU_START_INFO11_MPDU_HT_CTRL_VALID		BIT(8)
11285#define RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID		BIT(9)
11286#define RX_MPDU_START_INFO11_MPDU_FRAG_NUMBER		GENMASK(13, 10)
11287#define RX_MPDU_START_INFO11_MORE_FRAG_FLAG		BIT(14)
11288#define RX_MPDU_START_INFO11_FROM_DS			BIT(16)
11289#define RX_MPDU_START_INFO11_TO_DS			BIT(17)
11290#define RX_MPDU_START_INFO11_ENCRYPTED			BIT(18)
11291#define RX_MPDU_START_INFO11_MPDU_RETRY			BIT(19)
11292#define RX_MPDU_START_INFO11_MPDU_SEQ_NUM		GENMASK(31, 20)
11293
11294#define RX_MPDU_START_INFO12_KEY_ID			GENMASK(7, 0)
11295#define RX_MPDU_START_INFO12_NEW_PEER_ENTRY		BIT(8)
11296#define RX_MPDU_START_INFO12_DECRYPT_NEEDED		BIT(9)
11297#define RX_MPDU_START_INFO12_DECAP_TYPE			GENMASK(11, 10)
11298#define RX_MPDU_START_INFO12_VLAN_TAG_C_PADDING		BIT(12)
11299#define RX_MPDU_START_INFO12_VLAN_TAG_S_PADDING		BIT(13)
11300#define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_C		BIT(14)
11301#define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_S		BIT(15)
11302#define RX_MPDU_START_INFO12_PRE_DELIM_COUNT		GENMASK(27, 16)
11303#define RX_MPDU_START_INFO12_AMPDU_FLAG			BIT(28)
11304#define RX_MPDU_START_INFO12_BAR_FRAME			BIT(29)
11305#define RX_MPDU_START_INFO12_RAW_MPDU			BIT(30)
11306
11307#define RX_MPDU_START_INFO13_MPDU_LEN			GENMASK(13, 0)
11308#define RX_MPDU_START_INFO13_FIRST_MPDU			BIT(14)
11309#define RX_MPDU_START_INFO13_MCAST_BCAST		BIT(15)
11310#define RX_MPDU_START_INFO13_AST_IDX_NOT_FOUND		BIT(16)
11311#define RX_MPDU_START_INFO13_AST_IDX_TIMEOUT		BIT(17)
11312#define RX_MPDU_START_INFO13_POWER_MGMT			BIT(18)
11313#define RX_MPDU_START_INFO13_NON_QOS			BIT(19)
11314#define RX_MPDU_START_INFO13_NULL_DATA			BIT(20)
11315#define RX_MPDU_START_INFO13_MGMT_TYPE			BIT(21)
11316#define RX_MPDU_START_INFO13_CTRL_TYPE			BIT(22)
11317#define RX_MPDU_START_INFO13_MORE_DATA			BIT(23)
11318#define RX_MPDU_START_INFO13_EOSP			BIT(24)
11319#define RX_MPDU_START_INFO13_FRAGMENT			BIT(25)
11320#define RX_MPDU_START_INFO13_ORDER			BIT(26)
11321#define RX_MPDU_START_INFO13_UAPSD_TRIGGER		BIT(27)
11322#define RX_MPDU_START_INFO13_ENCRYPT_REQUIRED		BIT(28)
11323#define RX_MPDU_START_INFO13_DIRECTED			BIT(29)
11324#define RX_MPDU_START_INFO13_AMSDU_PRESENT		BIT(30)
11325
11326struct rx_mpdu_start_qcn9074 {
11327	uint32_t info7;
11328	uint32_t reo_queue_desc_lo;
11329	uint32_t info8;
11330	uint32_t pn[4];
11331	uint32_t info9;
11332	uint32_t peer_meta_data;
11333	uint16_t info10;
11334	uint16_t phy_ppdu_id;
11335	uint16_t ast_index;
11336	uint16_t sw_peer_id;
11337	uint32_t info11;
11338	uint32_t info12;
11339	uint32_t info13;
11340	uint16_t frame_ctrl;
11341	uint16_t duration;
11342	uint8_t addr1[IEEE80211_ADDR_LEN];
11343	uint8_t addr2[IEEE80211_ADDR_LEN];
11344	uint8_t addr3[IEEE80211_ADDR_LEN];
11345	uint16_t seq_ctrl;
11346	uint8_t addr4[IEEE80211_ADDR_LEN];
11347	uint16_t qos_ctrl;
11348	uint32_t ht_ctrl;
11349} __packed;
11350
11351struct rx_mpdu_start_wcn6855 {
11352	uint32_t info3;
11353	uint32_t reo_queue_desc_lo;
11354	uint32_t info4;
11355	uint32_t pn[4];
11356	uint32_t info2;
11357	uint32_t peer_meta_data;
11358	uint16_t info0;
11359	uint16_t phy_ppdu_id;
11360	uint16_t ast_index;
11361	uint16_t sw_peer_id;
11362	uint32_t info1;
11363	uint32_t info5;
11364	uint32_t info6;
11365	uint16_t frame_ctrl;
11366	uint16_t duration;
11367	uint8_t addr1[IEEE80211_ADDR_LEN];
11368	uint8_t addr2[IEEE80211_ADDR_LEN];
11369	uint8_t addr3[IEEE80211_ADDR_LEN];
11370	uint16_t seq_ctrl;
11371	uint8_t addr4[IEEE80211_ADDR_LEN];
11372	uint16_t qos_ctrl;
11373	uint32_t ht_ctrl;
11374} __packed;
11375
11376/* rx_mpdu_start
11377 *
11378 * rxpcu_mpdu_filter_in_category
11379 *		Field indicates what the reason was that this mpdu frame
11380 *		was allowed to come into the receive path by rxpcu. Values
11381 *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
11382 *		Note: for ndp frame, if it was expected because the preceding
11383 *		NDPA was filter_pass, the setting rxpcu_filter_pass will be
11384 *		used. This setting will also be used for every ndp frame in
11385 *		case Promiscuous mode is enabled.
11386 *
11387 * sw_frame_group_id
11388 *		SW processes frames based on certain classifications. Values
11389 *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
11390 *
11391 * ndp_frame
11392 *		Indicates that the received frame was an NDP frame.
11393 *
11394 * phy_err
11395 *		Indicates that PHY error was received before MAC received data.
11396 *
11397 * phy_err_during_mpdu_header
11398 *		PHY error was received before MAC received the complete MPDU
11399 *		header which was needed for proper decoding.
11400 *
11401 * protocol_version_err
11402 *		RXPCU detected a version error in the frame control field.
11403 *
11404 * ast_based_lookup_valid
11405 *		AST based lookup for this frame has found a valid result.
11406 *
11407 * phy_ppdu_id
11408 *		A ppdu counter value that PHY increments for every PPDU
11409 *		received. The counter value wraps around.
11410 *
11411 * ast_index
11412 *		This field indicates the index of the AST entry corresponding
11413 *		to this MPDU. It is provided by the GSE module instantiated in
11414 *		RXPCU. A value of 0xFFFF indicates an invalid AST index.
11415 *
11416 * sw_peer_id
11417 *		This field indicates a unique peer identifier. It is set equal
11418 *		to field 'sw_peer_id' from the AST entry.
11419 *
11420 * mpdu_frame_control_valid, mpdu_duration_valid, mpdu_qos_control_valid,
11421 * mpdu_ht_control_valid, frame_encryption_info_valid
11422 *		Indicates that each fields have valid entries.
11423 *
11424 * mac_addr_adx_valid
11425 *		Corresponding mac_addr_adx_{lo/hi} has valid entries.
11426 *
11427 * from_ds, to_ds
11428 *		Valid only when mpdu_frame_control_valid is set. Indicates that
11429 *		frame is received from DS and sent to DS.
11430 *
11431 * encrypted
11432 *		Protected bit from the frame control.
11433 *
11434 * mpdu_retry
11435 *		Retry bit from frame control. Only valid when first_msdu is set.
11436 *
11437 * mpdu_sequence_number
11438 *		The sequence number from the 802.11 header.
11439 *
11440 * epd_en
11441 *		If set, use EPD instead of LPD.
11442 *
11443 * all_frames_shall_be_encrypted
11444 *		If set, all frames (data only?) shall be encrypted. If not,
11445 *		RX CRYPTO shall set an error flag.
11446 *
11447 * encrypt_type
11448 *		Values are defined in enum %HAL_ENCRYPT_TYPE_.
11449 *
11450 * mesh_sta
11451 *		Indicates a Mesh (11s) STA.
11452 *
11453 * bssid_hit
11454 *		 BSSID of the incoming frame matched one of the 8 BSSID
11455 *		 register values.
11456 *
11457 * bssid_number
11458 *		This number indicates which one out of the 8 BSSID register
11459 *		values matched the incoming frame.
11460 *
11461 * tid
11462 *		TID field in the QoS control field
11463 *
11464 * pn
11465 *		The PN number.
11466 *
11467 * peer_meta_data
11468 *		Meta data that SW has programmed in the Peer table entry
11469 *		of the transmitting STA.
11470 *
11471 * rx_reo_queue_desc_addr_lo
11472 *		Address (lower 32 bits) of the REO queue descriptor.
11473 *
11474 * rx_reo_queue_desc_addr_hi
11475 *		Address (upper 8 bits) of the REO queue descriptor.
11476 *
11477 * receive_queue_number
11478 *		Indicates the MPDU queue ID to which this MPDU link
11479 *		descriptor belongs.
11480 *
11481 * pre_delim_err_warning
11482 *		Indicates that a delimiter FCS error was found in between the
11483 *		previous MPDU and this MPDU. Note that this is just a warning,
11484 *		and does not mean that this MPDU is corrupted in any way. If
11485 *		it is, there will be other errors indicated such as FCS or
11486 *		decrypt errors.
11487 *
11488 * first_delim_err
11489 *		Indicates that the first delimiter had a FCS failure.
11490 *
11491 * key_id
11492 *		The key ID octet from the IV.
11493 *
11494 * new_peer_entry
11495 *		Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY
11496 *		doesn't follow so RX DECRYPTION module either uses old peer
11497 *		entry or not decrypt.
11498 *
11499 * decrypt_needed
11500 *		When RXPCU sets bit 'ast_index_not_found or ast_index_timeout',
11501 *		RXPCU will also ensure that this bit is NOT set. CRYPTO for that
11502 *		reason only needs to evaluate this bit and non of the other ones
11503 *
11504 * decap_type
11505 *		Used by the OLE during decapsulation. Values are defined in
11506 *		enum %MPDU_START_DECAP_TYPE_*.
11507 *
11508 * rx_insert_vlan_c_tag_padding
11509 * rx_insert_vlan_s_tag_padding
11510 *		Insert 4 byte of all zeros as VLAN tag or double VLAN tag if
11511 *		the rx payload does not have VLAN.
11512 *
11513 * strip_vlan_c_tag_decap
11514 * strip_vlan_s_tag_decap
11515 *		Strip VLAN or double VLAN during decapsulation.
11516 *
11517 * pre_delim_count
11518 *		The number of delimiters before this MPDU. Note that this
11519 *		number is cleared at PPDU start. If this MPDU is the first
11520 *		received MPDU in the PPDU and this MPDU gets filtered-in,
11521 *		this field will indicate the number of delimiters located
11522 *		after the last MPDU in the previous PPDU.
11523 *
11524 *		If this MPDU is located after the first received MPDU in
11525 *		an PPDU, this field will indicate the number of delimiters
11526 *		located between the previous MPDU and this MPDU.
11527 *
11528 * ampdu_flag
11529 *		Received frame was part of an A-MPDU.
11530 *
11531 * bar_frame
11532 *		Received frame is a BAR frame
11533 *
11534 * mpdu_length
11535 *		MPDU length before decapsulation.
11536 *
11537 * first_mpdu..directed
11538 *		See definition in RX attention descriptor
11539 *
11540 */
11541
11542enum rx_msdu_start_pkt_type {
11543	RX_MSDU_START_PKT_TYPE_11A,
11544	RX_MSDU_START_PKT_TYPE_11B,
11545	RX_MSDU_START_PKT_TYPE_11N,
11546	RX_MSDU_START_PKT_TYPE_11AC,
11547	RX_MSDU_START_PKT_TYPE_11AX,
11548};
11549
11550enum rx_msdu_start_sgi {
11551	RX_MSDU_START_SGI_0_8_US,
11552	RX_MSDU_START_SGI_0_4_US,
11553	RX_MSDU_START_SGI_1_6_US,
11554	RX_MSDU_START_SGI_3_2_US,
11555};
11556
11557enum rx_msdu_start_recv_bw {
11558	RX_MSDU_START_RECV_BW_20MHZ,
11559	RX_MSDU_START_RECV_BW_40MHZ,
11560	RX_MSDU_START_RECV_BW_80MHZ,
11561	RX_MSDU_START_RECV_BW_160MHZ,
11562};
11563
11564enum rx_msdu_start_reception_type {
11565	RX_MSDU_START_RECEPTION_TYPE_SU,
11566	RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO,
11567	RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA,
11568	RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO,
11569	RX_MSDU_START_RECEPTION_TYPE_UL_MU_MIMO,
11570	RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA,
11571	RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO,
11572};
11573
11574#define RX_MSDU_START_INFO1_MSDU_LENGTH		GENMASK(13, 0)
11575#define RX_MSDU_START_INFO1_RSVD_1A		BIT(14)
11576#define RX_MSDU_START_INFO1_IPSEC_ESP		BIT(15)
11577#define RX_MSDU_START_INFO1_L3_OFFSET		GENMASK(22, 16)
11578#define RX_MSDU_START_INFO1_IPSEC_AH		BIT(23)
11579#define RX_MSDU_START_INFO1_L4_OFFSET		GENMASK(31, 24)
11580
11581#define RX_MSDU_START_INFO2_MSDU_NUMBER		GENMASK(7, 0)
11582#define RX_MSDU_START_INFO2_DECAP_TYPE		GENMASK(9, 8)
11583#define RX_MSDU_START_INFO2_IPV4		BIT(10)
11584#define RX_MSDU_START_INFO2_IPV6		BIT(11)
11585#define RX_MSDU_START_INFO2_TCP			BIT(12)
11586#define RX_MSDU_START_INFO2_UDP			BIT(13)
11587#define RX_MSDU_START_INFO2_IP_FRAG		BIT(14)
11588#define RX_MSDU_START_INFO2_TCP_ONLY_ACK	BIT(15)
11589#define RX_MSDU_START_INFO2_DA_IS_BCAST_MCAST	BIT(16)
11590#define RX_MSDU_START_INFO2_SELECTED_TOEPLITZ_HASH	GENMASK(18, 17)
11591#define RX_MSDU_START_INFO2_IP_FIXED_HDR_VALID		BIT(19)
11592#define RX_MSDU_START_INFO2_IP_EXTN_HDR_VALID		BIT(20)
11593#define RX_MSDU_START_INFO2_IP_TCP_UDP_HDR_VALID	BIT(21)
11594#define RX_MSDU_START_INFO2_MESH_CTRL_PRESENT		BIT(22)
11595#define RX_MSDU_START_INFO2_LDPC			BIT(23)
11596#define RX_MSDU_START_INFO2_IP4_IP6_NXT_HDR		GENMASK(31, 24)
11597#define RX_MSDU_START_INFO2_DECAP_FORMAT		GENMASK(9, 8)
11598
11599#define RX_MSDU_START_INFO3_USER_RSSI		GENMASK(7, 0)
11600#define RX_MSDU_START_INFO3_PKT_TYPE		GENMASK(11, 8)
11601#define RX_MSDU_START_INFO3_STBC		BIT(12)
11602#define RX_MSDU_START_INFO3_SGI			GENMASK(14, 13)
11603#define RX_MSDU_START_INFO3_RATE_MCS		GENMASK(18, 15)
11604#define RX_MSDU_START_INFO3_RECV_BW		GENMASK(20, 19)
11605#define RX_MSDU_START_INFO3_RECEPTION_TYPE	GENMASK(23, 21)
11606#define RX_MSDU_START_INFO3_MIMO_SS_BITMAP	GENMASK(31, 24)
11607
11608struct rx_msdu_start_ipq8074 {
11609	uint16_t info0;
11610	uint16_t phy_ppdu_id;
11611	uint32_t info1;
11612	uint32_t info2;
11613	uint32_t toeplitz_hash;
11614	uint32_t flow_id_toeplitz;
11615	uint32_t info3;
11616	uint32_t ppdu_start_timestamp;
11617	uint32_t phy_meta_data;
11618} __packed;
11619
11620struct rx_msdu_start_qcn9074 {
11621	uint16_t info0;
11622	uint16_t phy_ppdu_id;
11623	uint32_t info1;
11624	uint32_t info2;
11625	uint32_t toeplitz_hash;
11626	uint32_t flow_id_toeplitz;
11627	uint32_t info3;
11628	uint32_t ppdu_start_timestamp;
11629	uint32_t phy_meta_data;
11630	uint16_t vlan_ctag_c1;
11631	uint16_t vlan_stag_c1;
11632} __packed;
11633
11634struct rx_msdu_start_wcn6855 {
11635	uint16_t info0;
11636	uint16_t phy_ppdu_id;
11637	uint32_t info1;
11638	uint32_t info2;
11639	uint32_t toeplitz_hash;
11640	uint32_t flow_id_toeplitz;
11641	uint32_t info3;
11642	uint32_t ppdu_start_timestamp;
11643	uint32_t phy_meta_data;
11644	uint16_t vlan_ctag_ci;
11645	uint16_t vlan_stag_ci;
11646} __packed;
11647
11648/* rx_msdu_start
11649 *
11650 * rxpcu_mpdu_filter_in_category
11651 *		Field indicates what the reason was that this mpdu frame
11652 *		was allowed to come into the receive path by rxpcu. Values
11653 *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
11654 *
11655 * sw_frame_group_id
11656 *		SW processes frames based on certain classifications. Values
11657 *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
11658 *
11659 * phy_ppdu_id
11660 *		A ppdu counter value that PHY increments for every PPDU
11661 *		received. The counter value wraps around.
11662 *
11663 * msdu_length
11664 *		MSDU length in bytes after decapsulation.
11665 *
11666 * ipsec_esp
11667 *		Set if IPv4/v6 packet is using IPsec ESP.
11668 *
11669 * l3_offset
11670 *		Depending upon mode bit, this field either indicates the
11671 *		L3 offset in bytes from the start of the RX_HEADER or the IP
11672 *		offset in bytes from the start of the packet after
11673 *		decapsulation. The latter is only valid if ipv4_proto or
11674 *		ipv6_proto is set.
11675 *
11676 * ipsec_ah
11677 *		Set if IPv4/v6 packet is using IPsec AH
11678 *
11679 * l4_offset
11680 *		Depending upon mode bit, this field either indicates the
11681 *		L4 offset in bytes from the start of RX_HEADER (only valid
11682 *		if either ipv4_proto or ipv6_proto is set to 1) or indicates
11683 *		the offset in bytes to the start of TCP or UDP header from
11684 *		the start of the IP header after decapsulation (Only valid if
11685 *		tcp_proto or udp_proto is set). The value 0 indicates that
11686 *		the offset is longer than 127 bytes.
11687 *
11688 * msdu_number
11689 *		Indicates the MSDU number within a MPDU.  This value is
11690 *		reset to zero at the start of each MPDU.  If the number of
11691 *		MSDU exceeds 255 this number will wrap using modulo 256.
11692 *
11693 * decap_type
11694 *		Indicates the format after decapsulation. Values are defined in
11695 *		enum %MPDU_START_DECAP_TYPE_*.
11696 *
11697 * ipv4_proto
11698 *		Set if L2 layer indicates IPv4 protocol.
11699 *
11700 * ipv6_proto
11701 *		Set if L2 layer indicates IPv6 protocol.
11702 *
11703 * tcp_proto
11704 *		Set if the ipv4_proto or ipv6_proto are set and the IP protocol
11705 *		indicates TCP.
11706 *
11707 * udp_proto
11708 *		Set if the ipv4_proto or ipv6_proto are set and the IP protocol
11709 *		indicates UDP.
11710 *
11711 * ip_frag
11712 *		Indicates that either the IP More frag bit is set or IP frag
11713 *		number is non-zero.  If set indicates that this is a fragmented
11714 *		IP packet.
11715 *
11716 * tcp_only_ack
11717 *		Set if only the TCP Ack bit is set in the TCP flags and if
11718 *		the TCP payload is 0.
11719 *
11720 * da_is_bcast_mcast
11721 *		The destination address is broadcast or multicast.
11722 *
11723 * toeplitz_hash
11724 *		Actual chosen Hash.
11725 *		0 - Toeplitz hash of 2-tuple (IP source address, IP
11726 *		    destination address)
11727 *		1 - Toeplitz hash of 4-tuple (IP source	address,
11728 *		    IP destination address, L4 (TCP/UDP) source port,
11729 *		    L4 (TCP/UDP) destination port)
11730 *		2 - Toeplitz of flow_id
11731 *		3 - Zero is used
11732 *
11733 * ip_fixed_header_valid
11734 *		Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed
11735 *		fully within first 256 bytes of the packet
11736 *
11737 * ip_extn_header_valid
11738 *		IPv6/IPv6 header, including IPv4 options and
11739 *		recognizable extension headers parsed fully within first 256
11740 *		bytes of the packet
11741 *
11742 * tcp_udp_header_valid
11743 *		Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP
11744 *		header parsed fully within first 256 bytes of the packet
11745 *
11746 * mesh_control_present
11747 *		When set, this MSDU includes the 'Mesh Control' field
11748 *
11749 * ldpc
11750 *
11751 * ip4_protocol_ip6_next_header
11752 *		For IPv4, this is the 8 bit protocol field set). For IPv6 this
11753 *		is the 8 bit next_header field.
11754 *
11755 * toeplitz_hash_2_or_4
11756 *		Controlled by RxOLE register - If register bit set to 0,
11757 *		Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest
11758 *		addresses; otherwise, toeplitz hash is computed over 4-tuple
11759 *		IPv4 or IPv6 src/dest addresses and src/dest ports.
11760 *
11761 * flow_id_toeplitz
11762 *		Toeplitz hash of 5-tuple
11763 *		{IP source address, IP destination address, IP source port, IP
11764 *		destination port, L4 protocol}  in case of non-IPSec.
11765 *
11766 *		In case of IPSec - Toeplitz hash of 4-tuple
11767 *		{IP source address, IP destination address, SPI, L4 protocol}
11768 *
11769 *		The relevant Toeplitz key registers are provided in RxOLE's
11770 *		instance of common parser module. These registers are separate
11771 *		from the Toeplitz keys used by ASE/FSE modules inside RxOLE.
11772 *		The actual value will be passed on from common parser module
11773 *		to RxOLE in one of the WHO_* TLVs.
11774 *
11775 * user_rssi
11776 *		RSSI for this user
11777 *
11778 * pkt_type
11779 *		Values are defined in enum %RX_MSDU_START_PKT_TYPE_*.
11780 *
11781 * stbc
11782 *		When set, use STBC transmission rates.
11783 *
11784 * sgi
11785 *		Field only valid when pkt type is HT, VHT or HE. Values are
11786 *		defined in enum %RX_MSDU_START_SGI_*.
11787 *
11788 * rate_mcs
11789 *		MCS Rate used.
11790 *
11791 * receive_bandwidth
11792 *		Full receive Bandwidth. Values are defined in enum
11793 *		%RX_MSDU_START_RECV_*.
11794 *
11795 * reception_type
11796 *		Indicates what type of reception this is and defined in enum
11797 *		%RX_MSDU_START_RECEPTION_TYPE_*.
11798 *
11799 * mimo_ss_bitmap
11800 *		Field only valid when
11801 *		Reception_type is RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO or
11802 *		RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO.
11803 *
11804 *		Bitmap, with each bit indicating if the related spatial
11805 *		stream is used for this STA
11806 *
11807 *		LSB related to SS 0
11808 *
11809 *		0 - spatial stream not used for this reception
11810 *		1 - spatial stream used for this reception
11811 *
11812 * ppdu_start_timestamp
11813 *		Timestamp that indicates when the PPDU that contained this MPDU
11814 *		started on the medium.
11815 *
11816 * phy_meta_data
11817 *		SW programmed Meta data provided by the PHY. Can be used for SW
11818 *		to indicate the channel the device is on.
11819 */
11820
11821#define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER	GENMASK(1, 0)
11822#define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID	GENMASK(8, 2)
11823
11824#define RX_MSDU_END_INFO1_KEY_ID		GENMASK(7, 0)
11825#define RX_MSDU_END_INFO1_CCE_SUPER_RULE	GENMASK(13, 8)
11826#define RX_MSDU_END_INFO1_CCND_TRUNCATE		BIT(14)
11827#define RX_MSDU_END_INFO1_CCND_CCE_DIS		BIT(15)
11828#define RX_MSDU_END_INFO1_EXT_WAPI_PN		GENMASK(31, 16)
11829
11830#define RX_MSDU_END_INFO2_REPORTED_MPDU_LEN	GENMASK(13, 0)
11831#define RX_MSDU_END_INFO2_FIRST_MSDU		BIT(14)
11832#define RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855	BIT(28)
11833#define RX_MSDU_END_INFO2_LAST_MSDU		BIT(15)
11834#define RX_MSDU_END_INFO2_LAST_MSDU_WCN6855	BIT(29)
11835#define RX_MSDU_END_INFO2_SA_IDX_TIMEOUT	BIT(16)
11836#define RX_MSDU_END_INFO2_DA_IDX_TIMEOUT	BIT(17)
11837#define RX_MSDU_END_INFO2_MSDU_LIMIT_ERR	BIT(18)
11838#define RX_MSDU_END_INFO2_FLOW_IDX_TIMEOUT	BIT(19)
11839#define RX_MSDU_END_INFO2_FLOW_IDX_INVALID	BIT(20)
11840#define RX_MSDU_END_INFO2_WIFI_PARSER_ERR	BIT(21)
11841#define RX_MSDU_END_INFO2_AMSDU_PARSET_ERR	BIT(22)
11842#define RX_MSDU_END_INFO2_SA_IS_VALID		BIT(23)
11843#define RX_MSDU_END_INFO2_DA_IS_VALID		BIT(24)
11844#define RX_MSDU_END_INFO2_DA_IS_MCBC		BIT(25)
11845#define RX_MSDU_END_INFO2_L3_HDR_PADDING	GENMASK(27, 26)
11846
11847#define RX_MSDU_END_INFO3_TCP_FLAG		GENMASK(8, 0)
11848#define RX_MSDU_END_INFO3_LRO_ELIGIBLE		BIT(9)
11849
11850#define RX_MSDU_END_INFO4_DA_OFFSET		GENMASK(5, 0)
11851#define RX_MSDU_END_INFO4_SA_OFFSET		GENMASK(11, 6)
11852#define RX_MSDU_END_INFO4_DA_OFFSET_VALID	BIT(12)
11853#define RX_MSDU_END_INFO4_SA_OFFSET_VALID	BIT(13)
11854#define RX_MSDU_END_INFO4_L3_TYPE		GENMASK(31, 16)
11855
11856#define RX_MSDU_END_INFO5_MSDU_DROP		BIT(0)
11857#define RX_MSDU_END_INFO5_REO_DEST_IND		GENMASK(5, 1)
11858#define RX_MSDU_END_INFO5_FLOW_IDX		GENMASK(25, 6)
11859
11860struct rx_msdu_end_ipq8074 {
11861	uint16_t info0;
11862	uint16_t phy_ppdu_id;
11863	uint16_t ip_hdr_cksum;
11864	uint16_t tcp_udp_cksum;
11865	uint32_t info1;
11866	uint32_t ext_wapi_pn[2];
11867	uint32_t info2;
11868	uint32_t ipv6_options_crc;
11869	uint32_t tcp_seq_num;
11870	uint32_t tcp_ack_num;
11871	uint16_t info3;
11872	uint16_t window_size;
11873	uint32_t info4;
11874	uint32_t rule_indication[2];
11875	uint16_t sa_idx;
11876	uint16_t da_idx;
11877	uint32_t info5;
11878	uint32_t fse_metadata;
11879	uint16_t cce_metadata;
11880	uint16_t sa_sw_peer_id;
11881} __packed;
11882
11883struct rx_msdu_end_wcn6855 {
11884	uint16_t info0;
11885	uint16_t phy_ppdu_id;
11886	uint16_t ip_hdr_cksum;
11887	uint16_t reported_mpdu_len;
11888	uint32_t info1;
11889	uint32_t ext_wapi_pn[2];
11890	uint32_t info4;
11891	uint32_t ipv6_options_crc;
11892	uint32_t tcp_seq_num;
11893	uint32_t tcp_ack_num;
11894	uint16_t info3;
11895	uint16_t window_size;
11896	uint32_t info2;
11897	uint16_t sa_idx;
11898	uint16_t da_idx;
11899	uint32_t info5;
11900	uint32_t fse_metadata;
11901	uint16_t cce_metadata;
11902	uint16_t sa_sw_peer_id;
11903	uint32_t rule_indication[2];
11904	uint32_t info6;
11905	uint32_t info7;
11906} __packed;
11907
11908#define RX_MSDU_END_MPDU_LENGTH_INFO		GENMASK(13, 0)
11909
11910#define RX_MSDU_END_INFO2_DA_OFFSET		GENMASK(5, 0)
11911#define RX_MSDU_END_INFO2_SA_OFFSET		GENMASK(11, 6)
11912#define RX_MSDU_END_INFO2_DA_OFFSET_VALID	BIT(12)
11913#define RX_MSDU_END_INFO2_SA_OFFSET_VALID	BIT(13)
11914#define RX_MSDU_END_INFO2_L3_TYPE		GENMASK(31, 16)
11915
11916#define RX_MSDU_END_INFO4_SA_IDX_TIMEOUT	BIT(0)
11917#define RX_MSDU_END_INFO4_DA_IDX_TIMEOUT	BIT(1)
11918#define RX_MSDU_END_INFO4_MSDU_LIMIT_ERR	BIT(2)
11919#define RX_MSDU_END_INFO4_FLOW_IDX_TIMEOUT	BIT(3)
11920#define RX_MSDU_END_INFO4_FLOW_IDX_INVALID	BIT(4)
11921#define RX_MSDU_END_INFO4_WIFI_PARSER_ERR	BIT(5)
11922#define RX_MSDU_END_INFO4_AMSDU_PARSER_ERR	BIT(6)
11923#define RX_MSDU_END_INFO4_SA_IS_VALID		BIT(7)
11924#define RX_MSDU_END_INFO4_DA_IS_VALID		BIT(8)
11925#define RX_MSDU_END_INFO4_DA_IS_MCBC		BIT(9)
11926#define RX_MSDU_END_INFO4_L3_HDR_PADDING	GENMASK(11, 10)
11927#define RX_MSDU_END_INFO4_FIRST_MSDU		BIT(12)
11928#define RX_MSDU_END_INFO4_LAST_MSDU		BIT(13)
11929
11930#define RX_MSDU_END_INFO6_AGGR_COUNT		GENMASK(7, 0)
11931#define RX_MSDU_END_INFO6_FLOW_AGGR_CONTN	BIT(8)
11932#define RX_MSDU_END_INFO6_FISA_TIMEOUT		BIT(9)
11933
11934struct rx_msdu_end_qcn9074 {
11935	uint16_t info0;
11936	uint16_t phy_ppdu_id;
11937	uint16_t ip_hdr_cksum;
11938	uint16_t mpdu_length_info;
11939	uint32_t info1;
11940	uint32_t rule_indication[2];
11941	uint32_t info2;
11942	uint32_t ipv6_options_crc;
11943	uint32_t tcp_seq_num;
11944	uint32_t tcp_ack_num;
11945	uint16_t info3;
11946	uint16_t window_size;
11947	uint16_t tcp_udp_cksum;
11948	uint16_t info4;
11949	uint16_t sa_idx;
11950	uint16_t da_idx;
11951	uint32_t info5;
11952	uint32_t fse_metadata;
11953	uint16_t cce_metadata;
11954	uint16_t sa_sw_peer_id;
11955	uint32_t info6;
11956	uint16_t cum_l4_cksum;
11957	uint16_t cum_ip_length;
11958} __packed;
11959
11960/* rx_msdu_end
11961 *
11962 * rxpcu_mpdu_filter_in_category
11963 *		Field indicates what the reason was that this mpdu frame
11964 *		was allowed to come into the receive path by rxpcu. Values
11965 *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
11966 *
11967 * sw_frame_group_id
11968 *		SW processes frames based on certain classifications. Values
11969 *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
11970 *
11971 * phy_ppdu_id
11972 *		A ppdu counter value that PHY increments for every PPDU
11973 *		received. The counter value wraps around.
11974 *
11975 * ip_hdr_cksum
11976 *		This can include the IP header checksum or the pseudo
11977 *		header checksum used by TCP/UDP checksum.
11978 *
11979 * tcp_udp_chksum
11980 *		The value of the computed TCP/UDP checksum.  A mode bit
11981 *		selects whether this checksum is the full checksum or the
11982 *		partial checksum which does not include the pseudo header.
11983 *
11984 * key_id
11985 *		The key ID octet from the IV. Only valid when first_msdu is set.
11986 *
11987 * cce_super_rule
11988 *		Indicates the super filter rule.
11989 *
11990 * cce_classify_not_done_truncate
11991 *		Classification failed due to truncated frame.
11992 *
11993 * cce_classify_not_done_cce_dis
11994 *		Classification failed due to CCE global disable
11995 *
11996 * ext_wapi_pn*
11997 *		Extension PN (packet number) which is only used by WAPI.
11998 *
11999 * reported_mpdu_length
12000 *		MPDU length before decapsulation. Only valid when first_msdu is
12001 *		set. This field is taken directly from the length field of the
12002 *		A-MPDU delimiter or the preamble length field for non-A-MPDU
12003 *		frames.
12004 *
12005 * first_msdu
12006 *		Indicates the first MSDU of A-MSDU. If both first_msdu and
12007 *		last_msdu are set in the MSDU then this is a non-aggregated MSDU
12008 *		frame: normal MPDU. Interior MSDU in an A-MSDU shall have both
12009 *		first_mpdu and last_mpdu bits set to 0.
12010 *
12011 * last_msdu
12012 *		Indicates the last MSDU of the A-MSDU. MPDU end status is only
12013 *		valid when last_msdu is set.
12014 *
12015 * sa_idx_timeout
12016 *		Indicates an unsuccessful MAC source address search due to the
12017 *		expiring of the search timer.
12018 *
12019 * da_idx_timeout
12020 *		Indicates an unsuccessful MAC destination address search due to
12021 *		the expiring of the search timer.
12022 *
12023 * msdu_limit_error
12024 *		Indicates that the MSDU threshold was exceeded and thus all the
12025 *		rest of the MSDUs will not be scattered and will not be
12026 *		decapsulated but will be DMA'ed in RAW format as a single MSDU.
12027 *
12028 * flow_idx_timeout
12029 *		Indicates an unsuccessful flow search due to the expiring of
12030 *		the search timer.
12031 *
12032 * flow_idx_invalid
12033 *		flow id is not valid.
12034 *
12035 * amsdu_parser_error
12036 *		A-MSDU could not be properly de-agregated.
12037 *
12038 * sa_is_valid
12039 *		Indicates that OLE found a valid SA entry.
12040 *
12041 * da_is_valid
12042 *		Indicates that OLE found a valid DA entry.
12043 *
12044 * da_is_mcbc
12045 *		Field Only valid if da_is_valid is set. Indicates the DA address
12046 *		was a Multicast of Broadcast address.
12047 *
12048 * l3_header_padding
12049 *		Number of bytes padded  to make sure that the L3 header will
12050 *		always start of a Dword boundary.
12051 *
12052 * ipv6_options_crc
12053 *		32 bit CRC computed out of  IP v6 extension headers.
12054 *
12055 * tcp_seq_number
12056 *		TCP sequence number.
12057 *
12058 * tcp_ack_number
12059 *		TCP acknowledge number.
12060 *
12061 * tcp_flag
12062 *		TCP flags {NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN}.
12063 *
12064 * lro_eligible
12065 *		Computed out of TCP and IP fields to indicate that this
12066 *		MSDU is eligible for LRO.
12067 *
12068 * window_size
12069 *		TCP receive window size.
12070 *
12071 * da_offset
12072 *		Offset into MSDU buffer for DA.
12073 *
12074 * sa_offset
12075 *		Offset into MSDU buffer for SA.
12076 *
12077 * da_offset_valid
12078 *		da_offset field is valid. This will be set to 0 in case
12079 *		of a dynamic A-MSDU when DA is compressed.
12080 *
12081 * sa_offset_valid
12082 *		sa_offset field is valid. This will be set to 0 in case
12083 *		of a dynamic A-MSDU when SA is compressed.
12084 *
12085 * l3_type
12086 *		The 16-bit type value indicating the type of L3 later
12087 *		extracted from LLC/SNAP, set to zero if SNAP is not
12088 *		available.
12089 *
12090 * rule_indication
12091 *		Bitmap indicating which of rules have matched.
12092 *
12093 * sa_idx
12094 *		The offset in the address table which matches MAC source address
12095 *
12096 * da_idx
12097 *		The offset in the address table which matches MAC destination
12098 *		address.
12099 *
12100 * msdu_drop
12101 *		REO shall drop this MSDU and not forward it to any other ring.
12102 *
12103 * reo_destination_indication
12104 *		The id of the reo exit ring where the msdu frame shall push
12105 *		after (MPDU level) reordering has finished. Values are defined
12106 *		in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_.
12107 *
12108 * flow_idx
12109 *		Flow table index.
12110 *
12111 * fse_metadata
12112 *		FSE related meta data.
12113 *
12114 * cce_metadata
12115 *		CCE related meta data.
12116 *
12117 * sa_sw_peer_id
12118 *		sw_peer_id from the address search entry corresponding to the
12119 *		source address of the MSDU.
12120 */
12121
12122enum rx_mpdu_end_rxdma_dest_ring {
12123	RX_MPDU_END_RXDMA_DEST_RING_RELEASE,
12124	RX_MPDU_END_RXDMA_DEST_RING_FW,
12125	RX_MPDU_END_RXDMA_DEST_RING_SW,
12126	RX_MPDU_END_RXDMA_DEST_RING_REO,
12127};
12128
12129#define RX_MPDU_END_INFO1_UNSUP_KTYPE_SHORT_FRAME	BIT(11)
12130#define RX_MPDU_END_INFO1_RX_IN_TX_DECRYPT_BYT		BIT(12)
12131#define RX_MPDU_END_INFO1_OVERFLOW_ERR			BIT(13)
12132#define RX_MPDU_END_INFO1_MPDU_LEN_ERR			BIT(14)
12133#define RX_MPDU_END_INFO1_TKIP_MIC_ERR			BIT(15)
12134#define RX_MPDU_END_INFO1_DECRYPT_ERR			BIT(16)
12135#define RX_MPDU_END_INFO1_UNENCRYPTED_FRAME_ERR		BIT(17)
12136#define RX_MPDU_END_INFO1_PN_FIELDS_VALID		BIT(18)
12137#define RX_MPDU_END_INFO1_FCS_ERR			BIT(19)
12138#define RX_MPDU_END_INFO1_MSDU_LEN_ERR			BIT(20)
12139#define RX_MPDU_END_INFO1_RXDMA0_DEST_RING		GENMASK(22, 21)
12140#define RX_MPDU_END_INFO1_RXDMA1_DEST_RING		GENMASK(24, 23)
12141#define RX_MPDU_END_INFO1_DECRYPT_STATUS_CODE		GENMASK(27, 25)
12142#define RX_MPDU_END_INFO1_RX_BITMAP_NOT_UPD		BIT(28)
12143
12144struct rx_mpdu_end {
12145	uint16_t info0;
12146	uint16_t phy_ppdu_id;
12147	uint32_t info1;
12148} __packed;
12149
12150/* rx_mpdu_end
12151 *
12152 * rxpcu_mpdu_filter_in_category
12153 *		Field indicates what the reason was that this mpdu frame
12154 *		was allowed to come into the receive path by rxpcu. Values
12155 *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
12156 *
12157 * sw_frame_group_id
12158 *		SW processes frames based on certain classifications. Values
12159 *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
12160 *
12161 * phy_ppdu_id
12162 *		A ppdu counter value that PHY increments for every PPDU
12163 *		received. The counter value wraps around.
12164 *
12165 * unsup_ktype_short_frame
12166 *		This bit will be '1' when WEP or TKIP or WAPI key type is
12167 *		received for 11ah short frame. Crypto will bypass the received
12168 *		packet without decryption to RxOLE after setting this bit.
12169 *
12170 * rx_in_tx_decrypt_byp
12171 *		Indicates that RX packet is not decrypted as Crypto is
12172 *		busy with TX packet processing.
12173 *
12174 * overflow_err
12175 *		RXPCU Receive FIFO ran out of space to receive the full MPDU.
12176 *		Therefore this MPDU is terminated early and is thus corrupted.
12177 *
12178 *		This MPDU will not be ACKed.
12179 *
12180 *		RXPCU might still be able to correctly receive the following
12181 *		MPDUs in the PPDU if enough fifo space became available in time.
12182 *
12183 * mpdu_length_err
12184 *		Set by RXPCU if the expected MPDU length does not correspond
12185 *		with the actually received number of bytes in the MPDU.
12186 *
12187 * tkip_mic_err
12188 *		Set by Rx crypto when crypto detected a TKIP MIC error for
12189 *		this MPDU.
12190 *
12191 * decrypt_err
12192 *		Set by RX CRYPTO when CRYPTO detected a decrypt error for this
12193 *		MPDU or CRYPTO received an encrypted frame, but did not get a
12194 *		valid corresponding key id in the peer entry.
12195 *
12196 * unencrypted_frame_err
12197 *		Set by RX CRYPTO when CRYPTO detected an unencrypted frame while
12198 *		in the peer entry field 'All_frames_shall_be_encrypted' is set.
12199 *
12200 * pn_fields_contain_valid_info
12201 *		Set by RX CRYPTO to indicate that there is a valid PN field
12202 *		present in this MPDU.
12203 *
12204 * fcs_err
12205 *		Set by RXPCU when there is an FCS error detected for this MPDU.
12206 *
12207 * msdu_length_err
12208 *		Set by RXOLE when there is an msdu length error detected
12209 *		in at least 1 of the MSDUs embedded within the MPDU.
12210 *
12211 * rxdma0_destination_ring
12212 * rxdma1_destination_ring
12213 *		The ring to which RXDMA0/1 shall push the frame, assuming
12214 *		no MPDU level errors are detected. In case of MPDU level
12215 *		errors, RXDMA0/1 might change the RXDMA0/1 destination. Values
12216 *		are defined in %enum RX_MPDU_END_RXDMA_DEST_RING_*.
12217 *
12218 * decrypt_status_code
12219 *		Field provides insight into the decryption performed. Values
12220 *		are defined in enum %RX_DESC_DECRYPT_STATUS_CODE_*.
12221 *
12222 * rx_bitmap_not_updated
12223 *		Frame is received, but RXPCU could not update the receive bitmap
12224 *		due to (temporary) fifo constraints.
12225 */
12226
12227/* Padding bytes to avoid TLV's spanning across 128 byte boundary */
12228#define HAL_RX_DESC_PADDING0_BYTES	4
12229#define HAL_RX_DESC_PADDING1_BYTES	16
12230
12231#define HAL_RX_DESC_HDR_STATUS_LEN	120
12232
12233struct hal_rx_desc_ipq8074 {
12234	uint32_t msdu_end_tag;
12235	struct rx_msdu_end_ipq8074 msdu_end;
12236	uint32_t rx_attn_tag;
12237	struct rx_attention attention;
12238	uint32_t msdu_start_tag;
12239	struct rx_msdu_start_ipq8074 msdu_start;
12240	uint8_t rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
12241	uint32_t mpdu_start_tag;
12242	struct rx_mpdu_start_ipq8074 mpdu_start;
12243	uint32_t mpdu_end_tag;
12244	struct rx_mpdu_end mpdu_end;
12245	uint8_t rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
12246	uint32_t hdr_status_tag;
12247	uint32_t phy_ppdu_id;
12248	uint8_t hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
12249	uint8_t msdu_payload[];
12250} __packed;
12251
12252struct hal_rx_desc_qcn9074 {
12253	uint32_t msdu_end_tag;
12254	struct rx_msdu_end_qcn9074 msdu_end;
12255	uint32_t rx_attn_tag;
12256	struct rx_attention attention;
12257	uint32_t msdu_start_tag;
12258	struct rx_msdu_start_qcn9074 msdu_start;
12259	uint8_t rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
12260	uint32_t mpdu_start_tag;
12261	struct rx_mpdu_start_qcn9074 mpdu_start;
12262	uint32_t mpdu_end_tag;
12263	struct rx_mpdu_end mpdu_end;
12264	uint8_t rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
12265	uint32_t hdr_status_tag;
12266	uint32_t phy_ppdu_id;
12267	uint8_t hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
12268	uint8_t msdu_payload[];
12269} __packed;
12270
12271struct hal_rx_desc_wcn6855 {
12272	uint32_t msdu_end_tag;
12273	struct rx_msdu_end_wcn6855 msdu_end;
12274	uint32_t rx_attn_tag;
12275	struct rx_attention attention;
12276	uint32_t msdu_start_tag;
12277	struct rx_msdu_start_wcn6855 msdu_start;
12278	uint8_t rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
12279	uint32_t mpdu_start_tag;
12280	struct rx_mpdu_start_wcn6855 mpdu_start;
12281	uint32_t mpdu_end_tag;
12282	struct rx_mpdu_end mpdu_end;
12283	uint8_t rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
12284	uint32_t hdr_status_tag;
12285	uint32_t phy_ppdu_id;
12286	uint8_t hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
12287	uint8_t msdu_payload[];
12288} __packed;
12289
12290struct hal_rx_desc {
12291	union {
12292		struct hal_rx_desc_ipq8074 ipq8074;
12293		struct hal_rx_desc_qcn9074 qcn9074;
12294		struct hal_rx_desc_wcn6855 wcn6855;
12295	} u;
12296} __packed;
12297
12298#define HAL_RX_RU_ALLOC_TYPE_MAX 6
12299#define RU_26  1
12300#define RU_52  2
12301#define RU_106 4
12302#define RU_242 9
12303#define RU_484 18
12304#define RU_996 37
12305
12306/*
12307 * dp.h
12308 */
12309
12310/* HTT definitions */
12311
12312#define HTT_TCL_META_DATA_TYPE			BIT(0)
12313#define HTT_TCL_META_DATA_VALID_HTT		BIT(1)
12314
12315/* vdev meta data */
12316#define HTT_TCL_META_DATA_VDEV_ID		GENMASK(9, 2)
12317#define HTT_TCL_META_DATA_PDEV_ID		GENMASK(11, 10)
12318#define HTT_TCL_META_DATA_HOST_INSPECTED	BIT(12)
12319
12320/* peer meta data */
12321#define HTT_TCL_META_DATA_PEER_ID		GENMASK(15, 2)
12322
12323#define HTT_TX_WBM_COMP_STATUS_OFFSET 8
12324
12325#define HTT_INVALID_PEER_ID	0xffff
12326
12327/* HTT tx completion is overlaid in wbm_release_ring */
12328#define HTT_TX_WBM_COMP_INFO0_STATUS		GENMASK(12, 9)
12329#define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON	GENMASK(16, 13)
12330#define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON	GENMASK(16, 13)
12331
12332#define HTT_TX_WBM_COMP_INFO1_ACK_RSSI		GENMASK(31, 24)
12333#define HTT_TX_WBM_COMP_INFO2_SW_PEER_ID	GENMASK(15, 0)
12334#define HTT_TX_WBM_COMP_INFO2_VALID		BIT(21)
12335
12336struct htt_tx_wbm_completion {
12337	uint32_t info0;
12338	uint32_t info1;
12339	uint32_t info2;
12340	uint32_t info3;
12341} __packed;
12342
12343enum htt_h2t_msg_type {
12344	HTT_H2T_MSG_TYPE_VERSION_REQ		= 0,
12345	HTT_H2T_MSG_TYPE_SRING_SETUP		= 0xb,
12346	HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG	= 0xc,
12347	HTT_H2T_MSG_TYPE_EXT_STATS_CFG		= 0x10,
12348	HTT_H2T_MSG_TYPE_PPDU_STATS_CFG		= 0x11,
12349	HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE	= 0x17,
12350};
12351
12352#define HTT_VER_REQ_INFO_MSG_ID		GENMASK(7, 0)
12353
12354struct htt_ver_req_cmd {
12355	uint32_t ver_reg_info;
12356} __packed;
12357
12358enum htt_srng_ring_type {
12359	HTT_HW_TO_SW_RING,
12360	HTT_SW_TO_HW_RING,
12361	HTT_SW_TO_SW_RING,
12362};
12363
12364enum htt_srng_ring_id {
12365	HTT_RXDMA_HOST_BUF_RING,
12366	HTT_RXDMA_MONITOR_STATUS_RING,
12367	HTT_RXDMA_MONITOR_BUF_RING,
12368	HTT_RXDMA_MONITOR_DESC_RING,
12369	HTT_RXDMA_MONITOR_DEST_RING,
12370	HTT_HOST1_TO_FW_RXBUF_RING,
12371	HTT_HOST2_TO_FW_RXBUF_RING,
12372	HTT_RXDMA_NON_MONITOR_DEST_RING,
12373};
12374
12375/* host -> target  HTT_SRING_SETUP message
12376 *
12377 * After target is booted up, Host can send SRING setup message for
12378 * each host facing LMAC SRING. Target setups up HW registers based
12379 * on setup message and confirms back to Host if response_required is set.
12380 * Host should wait for confirmation message before sending new SRING
12381 * setup message
12382 *
12383 * The message would appear as follows:
12384 *
12385 * |31            24|23    20|19|18 16|15|14          8|7                0|
12386 * |--------------- +-----------------+----------------+------------------|
12387 * |    ring_type   |      ring_id    |    pdev_id     |     msg_type     |
12388 * |----------------------------------------------------------------------|
12389 * |                          ring_base_addr_lo                           |
12390 * |----------------------------------------------------------------------|
12391 * |                         ring_base_addr_hi                            |
12392 * |----------------------------------------------------------------------|
12393 * |ring_misc_cfg_flag|ring_entry_size|            ring_size              |
12394 * |----------------------------------------------------------------------|
12395 * |                         ring_head_offset32_remote_addr_lo            |
12396 * |----------------------------------------------------------------------|
12397 * |                         ring_head_offset32_remote_addr_hi            |
12398 * |----------------------------------------------------------------------|
12399 * |                         ring_tail_offset32_remote_addr_lo            |
12400 * |----------------------------------------------------------------------|
12401 * |                         ring_tail_offset32_remote_addr_hi            |
12402 * |----------------------------------------------------------------------|
12403 * |                          ring_msi_addr_lo                            |
12404 * |----------------------------------------------------------------------|
12405 * |                          ring_msi_addr_hi                            |
12406 * |----------------------------------------------------------------------|
12407 * |                          ring_msi_data                               |
12408 * |----------------------------------------------------------------------|
12409 * |         intr_timer_th            |IM|      intr_batch_counter_th     |
12410 * |----------------------------------------------------------------------|
12411 * |          reserved        |RR|PTCF|        intr_low_threshold         |
12412 * |----------------------------------------------------------------------|
12413 * Where
12414 *     IM = sw_intr_mode
12415 *     RR = response_required
12416 *     PTCF = prefetch_timer_cfg
12417 *
12418 * The message is interpreted as follows:
12419 * dword0  - b'0:7   - msg_type: This will be set to
12420 *                     HTT_H2T_MSG_TYPE_SRING_SETUP
12421 *           b'8:15  - pdev_id:
12422 *                     0 (for rings at SOC/UMAC level),
12423 *                     1/2/3 mac id (for rings at LMAC level)
12424 *           b'16:23 - ring_id: identify which ring is to setup,
12425 *                     more details can be got from enum htt_srng_ring_id
12426 *           b'24:31 - ring_type: identify type of host rings,
12427 *                     more details can be got from enum htt_srng_ring_type
12428 * dword1  - b'0:31  - ring_base_addr_lo: Lower 32bits of ring base address
12429 * dword2  - b'0:31  - ring_base_addr_hi: Upper 32bits of ring base address
12430 * dword3  - b'0:15  - ring_size: size of the ring in unit of 4-bytes words
12431 *           b'16:23 - ring_entry_size: Size of each entry in 4-byte word units
12432 *           b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and
12433 *                     SW_TO_HW_RING.
12434 *                     Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs.
12435 * dword4  - b'0:31  - ring_head_off32_remote_addr_lo:
12436 *                     Lower 32 bits of memory address of the remote variable
12437 *                     storing the 4-byte word offset that identifies the head
12438 *                     element within the ring.
12439 *                     (The head offset variable has type uint32_t.)
12440 *                     Valid for HW_TO_SW and SW_TO_SW rings.
12441 * dword5  - b'0:31  - ring_head_off32_remote_addr_hi:
12442 *                     Upper 32 bits of memory address of the remote variable
12443 *                     storing the 4-byte word offset that identifies the head
12444 *                     element within the ring.
12445 *                     (The head offset variable has type uint32_t.)
12446 *                     Valid for HW_TO_SW and SW_TO_SW rings.
12447 * dword6  - b'0:31  - ring_tail_off32_remote_addr_lo:
12448 *                     Lower 32 bits of memory address of the remote variable
12449 *                     storing the 4-byte word offset that identifies the tail
12450 *                     element within the ring.
12451 *                     (The tail offset variable has type uint32_t.)
12452 *                     Valid for HW_TO_SW and SW_TO_SW rings.
12453 * dword7  - b'0:31  - ring_tail_off32_remote_addr_hi:
12454 *                     Upper 32 bits of memory address of the remote variable
12455 *                     storing the 4-byte word offset that identifies the tail
12456 *                     element within the ring.
12457 *                     (The tail offset variable has type uint32_t.)
12458 *                     Valid for HW_TO_SW and SW_TO_SW rings.
12459 * dword8  - b'0:31  - ring_msi_addr_lo: Lower 32bits of MSI cfg address
12460 *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
12461 * dword9  - b'0:31  - ring_msi_addr_hi: Upper 32bits of MSI cfg address
12462 *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
12463 * dword10 - b'0:31  - ring_msi_data: MSI data
12464 *                     Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs
12465 *                     valid only for HW_TO_SW_RING and SW_TO_HW_RING
12466 * dword11 - b'0:14  - intr_batch_counter_th:
12467 *                     batch counter threshold is in units of 4-byte words.
12468 *                     HW internally maintains and increments batch count.
12469 *                     (see SRING spec for detail description).
12470 *                     When batch count reaches threshold value, an interrupt
12471 *                     is generated by HW.
12472 *           b'15    - sw_intr_mode:
12473 *                     This configuration shall be static.
12474 *                     Only programmed at power up.
12475 *                     0: generate pulse style sw interrupts
12476 *                     1: generate level style sw interrupts
12477 *           b'16:31 - intr_timer_th:
12478 *                     The timer init value when timer is idle or is
12479 *                     initialized to start downcounting.
12480 *                     In 8us units (to cover a range of 0 to 524 ms)
12481 * dword12 - b'0:15  - intr_low_threshold:
12482 *                     Used only by Consumer ring to generate ring_sw_int_p.
12483 *                     Ring entries low threshold water mark, that is used
12484 *                     in combination with the interrupt timer as well as
12485 *                     the clearing of the level interrupt.
12486 *           b'16:18 - prefetch_timer_cfg:
12487 *                     Used only by Consumer ring to set timer mode to
12488 *                     support Application prefetch handling.
12489 *                     The external tail offset/pointer will be updated
12490 *                     at following intervals:
12491 *                     3'b000: (Prefetch feature disabled; used only for debug)
12492 *                     3'b001: 1 usec
12493 *                     3'b010: 4 usec
12494 *                     3'b011: 8 usec (default)
12495 *                     3'b100: 16 usec
12496 *                     Others: Reserved
12497 *           b'19    - response_required:
12498 *                     Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
12499 *           b'20:31 - reserved:  reserved for future use
12500 */
12501
12502#define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE	GENMASK(7, 0)
12503#define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID	GENMASK(15, 8)
12504#define HTT_SRNG_SETUP_CMD_INFO0_RING_ID	GENMASK(23, 16)
12505#define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE	GENMASK(31, 24)
12506
12507#define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE			GENMASK(15, 0)
12508#define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE		GENMASK(23, 16)
12509#define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS		BIT(25)
12510#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP		BIT(27)
12511#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP	BIT(28)
12512#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP		BIT(29)
12513
12514#define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH	GENMASK(14, 0)
12515#define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE		BIT(15)
12516#define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH		GENMASK(31, 16)
12517
12518#define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH	GENMASK(15, 0)
12519#define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG	BIT(16)
12520#define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED	BIT(19)
12521
12522struct htt_srng_setup_cmd {
12523	uint32_t info0;
12524	uint32_t ring_base_addr_lo;
12525	uint32_t ring_base_addr_hi;
12526	uint32_t info1;
12527	uint32_t ring_head_off32_remote_addr_lo;
12528	uint32_t ring_head_off32_remote_addr_hi;
12529	uint32_t ring_tail_off32_remote_addr_lo;
12530	uint32_t ring_tail_off32_remote_addr_hi;
12531	uint32_t ring_msi_addr_lo;
12532	uint32_t ring_msi_addr_hi;
12533	uint32_t msi_data;
12534	uint32_t intr_info;
12535	uint32_t info2;
12536} __packed;
12537
12538/* host -> target FW  PPDU_STATS config message
12539 *
12540 * @details
12541 * The following field definitions describe the format of the HTT host
12542 * to target FW for PPDU_STATS_CFG msg.
12543 * The message allows the host to configure the PPDU_STATS_IND messages
12544 * produced by the target.
12545 *
12546 * |31          24|23          16|15           8|7            0|
12547 * |-----------------------------------------------------------|
12548 * |    REQ bit mask             |   pdev_mask  |   msg type   |
12549 * |-----------------------------------------------------------|
12550 * Header fields:
12551 *  - MSG_TYPE
12552 *    Bits 7:0
12553 *    Purpose: identifies this is a req to configure ppdu_stats_ind from target
12554 *    Value: 0x11
12555 *  - PDEV_MASK
12556 *    Bits 8:15
12557 *    Purpose: identifies which pdevs this PPDU stats configuration applies to
12558 *    Value: This is a overloaded field, refer to usage and interpretation of
12559 *           PDEV in interface document.
12560 *           Bit   8    :  Reserved for SOC stats
12561 *           Bit 9 - 15 :  Indicates PDEV_MASK in DBDC
12562 *                         Indicates MACID_MASK in DBS
12563 *  - REQ_TLV_BIT_MASK
12564 *    Bits 16:31
12565 *    Purpose: each set bit indicates the corresponding PPDU stats TLV type
12566 *        needs to be included in the target's PPDU_STATS_IND messages.
12567 *    Value: refer htt_ppdu_stats_tlv_tag_t <<<???
12568 *
12569 */
12570
12571struct htt_ppdu_stats_cfg_cmd {
12572	uint32_t msg;
12573} __packed;
12574
12575#define HTT_PPDU_STATS_CFG_MSG_TYPE		GENMASK(7, 0)
12576#define HTT_PPDU_STATS_CFG_SOC_STATS		BIT(8)
12577#define HTT_PPDU_STATS_CFG_PDEV_ID		GENMASK(15, 9)
12578#define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK	GENMASK(31, 16)
12579
12580enum htt_ppdu_stats_tag_type {
12581	HTT_PPDU_STATS_TAG_COMMON,
12582	HTT_PPDU_STATS_TAG_USR_COMMON,
12583	HTT_PPDU_STATS_TAG_USR_RATE,
12584	HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64,
12585	HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256,
12586	HTT_PPDU_STATS_TAG_SCH_CMD_STATUS,
12587	HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON,
12588	HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64,
12589	HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256,
12590	HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS,
12591	HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH,
12592	HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY,
12593	HTT_PPDU_STATS_TAG_INFO,
12594	HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD,
12595
12596	/* New TLV's are added above to this line */
12597	HTT_PPDU_STATS_TAG_MAX,
12598};
12599
12600#define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \
12601				   | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \
12602				   | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \
12603				   | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \
12604				   | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \
12605				   | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \
12606				   | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \
12607				   | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY))
12608
12609#define HTT_PPDU_STATS_TAG_PKTLOG  (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \
12610				    BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \
12611				    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \
12612				    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \
12613				    BIT(HTT_PPDU_STATS_TAG_INFO) | \
12614				    BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \
12615				    HTT_PPDU_STATS_TAG_DEFAULT)
12616
12617/* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message
12618 *
12619 * details:
12620 *    HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to
12621 *    configure RXDMA rings.
12622 *    The configuration is per ring based and includes both packet subtypes
12623 *    and PPDU/MPDU TLVs.
12624 *
12625 *    The message would appear as follows:
12626 *
12627 *    |31       26|25|24|23            16|15             8|7             0|
12628 *    |-----------------+----------------+----------------+---------------|
12629 *    |   rsvd1   |PS|SS|     ring_id    |     pdev_id    |    msg_type   |
12630 *    |-------------------------------------------------------------------|
12631 *    |              rsvd2               |           ring_buffer_size     |
12632 *    |-------------------------------------------------------------------|
12633 *    |                        packet_type_enable_flags_0                 |
12634 *    |-------------------------------------------------------------------|
12635 *    |                        packet_type_enable_flags_1                 |
12636 *    |-------------------------------------------------------------------|
12637 *    |                        packet_type_enable_flags_2                 |
12638 *    |-------------------------------------------------------------------|
12639 *    |                        packet_type_enable_flags_3                 |
12640 *    |-------------------------------------------------------------------|
12641 *    |                         tlv_filter_in_flags                       |
12642 *    |-------------------------------------------------------------------|
12643 * Where:
12644 *     PS = pkt_swap
12645 *     SS = status_swap
12646 * The message is interpreted as follows:
12647 * dword0 - b'0:7   - msg_type: This will be set to
12648 *                    HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
12649 *          b'8:15  - pdev_id:
12650 *                    0 (for rings at SOC/UMAC level),
12651 *                    1/2/3 mac id (for rings at LMAC level)
12652 *          b'16:23 - ring_id : Identify the ring to configure.
12653 *                    More details can be got from enum htt_srng_ring_id
12654 *          b'24    - status_swap: 1 is to swap status TLV
12655 *          b'25    - pkt_swap:  1 is to swap packet TLV
12656 *          b'26:31 - rsvd1:  reserved for future use
12657 * dword1 - b'0:16  - ring_buffer_size: size of buffers referenced by rx ring,
12658 *                    in byte units.
12659 *                    Valid only for HW_TO_SW_RING and SW_TO_HW_RING
12660 *        - b'16:31 - rsvd2: Reserved for future use
12661 * dword2 - b'0:31  - packet_type_enable_flags_0:
12662 *                    Enable MGMT packet from 0b0000 to 0b1001
12663 *                    bits from low to high: FP, MD, MO - 3 bits
12664 *                        FP: Filter_Pass
12665 *                        MD: Monitor_Direct
12666 *                        MO: Monitor_Other
12667 *                    10 mgmt subtypes * 3 bits -> 30 bits
12668 *                    Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs
12669 * dword3 - b'0:31  - packet_type_enable_flags_1:
12670 *                    Enable MGMT packet from 0b1010 to 0b1111
12671 *                    bits from low to high: FP, MD, MO - 3 bits
12672 *                    Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs
12673 * dword4 - b'0:31 -  packet_type_enable_flags_2:
12674 *                    Enable CTRL packet from 0b0000 to 0b1001
12675 *                    bits from low to high: FP, MD, MO - 3 bits
12676 *                    Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs
12677 * dword5 - b'0:31  - packet_type_enable_flags_3:
12678 *                    Enable CTRL packet from 0b1010 to 0b1111,
12679 *                    MCAST_DATA, UCAST_DATA, NULL_DATA
12680 *                    bits from low to high: FP, MD, MO - 3 bits
12681 *                    Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs
12682 * dword6 - b'0:31 -  tlv_filter_in_flags:
12683 *                    Filter in Attention/MPDU/PPDU/Header/User tlvs
12684 *                    Refer to CFG_TLV_FILTER_IN_FLAG defs
12685 */
12686
12687#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE	GENMASK(7, 0)
12688#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID	GENMASK(15, 8)
12689#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID	GENMASK(23, 16)
12690#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS		BIT(24)
12691#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS		BIT(25)
12692
12693#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE	GENMASK(15, 0)
12694
12695enum htt_rx_filter_tlv_flags {
12696	HTT_RX_FILTER_TLV_FLAGS_MPDU_START		= BIT(0),
12697	HTT_RX_FILTER_TLV_FLAGS_MSDU_START		= BIT(1),
12698	HTT_RX_FILTER_TLV_FLAGS_RX_PACKET		= BIT(2),
12699	HTT_RX_FILTER_TLV_FLAGS_MSDU_END		= BIT(3),
12700	HTT_RX_FILTER_TLV_FLAGS_MPDU_END		= BIT(4),
12701	HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER		= BIT(5),
12702	HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER		= BIT(6),
12703	HTT_RX_FILTER_TLV_FLAGS_ATTENTION		= BIT(7),
12704	HTT_RX_FILTER_TLV_FLAGS_PPDU_START		= BIT(8),
12705	HTT_RX_FILTER_TLV_FLAGS_PPDU_END		= BIT(9),
12706	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS	= BIT(10),
12707	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT	= BIT(11),
12708	HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE	= BIT(12),
12709};
12710
12711enum htt_rx_mgmt_pkt_filter_tlv_flags0 {
12712	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ		= BIT(0),
12713	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ		= BIT(1),
12714	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ		= BIT(2),
12715	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP		= BIT(3),
12716	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP		= BIT(4),
12717	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP		= BIT(5),
12718	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ	= BIT(6),
12719	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ	= BIT(7),
12720	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ	= BIT(8),
12721	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP	= BIT(9),
12722	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP	= BIT(10),
12723	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP	= BIT(11),
12724	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ		= BIT(12),
12725	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ		= BIT(13),
12726	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ		= BIT(14),
12727	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP		= BIT(15),
12728	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP		= BIT(16),
12729	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP		= BIT(17),
12730	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV	= BIT(18),
12731	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV	= BIT(19),
12732	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV	= BIT(20),
12733	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7		= BIT(21),
12734	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7		= BIT(22),
12735	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7		= BIT(23),
12736	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON		= BIT(24),
12737	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON		= BIT(25),
12738	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON		= BIT(26),
12739	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM		= BIT(27),
12740	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM		= BIT(28),
12741	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM		= BIT(29),
12742};
12743
12744enum htt_rx_mgmt_pkt_filter_tlv_flags1 {
12745	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC		= BIT(0),
12746	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC		= BIT(1),
12747	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC		= BIT(2),
12748	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH		= BIT(3),
12749	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH		= BIT(4),
12750	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH		= BIT(5),
12751	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH		= BIT(6),
12752	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH		= BIT(7),
12753	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH		= BIT(8),
12754	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION		= BIT(9),
12755	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION		= BIT(10),
12756	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION		= BIT(11),
12757	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK	= BIT(12),
12758	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK	= BIT(13),
12759	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK	= BIT(14),
12760	HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15	= BIT(15),
12761	HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15	= BIT(16),
12762	HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15	= BIT(17),
12763};
12764
12765enum htt_rx_ctrl_pkt_filter_tlv_flags2 {
12766	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1	= BIT(0),
12767	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1	= BIT(1),
12768	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1	= BIT(2),
12769	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2	= BIT(3),
12770	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2	= BIT(4),
12771	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2	= BIT(5),
12772	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER	= BIT(6),
12773	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER	= BIT(7),
12774	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER	= BIT(8),
12775	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4	= BIT(9),
12776	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4	= BIT(10),
12777	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4	= BIT(11),
12778	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL	= BIT(12),
12779	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL	= BIT(13),
12780	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL	= BIT(14),
12781	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP	= BIT(15),
12782	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP	= BIT(16),
12783	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP	= BIT(17),
12784	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT	= BIT(18),
12785	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT	= BIT(19),
12786	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT	= BIT(20),
12787	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER	= BIT(21),
12788	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER	= BIT(22),
12789	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER	= BIT(23),
12790	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR		= BIT(24),
12791	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR		= BIT(25),
12792	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR		= BIT(26),
12793	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA			= BIT(27),
12794	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA			= BIT(28),
12795	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA			= BIT(29),
12796};
12797
12798enum htt_rx_ctrl_pkt_filter_tlv_flags3 {
12799	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL		= BIT(0),
12800	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL		= BIT(1),
12801	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL		= BIT(2),
12802	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS		= BIT(3),
12803	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS		= BIT(4),
12804	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS		= BIT(5),
12805	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS		= BIT(6),
12806	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS		= BIT(7),
12807	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS		= BIT(8),
12808	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK		= BIT(9),
12809	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK		= BIT(10),
12810	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK		= BIT(11),
12811	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND		= BIT(12),
12812	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND		= BIT(13),
12813	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND		= BIT(14),
12814	HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK		= BIT(15),
12815	HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK		= BIT(16),
12816	HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK		= BIT(17),
12817};
12818
12819enum htt_rx_data_pkt_filter_tlv_flasg3 {
12820	HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST	= BIT(18),
12821	HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST	= BIT(19),
12822	HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST	= BIT(20),
12823	HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST	= BIT(21),
12824	HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST	= BIT(22),
12825	HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST	= BIT(23),
12826	HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA	= BIT(24),
12827	HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA	= BIT(25),
12828	HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA	= BIT(26),
12829};
12830
12831#define HTT_RX_FP_MGMT_FILTER_FLAGS0 \
12832	(HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
12833	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
12834	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
12835	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
12836	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
12837	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
12838	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
12839	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
12840	| HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
12841
12842#define HTT_RX_MD_MGMT_FILTER_FLAGS0 \
12843	(HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
12844	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
12845	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
12846	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
12847	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
12848	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
12849	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
12850	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
12851	| HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
12852
12853#define HTT_RX_MO_MGMT_FILTER_FLAGS0 \
12854	(HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \
12855	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \
12856	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \
12857	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \
12858	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \
12859	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \
12860	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \
12861	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \
12862	| HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM)
12863
12864#define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
12865				     | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
12866				     | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
12867				     | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
12868				     | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
12869
12870#define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
12871				     | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
12872				     | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
12873				     | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
12874				     | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
12875
12876#define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \
12877				     | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \
12878				     | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \
12879				     | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \
12880				     | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK)
12881
12882#define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
12883				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
12884				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
12885
12886#define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
12887				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
12888				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
12889
12890#define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \
12891				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \
12892				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA)
12893
12894#define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
12895				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
12896				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
12897				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
12898				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
12899				     | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
12900
12901#define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
12902				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
12903				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
12904				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
12905				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
12906				     | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
12907
12908#define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \
12909				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \
12910				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \
12911				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \
12912				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \
12913				     | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK)
12914
12915#define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
12916				     | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
12917				     | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
12918
12919#define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
12920				     | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
12921				     | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
12922
12923#define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \
12924				     | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \
12925				     | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA)
12926
12927#define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \
12928		(HTT_RX_FP_MGMT_FILTER_FLAGS0 | \
12929		HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
12930
12931#define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \
12932		(HTT_RX_MO_MGMT_FILTER_FLAGS0 | \
12933		HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7)
12934
12935#define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \
12936		(HTT_RX_FP_MGMT_FILTER_FLAGS1 | \
12937		HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
12938
12939#define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \
12940		(HTT_RX_MO_MGMT_FILTER_FLAGS1 | \
12941		HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15)
12942
12943#define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \
12944		(HTT_RX_FP_CTRL_FILTER_FLASG2 | \
12945		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
12946		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
12947		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
12948		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
12949		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
12950		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
12951		HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
12952
12953#define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \
12954		(HTT_RX_MO_CTRL_FILTER_FLASG2 | \
12955		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \
12956		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \
12957		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \
12958		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \
12959		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \
12960		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \
12961		HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT)
12962
12963#define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3
12964
12965#define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3
12966
12967#define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3
12968
12969#define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3
12970
12971#define HTT_RX_MON_FILTER_TLV_FLAGS \
12972		(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
12973		HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
12974		HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
12975		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
12976		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
12977		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
12978
12979#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \
12980		(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
12981		HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \
12982		HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \
12983		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \
12984		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \
12985		HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE)
12986
12987#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \
12988		(HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \
12989		HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \
12990		HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \
12991		HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \
12992		HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \
12993		HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \
12994		HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \
12995		HTT_RX_FILTER_TLV_FLAGS_ATTENTION)
12996
12997struct htt_rx_ring_selection_cfg_cmd {
12998	uint32_t info0;
12999	uint32_t info1;
13000	uint32_t pkt_type_en_flags0;
13001	uint32_t pkt_type_en_flags1;
13002	uint32_t pkt_type_en_flags2;
13003	uint32_t pkt_type_en_flags3;
13004	uint32_t rx_filter_tlv;
13005} __packed;
13006
13007struct htt_rx_ring_tlv_filter {
13008	uint32_t rx_filter; /* see htt_rx_filter_tlv_flags */
13009	uint32_t pkt_filter_flags0; /* MGMT */
13010	uint32_t pkt_filter_flags1; /* MGMT */
13011	uint32_t pkt_filter_flags2; /* CTRL */
13012	uint32_t pkt_filter_flags3; /* DATA */
13013};
13014
13015#define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE	GENMASK(7, 0)
13016#define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID	GENMASK(15, 8)
13017
13018#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE			BIT(0)
13019#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END		BIT(1)
13020#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END	BIT(2)
13021#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING		GENMASK(10, 3)
13022
13023/* Enumeration for full monitor mode destination ring select
13024 * 0 - REO destination ring select
13025 * 1 - FW destination ring select
13026 * 2 - SW destination ring select
13027 * 3 - Release destination ring select
13028 */
13029enum htt_rx_full_mon_release_ring {
13030	HTT_RX_MON_RING_REO,
13031	HTT_RX_MON_RING_FW,
13032	HTT_RX_MON_RING_SW,
13033	HTT_RX_MON_RING_RELEASE,
13034};
13035
13036struct htt_rx_full_monitor_mode_cfg_cmd {
13037	uint32_t info0;
13038	uint32_t cfg;
13039} __packed;
13040
13041/* HTT message target->host */
13042
13043enum htt_t2h_msg_type {
13044	HTT_T2H_MSG_TYPE_VERSION_CONF,
13045	HTT_T2H_MSG_TYPE_PEER_MAP	= 0x3,
13046	HTT_T2H_MSG_TYPE_PEER_UNMAP	= 0x4,
13047	HTT_T2H_MSG_TYPE_RX_ADDBA	= 0x5,
13048	HTT_T2H_MSG_TYPE_PKTLOG		= 0x8,
13049	HTT_T2H_MSG_TYPE_SEC_IND	= 0xb,
13050	HTT_T2H_MSG_TYPE_PEER_MAP2	= 0x1e,
13051	HTT_T2H_MSG_TYPE_PEER_UNMAP2	= 0x1f,
13052	HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d,
13053	HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c,
13054	HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
13055};
13056
13057#define HTT_TARGET_VERSION_MAJOR 3
13058
13059#define HTT_T2H_MSG_TYPE		GENMASK(7, 0)
13060#define HTT_T2H_VERSION_CONF_MINOR	GENMASK(15, 8)
13061#define HTT_T2H_VERSION_CONF_MAJOR	GENMASK(23, 16)
13062
13063struct htt_t2h_version_conf_msg {
13064	uint32_t version;
13065} __packed;
13066
13067#define HTT_T2H_PEER_MAP_INFO_VDEV_ID	GENMASK(15, 8)
13068#define HTT_T2H_PEER_MAP_INFO_PEER_ID	GENMASK(31, 16)
13069#define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16	GENMASK(15, 0)
13070#define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID	GENMASK(31, 16)
13071#define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL	GENMASK(15, 0)
13072#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M	BIT(16)
13073#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S	16
13074
13075struct htt_t2h_peer_map_event {
13076	uint32_t info;
13077	uint32_t mac_addr_l32;
13078	uint32_t info1;
13079	uint32_t info2;
13080} __packed;
13081
13082#define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID	HTT_T2H_PEER_MAP_INFO_VDEV_ID
13083#define HTT_T2H_PEER_UNMAP_INFO_PEER_ID	HTT_T2H_PEER_MAP_INFO_PEER_ID
13084#define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \
13085					HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16
13086#define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M
13087#define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S
13088
13089struct htt_t2h_peer_unmap_event {
13090	uint32_t info;
13091	uint32_t mac_addr_l32;
13092	uint32_t info1;
13093} __packed;
13094
13095struct htt_resp_msg {
13096	union {
13097		struct htt_t2h_version_conf_msg version_msg;
13098		struct htt_t2h_peer_map_event peer_map_ev;
13099		struct htt_t2h_peer_unmap_event peer_unmap_ev;
13100	};
13101} __packed;
13102
13103#define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8)
13104#define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16)
13105#define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24)
13106
13107#define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0)
13108#define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16)
13109
13110#define HTT_BACKPRESSURE_UMAC_RING_TYPE	0
13111#define HTT_BACKPRESSURE_LMAC_RING_TYPE	1
13112
13113enum htt_backpressure_umac_ringid {
13114	HTT_SW_RING_IDX_REO_REO2SW1_RING,
13115	HTT_SW_RING_IDX_REO_REO2SW2_RING,
13116	HTT_SW_RING_IDX_REO_REO2SW3_RING,
13117	HTT_SW_RING_IDX_REO_REO2SW4_RING,
13118	HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING,
13119	HTT_SW_RING_IDX_REO_REO2TCL_RING,
13120	HTT_SW_RING_IDX_REO_REO2FW_RING,
13121	HTT_SW_RING_IDX_REO_REO_RELEASE_RING,
13122	HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING,
13123	HTT_SW_RING_IDX_TCL_TCL2TQM_RING,
13124	HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING,
13125	HTT_SW_RING_IDX_WBM_REO_RELEASE_RING,
13126	HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING,
13127	HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING,
13128	HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING,
13129	HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING,
13130	HTT_SW_RING_IDX_REO_REO_CMD_RING,
13131	HTT_SW_RING_IDX_REO_REO_STATUS_RING,
13132	HTT_SW_UMAC_RING_IDX_MAX,
13133};
13134
13135enum htt_backpressure_lmac_ringid {
13136	HTT_SW_RING_IDX_FW2RXDMA_BUF_RING,
13137	HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING,
13138	HTT_SW_RING_IDX_FW2RXDMA_LINK_RING,
13139	HTT_SW_RING_IDX_SW2RXDMA_BUF_RING,
13140	HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING,
13141	HTT_SW_RING_IDX_RXDMA2FW_RING,
13142	HTT_SW_RING_IDX_RXDMA2SW_RING,
13143	HTT_SW_RING_IDX_RXDMA2RELEASE_RING,
13144	HTT_SW_RING_IDX_RXDMA2REO_RING,
13145	HTT_SW_RING_IDX_MONITOR_STATUS_RING,
13146	HTT_SW_RING_IDX_MONITOR_BUF_RING,
13147	HTT_SW_RING_IDX_MONITOR_DESC_RING,
13148	HTT_SW_RING_IDX_MONITOR_DEST_RING,
13149	HTT_SW_LMAC_RING_IDX_MAX,
13150};
13151
13152/* ppdu stats
13153 *
13154 * @details
13155 * The following field definitions describe the format of the HTT target
13156 * to host ppdu stats indication message.
13157 *
13158 *
13159 * |31                         16|15   12|11   10|9      8|7            0 |
13160 * |----------------------------------------------------------------------|
13161 * |    payload_size             | rsvd  |pdev_id|mac_id  |    msg type   |
13162 * |----------------------------------------------------------------------|
13163 * |                          ppdu_id                                     |
13164 * |----------------------------------------------------------------------|
13165 * |                        Timestamp in us                               |
13166 * |----------------------------------------------------------------------|
13167 * |                          reserved                                    |
13168 * |----------------------------------------------------------------------|
13169 * |                    type-specific stats info                          |
13170 * |                     (see htt_ppdu_stats.h)                           |
13171 * |----------------------------------------------------------------------|
13172 * Header fields:
13173 *  - MSG_TYPE
13174 *    Bits 7:0
13175 *    Purpose: Identifies this is a PPDU STATS indication
13176 *             message.
13177 *    Value: 0x1d
13178 *  - mac_id
13179 *    Bits 9:8
13180 *    Purpose: mac_id of this ppdu_id
13181 *    Value: 0-3
13182 *  - pdev_id
13183 *    Bits 11:10
13184 *    Purpose: pdev_id of this ppdu_id
13185 *    Value: 0-3
13186 *     0 (for rings at SOC level),
13187 *     1/2/3 PDEV -> 0/1/2
13188 *  - payload_size
13189 *    Bits 31:16
13190 *    Purpose: total tlv size
13191 *    Value: payload_size in bytes
13192 */
13193
13194#define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10)
13195#define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16)
13196
13197struct ath12k_htt_ppdu_stats_msg {
13198	uint32_t info;
13199	uint32_t ppdu_id;
13200	uint32_t timestamp;
13201	uint32_t rsvd;
13202	uint8_t data[];
13203} __packed;
13204
13205struct htt_tlv {
13206	uint32_t header;
13207	uint8_t *value;
13208} __packed;
13209
13210#define HTT_TLV_TAG			GENMASK(11, 0)
13211#define HTT_TLV_LEN			GENMASK(23, 12)
13212
13213enum HTT_PPDU_STATS_BW {
13214	HTT_PPDU_STATS_BANDWIDTH_5MHZ   = 0,
13215	HTT_PPDU_STATS_BANDWIDTH_10MHZ  = 1,
13216	HTT_PPDU_STATS_BANDWIDTH_20MHZ  = 2,
13217	HTT_PPDU_STATS_BANDWIDTH_40MHZ  = 3,
13218	HTT_PPDU_STATS_BANDWIDTH_80MHZ  = 4,
13219	HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */
13220	HTT_PPDU_STATS_BANDWIDTH_DYN    = 6,
13221};
13222
13223#define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M	GENMASK(7, 0)
13224#define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M	GENMASK(15, 8)
13225/* bw - HTT_PPDU_STATS_BW */
13226#define HTT_PPDU_STATS_CMN_FLAGS_BW_M		GENMASK(19, 16)
13227
13228struct htt_ppdu_stats_common {
13229	uint32_t ppdu_id;
13230	uint16_t sched_cmdid;
13231	uint8_t ring_id;
13232	uint8_t num_users;
13233	uint32_t flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/
13234	uint32_t chain_mask;
13235	uint32_t fes_duration_us; /* frame exchange sequence */
13236	uint32_t ppdu_sch_eval_start_tstmp_us;
13237	uint32_t ppdu_sch_end_tstmp_us;
13238	uint32_t ppdu_start_tstmp_us;
13239	/* BIT [15 :  0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted
13240	 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted
13241	 */
13242	uint16_t phy_mode;
13243	uint16_t bw_mhz;
13244} __packed;
13245
13246enum htt_ppdu_stats_gi {
13247	HTT_PPDU_STATS_SGI_0_8_US,
13248	HTT_PPDU_STATS_SGI_0_4_US,
13249	HTT_PPDU_STATS_SGI_1_6_US,
13250	HTT_PPDU_STATS_SGI_3_2_US,
13251};
13252
13253#define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M	GENMASK(3, 0)
13254#define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M	GENMASK(11, 4)
13255
13256#define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M	BIT(0)
13257#define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M	GENMASK(5, 1)
13258
13259#define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M	GENMASK(1, 0)
13260#define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M		BIT(2)
13261#define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M		BIT(3)
13262#define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M		GENMASK(7, 4)
13263#define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M		GENMASK(11, 8)
13264#define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M		GENMASK(15, 12)
13265#define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M		GENMASK(19, 16)
13266#define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M	GENMASK(23, 20)
13267#define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M		GENMASK(27, 24)
13268#define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M		BIT(28)
13269#define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M		BIT(29)
13270
13271#define HTT_USR_RATE_PREAMBLE(_val) \
13272		FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val)
13273#define HTT_USR_RATE_BW(_val) \
13274		FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val)
13275#define HTT_USR_RATE_NSS(_val) \
13276		FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val)
13277#define HTT_USR_RATE_MCS(_val) \
13278		FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val)
13279#define HTT_USR_RATE_GI(_val) \
13280		FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val)
13281#define HTT_USR_RATE_DCM(_val) \
13282		FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val)
13283
13284#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M		GENMASK(1, 0)
13285#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M		BIT(2)
13286#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M		BIT(3)
13287#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M		GENMASK(7, 4)
13288#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M		GENMASK(11, 8)
13289#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M		GENMASK(15, 12)
13290#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M		GENMASK(19, 16)
13291#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M		GENMASK(23, 20)
13292#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M		GENMASK(27, 24)
13293#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M		BIT(28)
13294#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M		BIT(29)
13295
13296struct htt_ppdu_stats_user_rate {
13297	uint8_t tid_num;
13298	uint8_t reserved0;
13299	uint16_t sw_peer_id;
13300	uint32_t info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/
13301	uint16_t ru_end;
13302	uint16_t ru_start;
13303	uint16_t resp_ru_end;
13304	uint16_t resp_ru_start;
13305	uint32_t info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */
13306	uint32_t rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */
13307	/* Note: resp_rate_info is only valid for if resp_type is UL */
13308	uint32_t resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */
13309} __packed;
13310
13311#define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M		GENMASK(7, 0)
13312#define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M		BIT(8)
13313#define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M	GENMASK(10, 9)
13314#define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M		GENMASK(13, 11)
13315#define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M		BIT(14)
13316#define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M		GENMASK(31, 16)
13317
13318#define HTT_TX_INFO_IS_AMSDU(_flags) \
13319			FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags)
13320#define HTT_TX_INFO_BA_ACK_FAILED(_flags) \
13321			FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags)
13322#define HTT_TX_INFO_RATECODE(_flags) \
13323			FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags)
13324#define HTT_TX_INFO_PEERID(_flags) \
13325			FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags)
13326
13327struct htt_tx_ppdu_stats_info {
13328	struct htt_tlv tlv_hdr;
13329	uint32_t tx_success_bytes;
13330	uint32_t tx_retry_bytes;
13331	uint32_t tx_failed_bytes;
13332	uint32_t flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */
13333	uint16_t tx_success_msdus;
13334	uint16_t tx_retry_msdus;
13335	uint16_t tx_failed_msdus;
13336	uint16_t tx_duration; /* united in us */
13337} __packed;
13338
13339enum  htt_ppdu_stats_usr_compln_status {
13340	HTT_PPDU_STATS_USER_STATUS_OK,
13341	HTT_PPDU_STATS_USER_STATUS_FILTERED,
13342	HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT,
13343	HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH,
13344	HTT_PPDU_STATS_USER_STATUS_ABORT,
13345};
13346
13347#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M	GENMASK(3, 0)
13348#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M	GENMASK(7, 4)
13349#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M		BIT(8)
13350#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M		GENMASK(12, 9)
13351
13352#define HTT_USR_CMPLTN_IS_AMPDU(_val) \
13353	    FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val)
13354#define HTT_USR_CMPLTN_LONG_RETRY(_val) \
13355	    FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val)
13356#define HTT_USR_CMPLTN_SHORT_RETRY(_val) \
13357	    FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val)
13358
13359struct htt_ppdu_stats_usr_cmpltn_cmn {
13360	uint8_t status;
13361	uint8_t tid_num;
13362	uint16_t sw_peer_id;
13363	/* RSSI value of last ack packet (units = dB above noise floor) */
13364	uint32_t ack_rssi;
13365	uint16_t mpdu_tried;
13366	uint16_t mpdu_success;
13367	uint32_t flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/
13368} __packed;
13369
13370#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M	GENMASK(8, 0)
13371#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M	GENMASK(24, 9)
13372#define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM	GENMASK(31, 25)
13373
13374#define HTT_PPDU_STATS_NON_QOS_TID	16
13375
13376struct htt_ppdu_stats_usr_cmpltn_ack_ba_status {
13377	uint32_t ppdu_id;
13378	uint16_t sw_peer_id;
13379	uint16_t reserved0;
13380	uint32_t info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */
13381	uint16_t current_seq;
13382	uint16_t start_seq;
13383	uint32_t success_bytes;
13384} __packed;
13385
13386struct htt_ppdu_stats_usr_cmn_array {
13387	struct htt_tlv tlv_hdr;
13388	uint32_t num_ppdu_stats;
13389	/* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info
13390	 * elements.
13391	 * tx_ppdu_stats_info is variable length, with length =
13392	 *     number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info)
13393	 */
13394	struct htt_tx_ppdu_stats_info tx_ppdu_info[];
13395} __packed;
13396
13397struct htt_ppdu_user_stats {
13398	uint16_t peer_id;
13399	uint32_t tlv_flags;
13400	bool is_valid_peer_id;
13401	struct htt_ppdu_stats_user_rate rate;
13402	struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn;
13403	struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba;
13404};
13405
13406#define HTT_PPDU_STATS_MAX_USERS	8
13407#define HTT_PPDU_DESC_MAX_DEPTH	16
13408
13409struct htt_ppdu_stats {
13410	struct htt_ppdu_stats_common common;
13411	struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS];
13412};
13413
13414struct htt_ppdu_stats_info {
13415	uint32_t ppdu_id;
13416	struct htt_ppdu_stats ppdu_stats;
13417#if 0
13418	struct list_head list;
13419#endif
13420};
13421
13422/* @brief target -> host packet log message
13423 *
13424 * @details
13425 * The following field definitions describe the format of the packet log
13426 * message sent from the target to the host.
13427 * The message consists of a 4-octet header,followed by a variable number
13428 * of 32-bit character values.
13429 *
13430 * |31                         16|15  12|11   10|9    8|7            0|
13431 * |------------------------------------------------------------------|
13432 * |        payload_size         | rsvd |pdev_id|mac_id|   msg type   |
13433 * |------------------------------------------------------------------|
13434 * |                              payload                             |
13435 * |------------------------------------------------------------------|
13436 *   - MSG_TYPE
13437 *     Bits 7:0
13438 *     Purpose: identifies this as a pktlog message
13439 *     Value: HTT_T2H_MSG_TYPE_PKTLOG
13440 *   - mac_id
13441 *     Bits 9:8
13442 *     Purpose: identifies which MAC/PHY instance generated this pktlog info
13443 *     Value: 0-3
13444 *   - pdev_id
13445 *     Bits 11:10
13446 *     Purpose: pdev_id
13447 *     Value: 0-3
13448 *     0 (for rings at SOC level),
13449 *     1/2/3 PDEV -> 0/1/2
13450 *   - payload_size
13451 *     Bits 31:16
13452 *     Purpose: explicitly specify the payload size
13453 *     Value: payload size in bytes (payload size is a multiple of 4 bytes)
13454 */
13455struct htt_pktlog_msg {
13456	uint32_t hdr;
13457	uint8_t payload[];
13458};
13459
13460/* @brief host -> target FW extended statistics retrieve
13461 *
13462 * @details
13463 * The following field definitions describe the format of the HTT host
13464 * to target FW extended stats retrieve message.
13465 * The message specifies the type of stats the host wants to retrieve.
13466 *
13467 * |31          24|23          16|15           8|7            0|
13468 * |-----------------------------------------------------------|
13469 * |   reserved   | stats type   |   pdev_mask  |   msg type   |
13470 * |-----------------------------------------------------------|
13471 * |                   config param [0]                        |
13472 * |-----------------------------------------------------------|
13473 * |                   config param [1]                        |
13474 * |-----------------------------------------------------------|
13475 * |                   config param [2]                        |
13476 * |-----------------------------------------------------------|
13477 * |                   config param [3]                        |
13478 * |-----------------------------------------------------------|
13479 * |                         reserved                          |
13480 * |-----------------------------------------------------------|
13481 * |                        cookie LSBs                        |
13482 * |-----------------------------------------------------------|
13483 * |                        cookie MSBs                        |
13484 * |-----------------------------------------------------------|
13485 * Header fields:
13486 *  - MSG_TYPE
13487 *    Bits 7:0
13488 *    Purpose: identifies this is a extended stats upload request message
13489 *    Value: 0x10
13490 *  - PDEV_MASK
13491 *    Bits 8:15
13492 *    Purpose: identifies the mask of PDEVs to retrieve stats from
13493 *    Value: This is a overloaded field, refer to usage and interpretation of
13494 *           PDEV in interface document.
13495 *           Bit   8    :  Reserved for SOC stats
13496 *           Bit 9 - 15 :  Indicates PDEV_MASK in DBDC
13497 *                         Indicates MACID_MASK in DBS
13498 *  - STATS_TYPE
13499 *    Bits 23:16
13500 *    Purpose: identifies which FW statistics to upload
13501 *    Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h)
13502 *  - Reserved
13503 *    Bits 31:24
13504 *  - CONFIG_PARAM [0]
13505 *    Bits 31:0
13506 *    Purpose: give an opaque configuration value to the specified stats type
13507 *    Value: stats-type specific configuration value
13508 *           Refer to htt_stats.h for interpretation for each stats sub_type
13509 *  - CONFIG_PARAM [1]
13510 *    Bits 31:0
13511 *    Purpose: give an opaque configuration value to the specified stats type
13512 *    Value: stats-type specific configuration value
13513 *           Refer to htt_stats.h for interpretation for each stats sub_type
13514 *  - CONFIG_PARAM [2]
13515 *    Bits 31:0
13516 *    Purpose: give an opaque configuration value to the specified stats type
13517 *    Value: stats-type specific configuration value
13518 *           Refer to htt_stats.h for interpretation for each stats sub_type
13519 *  - CONFIG_PARAM [3]
13520 *    Bits 31:0
13521 *    Purpose: give an opaque configuration value to the specified stats type
13522 *    Value: stats-type specific configuration value
13523 *           Refer to htt_stats.h for interpretation for each stats sub_type
13524 *  - Reserved [31:0] for future use.
13525 *  - COOKIE_LSBS
13526 *    Bits 31:0
13527 *    Purpose: Provide a mechanism to match a target->host stats confirmation
13528 *        message with its preceding host->target stats request message.
13529 *    Value: LSBs of the opaque cookie specified by the host-side requestor
13530 *  - COOKIE_MSBS
13531 *    Bits 31:0
13532 *    Purpose: Provide a mechanism to match a target->host stats confirmation
13533 *        message with its preceding host->target stats request message.
13534 *    Value: MSBs of the opaque cookie specified by the host-side requestor
13535 */
13536
13537struct htt_ext_stats_cfg_hdr {
13538	uint8_t msg_type;
13539	uint8_t pdev_mask;
13540	uint8_t stats_type;
13541	uint8_t reserved;
13542} __packed;
13543
13544struct htt_ext_stats_cfg_cmd {
13545	struct htt_ext_stats_cfg_hdr hdr;
13546	uint32_t cfg_param0;
13547	uint32_t cfg_param1;
13548	uint32_t cfg_param2;
13549	uint32_t cfg_param3;
13550	uint32_t reserved;
13551	uint32_t cookie_lsb;
13552	uint32_t cookie_msb;
13553} __packed;
13554
13555/* htt stats config default params */
13556#define HTT_STAT_DEFAULT_RESET_START_OFFSET 0
13557#define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff
13558#define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff
13559#define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff
13560#define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff
13561#define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff
13562#define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00
13563#define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00
13564
13565/* HTT_DBG_EXT_STATS_PEER_INFO
13566 * PARAMS:
13567 * @config_param0:
13568 *  [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request
13569 *  [Bit15 : Bit 1] htt_peer_stats_req_mode_t
13570 *  [Bit31 : Bit16] sw_peer_id
13571 * @config_param1:
13572 *  peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum)
13573 *   0 bit htt_peer_stats_cmn_tlv
13574 *   1 bit htt_peer_details_tlv
13575 *   2 bit htt_tx_peer_rate_stats_tlv
13576 *   3 bit htt_rx_peer_rate_stats_tlv
13577 *   4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv
13578 *   5 bit htt_rx_tid_stats_tlv
13579 *   6 bit htt_msdu_flow_stats_tlv
13580 * @config_param2: [Bit31 : Bit0] mac_addr31to0
13581 * @config_param3: [Bit15 : Bit0] mac_addr47to32
13582 *                [Bit31 : Bit16] reserved
13583 */
13584#define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0)
13585#define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f
13586
13587/* Used to set different configs to the specified stats type.*/
13588struct htt_ext_stats_cfg_params {
13589	uint32_t cfg0;
13590	uint32_t cfg1;
13591	uint32_t cfg2;
13592	uint32_t cfg3;
13593};
13594
13595/* @brief target -> host extended statistics upload
13596 *
13597 * @details
13598 * The following field definitions describe the format of the HTT target
13599 * to host stats upload confirmation message.
13600 * The message contains a cookie echoed from the HTT host->target stats
13601 * upload request, which identifies which request the confirmation is
13602 * for, and a single stats can span over multiple HTT stats indication
13603 * due to the HTT message size limitation so every HTT ext stats indication
13604 * will have tag-length-value stats information elements.
13605 * The tag-length header for each HTT stats IND message also includes a
13606 * status field, to indicate whether the request for the stat type in
13607 * question was fully met, partially met, unable to be met, or invalid
13608 * (if the stat type in question is disabled in the target).
13609 * A Done bit 1's indicate the end of the of stats info elements.
13610 *
13611 *
13612 * |31                         16|15    12|11|10 8|7   5|4       0|
13613 * |--------------------------------------------------------------|
13614 * |                   reserved                   |    msg type   |
13615 * |--------------------------------------------------------------|
13616 * |                         cookie LSBs                          |
13617 * |--------------------------------------------------------------|
13618 * |                         cookie MSBs                          |
13619 * |--------------------------------------------------------------|
13620 * |      stats entry length     | rsvd   | D|  S |   stat type   |
13621 * |--------------------------------------------------------------|
13622 * |                   type-specific stats info                   |
13623 * |                      (see htt_stats.h)                       |
13624 * |--------------------------------------------------------------|
13625 * Header fields:
13626 *  - MSG_TYPE
13627 *    Bits 7:0
13628 *    Purpose: Identifies this is a extended statistics upload confirmation
13629 *             message.
13630 *    Value: 0x1c
13631 *  - COOKIE_LSBS
13632 *    Bits 31:0
13633 *    Purpose: Provide a mechanism to match a target->host stats confirmation
13634 *        message with its preceding host->target stats request message.
13635 *    Value: LSBs of the opaque cookie specified by the host-side requestor
13636 *  - COOKIE_MSBS
13637 *    Bits 31:0
13638 *    Purpose: Provide a mechanism to match a target->host stats confirmation
13639 *        message with its preceding host->target stats request message.
13640 *    Value: MSBs of the opaque cookie specified by the host-side requestor
13641 *
13642 * Stats Information Element tag-length header fields:
13643 *  - STAT_TYPE
13644 *    Bits 7:0
13645 *    Purpose: identifies the type of statistics info held in the
13646 *        following information element
13647 *    Value: htt_dbg_ext_stats_type
13648 *  - STATUS
13649 *    Bits 10:8
13650 *    Purpose: indicate whether the requested stats are present
13651 *    Value: htt_dbg_ext_stats_status
13652 *  - DONE
13653 *    Bits 11
13654 *    Purpose:
13655 *        Indicates the completion of the stats entry, this will be the last
13656 *        stats conf HTT segment for the requested stats type.
13657 *    Value:
13658 *        0 -> the stats retrieval is ongoing
13659 *        1 -> the stats retrieval is complete
13660 *  - LENGTH
13661 *    Bits 31:16
13662 *    Purpose: indicate the stats information size
13663 *    Value: This field specifies the number of bytes of stats information
13664 *       that follows the element tag-length header.
13665 *       It is expected but not required that this length is a multiple of
13666 *       4 bytes.
13667 */
13668
13669#define HTT_T2H_EXT_STATS_INFO1_DONE	BIT(11)
13670#define HTT_T2H_EXT_STATS_INFO1_LENGTH   GENMASK(31, 16)
13671
13672struct ath12k_htt_extd_stats_msg {
13673	uint32_t info0;
13674	uint64_t cookie;
13675	uint32_t info1;
13676	uint8_t data[];
13677} __packed;
13678
13679#define	HTT_MAC_ADDR_L32_0	GENMASK(7, 0)
13680#define	HTT_MAC_ADDR_L32_1	GENMASK(15, 8)
13681#define	HTT_MAC_ADDR_L32_2	GENMASK(23, 16)
13682#define	HTT_MAC_ADDR_L32_3	GENMASK(31, 24)
13683#define	HTT_MAC_ADDR_H16_0	GENMASK(7, 0)
13684#define	HTT_MAC_ADDR_H16_1	GENMASK(15, 8)
13685