qlareg.h revision 1.6
1/* $OpenBSD: qlareg.h,v 1.6 2014/04/05 12:49:27 jmatthew Exp $ */ 2 3/* 4 * Copyright (c) 2013, 2014 Jonathan Matthew <jmatthew@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19/* firmware loading */ 20#define QLA_2100_CODE_ORG 0x1000 21#define QLA_2200_CODE_ORG 0x1000 22#define QLA_2300_CODE_ORG 0x0800 23 24/* firmware attributes */ 25#define QLA_FW_ATTR_EXPANDED_LUN 0x0002 26#define QLA_FW_ATTR_FABRIC 0x0004 27#define QLA_FW_ATTR_2K_LOGINS 0x0100 28 29/* interrupt types */ 30#define QLA_INT_TYPE_MBOX 1 31#define QLA_INT_TYPE_ASYNC 2 32#define QLA_INT_TYPE_IO 3 33#define QLA_INT_TYPE_OTHER 4 34 35/* 23xx interrupt status codes */ 36#define QLA_23XX_INT_ROM_MBOX 0x01 37#define QLA_23XX_INT_ROM_MBOX_FAIL 0x02 38#define QLA_23XX_INT_MBOX 0x10 39#define QLA_23XX_INT_MBOX_FAIL 0x11 40#define QLA_23XX_INT_ASYNC 0x12 41#define QLA_23XX_INT_RSPQ 0x13 42#define QLA_23XX_INT_FP16 0x15 43#define QLA_23XX_INT_FP_SCSI 0x16 44#define QLA_23XX_INT_FP_CTIO 0x17 45 46/* ISP registers */ 47#define QLA_FLASH_BIOS_ADDR 0x00 48#define QLA_FLASH_BIOS_DATA 0x02 49#define QLA_CTRL_STATUS 0x06 50#define QLA_INT_CTRL 0x08 51#define QLA_INT_STATUS 0x0A 52#define QLA_SEMA 0x0C 53#define QLA_NVRAM 0x0E 54#define QLA_REQ_IN 0x10 55#define QLA_REQ_OUT 0x12 56#define QLA_RESP_IN 0x14 57#define QLA_RESP_OUT 0x16 58#define QLA_RISC_STATUS_LOW 0x18 59#define QLA_RISC_STATUS_HIGH 0x1A 60#define QLA_HOST_CMD_CTRL 0xC0 61#define QLA_GPIO_DATA 0xCC 62#define QLA_GPIO_ENABLE 0xCE 63 64#define QLA_FPM_DIAG 0x96 65 66 67/* mailbox base moves around between generations */ 68#define QLA_MBOX_BASE_23XX 0x40 69#define QLA_MBOX_BASE_2100 0x10 70#define QLA_MBOX_BASE_2200 0x10 71 72/* QLA_CTRL_STATUS */ 73#define QLA_CTRL_RESET 0x0001 74#define QLA_CTRL_RISC_REGS 0x0000 75#define QLA_CTRL_FB_REGS 0x0010 76#define QLA_CTRL_FPM0_REGS 0x0020 77#define QLA_CTRL_FPM1_REGS 0x0030 78 79/* QLA_INT_STATUS */ 80#define QLA_INT_REQ 0x8000 81#define QLA_RISC_INT_REQ 0x0008 82 83/* QLA_SEMA */ 84#define QLA_SEMA_STATUS 0x0002 85#define QLA_SEMA_LOCK 0x0001 86 87/* QLA_NVRAM */ 88#define QLA_NVRAM_DATA_IN 0x0008 89#define QLA_NVRAM_DATA_OUT 0x0004 90#define QLA_NVRAM_CHIP_SEL 0x0002 91#define QLA_NVRAM_CLOCK 0x0001 92#define QLA_NVRAM_CMD_READ 6 93 94 95/* QLA_RISC_STATUS LOW/HIGH */ 96#define QLA_INT_INFO_SHIFT 16 97#define QLA_RISC_HOST_INT_REQ 0x8000 98#define QLA_RISC_PAUSED 0x0100 99#define QLA_INT_STATUS_MASK 0x00FF 100 101/* QLA_HOST_CMD_CTRL write */ 102#define QLA_HOST_CMD_SHIFT 12 103#define QLA_HOST_CMD_NOP 0x0 104#define QLA_HOST_CMD_RESET 0x1 105#define QLA_HOST_CMD_PAUSE 0x2 106#define QLA_HOST_CMD_RELEASE 0x3 107#define QLA_HOST_CMD_MASK_PARITY 0x4 108#define QLA_HOST_CMD_SET_HOST_INT 0x5 109#define QLA_HOST_CMD_CLR_HOST_INT 0x6 110#define QLA_HOST_CMD_CLR_RISC_INT 0x7 111#define QLA_HOST_CMD_ENABLE_PARITY 0xA 112#define QLA_HOST_CMD_PARITY_ERROR 0xE 113 114/* QLA_HOST_CMD_CTRL read */ 115#define QLA_HOST_STATUS_HOST_INT 0x0080 116#define QLA_HOST_STATUS_RISC_RESET 0x0040 117#define QLA_HOST_STATUS_RISC_PAUSE 0x0020 118#define QLA_HOST_STATUS_RISC_EXT 0x0010 119 120/* QLA_FPM_DIAG */ 121#define QLA_FPM_RESET 0x0100 122 123/* QLA_MBOX_BASE (reg 0) read */ 124#define QLA_MBOX_HAS_STATUS 0x4000 125#define QLA_MBOX_COMPLETE 0x4000 126#define QLA_MBOX_INVALID 0x4001 127#define QLA_MBOX_INTF_ERROR 0x4002 128#define QLA_MBOX_TEST_FAILED 0x4003 129#define QLA_MBOX_CMD_ERROR 0x4005 130#define QLA_MBOX_CMD_PARAM 0x4006 131#define QLA_MBOX_PORT_USED 0x4007 132#define QLA_MBOX_LOOP_USED 0x4008 133#define QLA_MBOX_ALL_IDS_USED 0x4009 134#define QLA_MBOX_NOT_LOGGED_IN 0x400A 135#define QLA_MBOX_LINK_DOWN 0x400B 136#define QLA_ASYNC_SYSTEM_ERROR 0x8002 137#define QLA_ASYNC_REQ_XFER_ERROR 0x8003 138#define QLA_ASYNC_RSP_XFER_ERROR 0x8004 139#define QLA_ASYNC_LIP_OCCURRED 0x8010 140#define QLA_ASYNC_LOOP_UP 0x8011 141#define QLA_ASYNC_LOOP_DOWN 0x8012 142#define QLA_ASYNC_LIP_RESET 0x8013 143#define QLA_ASYNC_PORT_DB_CHANGE 0x8014 144#define QLA_ASYNC_CHANGE_NOTIFY 0x8015 145#define QLA_ASYNC_LIP_F8 0x8016 146#define QLA_ASYNC_LOOP_INIT_ERROR 0x8017 147#define QLA_ASYNC_LOGIN_REJECT 0x8018 148#define QLA_ASYNC_SCSI_CMD_COMPLETE 0x8020 149#define QLA_ASYNC_CTIO_COMPLETE 0x8021 150#define QLA_ASYNC_POINT_TO_POINT 0x8030 151#define QLA_ASYNC_ZIO_RESP_UPDATE 0x8040 152#define QLA_ASYNC_RND_ERROR 0x8048 153#define QLA_ASYNC_QUEUE_FULL 0x8049 154 155 156/* QLA_MBOX_BASE (reg 0) write */ 157#define QLA_MBOX_NOP 0x0000 158#define QLA_MBOX_LOAD_RAM 0x0001 159#define QLA_MBOX_EXEC_FIRMWARE 0x0002 160#define QLA_MBOX_WRITE_RAM_WORD 0x0004 161#define QLA_MBOX_REGISTER_TEST 0x0006 162#define QLA_MBOX_VERIFY_CSUM 0x0007 163#define QLA_MBOX_ABOUT_FIRMWARE 0x0008 164#define QLA_MBOX_LOAD_RAM_EXT 0x000B 165#define QLA_MBOX_CSUM_FIRMWARE 0x000E 166#define QLA_MBOX_INIT_REQ_QUEUE 0x0010 167#define QLA_MBOX_INIT_RSP_QUEUE 0x0011 168#define QLA_MBOX_STOP_FIRMWARE 0x0014 169#define QLA_MBOX_ABORT_IOCB 0x0015 170#define QLA_MBOX_ABORT_DEVICE 0x0016 171#define QLA_MBOX_ABORT_TARGET 0x0017 172#define QLA_MBOX_RESET 0x0018 173#define QLA_MBOX_ABORT_QUEUE 0x001C 174#define QLA_MBOX_GET_QUEUE_STATUS 0x001D 175#define QLA_MBOX_GET_FIRMWARE_STATUS 0x001F 176#define QLA_MBOX_GET_LOOP_ID 0x0020 177#define QLA_MBOX_SET_FIRMWARE_OPTIONS 0x0038 178#define QLA_MBOX_ENH_GET_PORT_DB 0x0047 179#define QLA_MBOX_PLOGO 0x0056 180#define QLA_MBOX_INIT_FIRMWARE 0x0060 181#define QLA_MBOX_GET_INIT_CB 0x0061 182#define QLA_MBOX_LIP 0x0062 183#define QLA_MBOX_GET_FC_AL_POS 0x0063 184#define QLA_MBOX_GET_PORT_DB 0x0064 185#define QLA_MBOX_TARGET_RESET 0x0066 186#define QLA_MBOX_GET_FIRMWARE_STATE 0x0069 187#define QLA_MBOX_GET_PORT_NAME 0x006A 188#define QLA_MBOX_GET_LINK_STATUS 0x006B 189#define QLA_MBOX_LIP_RESET 0x006C 190#define QLA_MBOX_SEND_SNS 0x006E 191#define QLA_MBOX_FABRIC_PLOGI 0x006F 192#define QLA_MBOX_SEND_CHANGE_REQ 0x0070 193#define QLA_MBOX_FABRIC_PLOGO 0x0071 194#define QLA_MBOX_LOOP_PLOGI 0x0074 195#define QLA_MBOX_GET_PORT_NAME_LIST 0x0075 196#define QLA_MBOX_LUN_RESET 0x007E 197 198/* mailbox operation register bitfields */ 199#define QLA_MBOX_ABOUT_FIRMWARE_IN 0x0001 200#define QLA_MBOX_ABOUT_FIRMWARE_OUT 0x004f 201#define QLA_MBOX_INIT_FIRMWARE_IN 0x00fd 202#define QLA_MBOX_SET_FIRMWARE_OPTIONS_IN 0x000f 203#define QLA_MBOX_GET_LOOP_ID_OUT 0x00cf 204 205#define QLA_MBOX_COUNT 32 206 207/* nvram layout */ 208struct qla_nvram { 209 u_int8_t id[4]; 210 u_int8_t nvram_version; 211 u_int8_t reserved_0; 212 213 u_int8_t parameter_block_version; 214 u_int8_t reserved_1; 215 216 u_int16_t fw_options; 217 218 u_int16_t frame_payload_size; 219 u_int16_t max_iocb_allocation; 220 u_int16_t execution_throttle; 221 u_int8_t retry_count; 222 u_int8_t retry_delay; 223 u_int64_t port_name; 224 u_int16_t hard_address; 225 u_int8_t inquiry_data; 226 u_int8_t login_timeout; 227 u_int64_t node_name; 228 229 u_int16_t add_fw_options; 230 231 u_int8_t response_accumulation_timer; 232 u_int8_t interrupt_delay_timer; 233 234 u_int16_t special_options; 235 236 u_int8_t reserved_2[22]; 237 238 u_int8_t seriallink_options[4]; 239 240 u_int8_t host_p[2]; 241 242 u_int64_t boot_node_name; 243 u_int8_t boot_lun_number; 244 u_int8_t reset_delay; 245 u_int8_t port_down_retry_count; 246 u_int8_t boot_id_number; 247 u_int16_t max_luns_per_target; 248 u_int64_t fcode_boot_port_name; 249 u_int64_t alternate_port_name; 250 u_int64_t alternate_node_name; 251 252 u_int8_t efi_parameters; 253 254 u_int8_t link_down_timeout; 255 256 u_int8_t adapter_id[16]; 257 258 u_int64_t alt1_boot_node_name; 259 u_int16_t alt1_boot_lun_number; 260 u_int64_t alt2_boot_node_name; 261 u_int16_t alt2_boot_lun_number; 262 u_int64_t alt3_boot_node_name; 263 u_int16_t alt3_boot_lun_number; 264 u_int64_t alt4_boot_node_name; 265 u_int16_t alt4_boot_lun_number; 266 u_int64_t alt5_boot_node_name; 267 u_int16_t alt5_boot_lun_number; 268 u_int64_t alt6_boot_node_name; 269 u_int16_t alt6_boot_lun_number; 270 u_int64_t alt7_boot_node_name; 271 u_int16_t alt7_boot_lun_number; 272 273 u_int8_t reserved_3[2]; 274 275 u_int8_t model_number[16]; 276 277 u_int8_t oem_specific[16]; 278 279 u_int8_t adapter_features[2]; 280 281 u_int8_t reserved_4[16]; 282 283 u_int16_t subsystem_vendor_id_2200; 284 u_int16_t subsystem_device_id_2200; 285 286 u_int8_t reserved_5; 287 u_int8_t checksum; 288} __packed; 289 290/* init firmware control block */ 291#define QLA_ICB_VERSION 1 292 293#define QLA_ICB_FW_HARD_ADDR 0x0001 294#define QLA_ICB_FW_FAIRNESS 0x0002 295#define QLA_ICB_FW_FULL_DUPLEX 0x0004 296#define QLA_ICB_FW_FAST_POST 0x0008 297#define QLA_ICB_FW_TARGET_MODE 0x0010 298#define QLA_ICB_FW_DISABLE_INITIATOR 0x0020 299#define QLA_ICB_FW_ENABLE_ADISC 0x0040 300#define QLA_ICB_FW_ENABLE_TGT_DEV 0x0080 301#define QLA_ICB_FW_ENABLE_PDB_CHANGED 0x0100 302#define QLA_ICB_FW_DISABLE_INIT_LIP 0x0200 303#define QLA_ICB_FW_DESC_LOOP_ID 0x0400 304#define QLA_ICB_FW_PREV_LOOP_ID 0x0800 305#define QLA_ICB_FW_RESERVED 0x1000 306#define QLA_ICB_FW_LOGIN_AFTER_LIP 0x2000 307#define QLA_ICB_FW_NAME_OPTION 0x4000 308#define QLA_ICB_FW_EXTENDED_INIT_CB 0x8000 309 310#define QLA_ICB_XFW_ZIO_DISABLED 0x0000 311#define QLA_ICB_XFW_ZIO_MODE_5 0x0005 312#define QLA_ICB_XFW_ZIO_MODE_6 0x0006 313 314#define QLA_ICB_XFW_LOOP_PTP 0x0020 315#define QLA_ICB_XFW_PTP_ONLY 0x0010 316#define QLA_ICB_XFW_LOOP_ONLY 0x0000 317 318#define QLA_ICB_XFW_HARD_ADDR_ONLY 0x0080 319#define QLA_ICB_XFW_ENABLE_CLASS_2 0x0100 320#define QLA_ICB_XFW_ENABLE_ACK0 0x0200 321#define QLA_ICB_XFW_ENABLE_FC_TAPE 0x1000 322#define QLA_ICB_XFW_ENABLE_FC_CONFIRM 0x2000 323#define QLA_ICB_XFW_ENABLE_TGT_QUEUE 0x4000 324#define QLA_ICB_XFW_NO_IMPLICIT_LOGOUT 0x8000 325 326#define QLA_ICB_ZFW_ENABLE_XFR_RDY 0x0001 327#define QLA_ICB_ZFW_SOFT_ID_ONLY 0x0002 328#define QLA_ICB_ZFW_FCP_RSP_12_0 0x0010 329#define QLA_ICB_ZFW_FCP_RSP_24_0 0x0020 330#define QLA_ICB_ZFW_FCP_RSP_32_BYTES 0x0030 331#define QLA_ICB_ZFW_ENABLE_OOO 0x0040 332#define QLA_ICB_ZFW_NO_AUTO_PLOGI 0x0080 333#define QLA_ICB_ZFW_50_OHMS 0x2000 334#define QLA_ICB_ZFW_1GBPS 0x0000 335#define QLA_ICB_ZFW_2GBPS 0x4000 336#define QLA_ICB_ZFW_AUTONEG 0x8000 337 338 339struct qla_init_cb { 340 u_int8_t icb_version; 341 u_int8_t icb_reserved; 342 u_int16_t icb_fw_options; 343 u_int16_t icb_max_frame_len; 344 u_int16_t icb_max_alloc; 345 u_int16_t icb_exec_throttle; 346 u_int8_t icb_retry_count; 347 u_int8_t icb_retry_delay; 348 u_int64_t icb_portname; 349 u_int16_t icb_hardaddr; 350 u_int8_t icb_inquiry_data; 351 u_int8_t icb_login_timeout; 352 u_int64_t icb_nodename; 353 u_int16_t icb_req_out; 354 u_int16_t icb_resp_in; 355 u_int16_t icb_req_queue_len; 356 u_int16_t icb_resp_queue_len; 357 u_int64_t icb_req_queue_addr; 358 u_int64_t icb_resp_queue_addr; 359 u_int16_t icb_lun_enables; 360 u_int8_t icb_cmd_count; 361 u_int8_t icb_notify_count; 362 u_int16_t icb_lun_timeout; 363 u_int16_t icb_reserved2; 364 u_int16_t icb_xfwoptions; 365 u_int8_t icb_reserved3; 366 u_int8_t icb_int_delaytimer; 367 u_int16_t icb_zfwoptions; 368 u_int16_t icb_reserved4[13]; 369} __packed; 370 371#define QLA_FW_OPTION1_ASYNC_LIP_F8 0x0001 372#define QLA_FW_OPTION1_ASYNC_LIP_RESET 0x0002 373#define QLA_FW_OPTION1_SYNC_LOSS_LIP 0x0010 374#define QLA_FW_OPTION1_ASYNC_LIP_ERROR 0x0080 375#define QLA_FW_OPTION1_ASYNC_LOGIN_RJT 0x0800 376 377#define QLA_FW_OPTION3_EMERG_IOCB 0x0001 378#define QLA_FW_OPTION3_ASYNC_RND_ERROR 0x0002 379 380/* topology types returned from QLA_MBOX_GET_LOOP_ID */ 381#define QLA_TOPO_NL_PORT 0 382#define QLA_TOPO_FL_PORT 1 383#define QLA_TOPO_N_PORT 2 384#define QLA_TOPO_F_PORT 3 385#define QLA_TOPO_N_PORT_NO_TARGET 4 386 387 388struct qla_get_port_db { 389 u_int8_t options; 390 u_int8_t control; 391 u_int8_t master_state; 392 u_int8_t slave_state; 393 u_int32_t adisc_hard_addr; 394 u_int16_t port_id[2]; 395 u_int64_t node_name; 396 u_int64_t port_name; 397 u_int16_t exec_throttle; 398 u_int16_t exec_count; 399 u_int8_t retry_count; 400 u_int8_t reserved; 401 u_int16_t resource_alloc; 402 u_int16_t current_alloc; 403 u_int16_t queue_head; 404 u_int16_t queue_tail; 405 u_int16_t xmit_exec_list_next; 406 u_int16_t xmit_exec_list_prev; 407 u_int16_t common_features; 408 u_int16_t total_concurrent_seq; 409 u_int16_t rel_offset; 410 u_int16_t recip_control_flags; 411 u_int16_t recv_data_size; 412 u_int16_t concurrent_seq; 413 u_int16_t open_seq; 414 u_int8_t reserved2[8]; 415 u_int16_t retry_timer; 416 u_int16_t next_seq_id; 417 u_int16_t frame_count; 418 u_int16_t prli_payload_len; 419 u_int16_t prli_svc_word0; 420 u_int16_t prli_svc_word3; 421 u_int16_t loop_id; 422 u_int16_t ext_lun_list_ptr; 423 u_int16_t ext_lun_stop_ptr; 424} __packed; 425 426struct qla_port_name_list { 427 u_int64_t port_name; 428 u_int16_t loop_id; 429} __packed; 430 431#define QLA_SVC3_TARGET_ROLE 0x0010 432 433/* fabric name server commands */ 434#define QLA_SNS_GA_NXT 0x0100 435#define QLA_SNS_GID_FT 0x0171 436#define QLA_SNS_RFT_ID 0x0217 437 438#define QLA_FC4_SCSI 8 439 440#define QLA_LS_REJECT 0x8001 441#define QLA_LS_ACCEPT 0x8002 442 443struct qla_sns_req_hdr { 444 u_int16_t resp_len; 445 u_int16_t reserved; 446 u_int64_t resp_addr; 447 u_int16_t subcmd_len; 448 u_int16_t reserved2; 449} __packed; 450 451struct qla_sns_ga_nxt { 452 struct qla_sns_req_hdr header; 453 u_int16_t subcmd; 454 u_int16_t max_word; 455 u_int32_t reserved3; 456 u_int32_t port_id; 457} __packed; 458 459struct qla_sns_ga_nxt_resp { 460 struct qla_sns_req_hdr header; 461 u_int32_t port_type_id; 462 u_int64_t port_name; 463 u_int8_t sym_port_name_len; 464 u_int8_t sym_port_name[255]; 465 u_int64_t node_name; 466 u_int8_t sym_node_name_len; 467 u_int8_t sym_node_name[255]; 468 u_int64_t initial_assoc; 469 u_int8_t ip_addr[16]; 470 u_int32_t cos; 471 u_int32_t fc4_types[8]; 472} __packed; 473 474struct qla_sns_rft_id { 475 struct qla_sns_req_hdr header; 476 u_int16_t subcmd; 477 u_int16_t max_word; 478 u_int32_t reserved3; 479 u_int32_t port_id; 480 u_int32_t fc4_types[8]; 481} __packed; 482 483struct qla_sns_gid_ft { 484 struct qla_sns_req_hdr header; 485 u_int16_t subcmd; 486 u_int16_t max_word; 487 u_int32_t reserved3; 488 u_int32_t fc4_proto; 489} __packed; 490 491/* available handle ranges */ 492#define QLA_2KL_MIN_HANDLE 0x81 493#define QLA_2KL_MAX_HANDLE 0x7EF 494#define QLA_2KL_BUSWIDTH 0x800 495 496#define QLA_MIN_HANDLE 0x81 497#define QLA_MAX_HANDLE 0xFE 498#define QLA_BUSWIDTH 0x100 499 500#define QLA_F_PORT_HANDLE 0x7E 501#define QLA_FABRIC_CTRL_HANDLE 0x7F 502#define QLA_SNS_HANDLE 0x80 503/* where does this go with 2klogin firmware? */ 504#define QLA_IP_BCAST_HANDLE 0xFF 505 506 507/* IOCB types */ 508/*#define QLA_IOCB_CONT_TYPE_1 0x02 */ 509#define QLA_IOCB_STATUS 0x03 510#define QLA_IOCB_MARKER 0x04 511#define QLA_IOCB_STATUS_CONT 0x10 512#define QLA_IOCB_CMD_TYPE_4 0x15 513#define QLA_IOCB_CMD_TYPE_3 0x19 514#define QLA_IOCB_MAILBOX 0x39 515 516#define QLA_REQ_FLAG_CONT 0x01 517#define QLA_REQ_FLAG_FULL 0x02 518#define QLA_REQ_FLAG_BAD_HDR 0x04 519#define QLA_REQ_FLAG_BAD_PKT 0x08 520 521#define QLA_RESP_FLAG_INVALID_COUNT 0x10 522#define QLA_RESP_FLAG_INVALID_ORDER 0x20 523#define QLA_RESP_FLAG_DMA_ERR 0x40 524#define QLA_RESP_FLAG_RESERVED 0x80 525 526#define QLA_IOCB_CMD_HEAD_OF_QUEUE 0x0002 527#define QLA_IOCB_CMD_ORDERED_QUEUE 0x0004 528#define QLA_IOCB_CMD_SIMPLE_QUEUE 0x0008 529#define QLA_IOCB_CMD_NO_DATA 0x0000 530#define QLA_IOCB_CMD_READ_DATA 0x0020 531#define QLA_IOCB_CMD_WRITE_DATA 0x0040 532#define QLA_IOCB_CMD_NO_FAST_POST 0x0080 533 534#define QLA_IOCB_SEGS_PER_CMD 2 535#define QLA_IOCB_SEGS_PER_CMD_CONT 5 536 537#define QLA_IOCB_MARKER_SYNC_ALL 2 538 539struct qla_iocb_seg { 540 u_int64_t seg_addr; 541 u_int32_t seg_len; 542} __packed; 543 544#if 0 545struct qla_iocb_cont1 { 546 u_int8_t entry_type; /* QLA_IOCB_CONT_TYPE_1 */ 547 u_int8_t entry_count; 548 u_int8_t seqno; 549 u_int8_t flags; 550 551 struct qla_iocb_seg segs[5]; 552} __packed; 553#endif 554 555struct qla_iocb_status { 556 u_int8_t entry_type; /* QLA_IOCB_STATUS */ 557 u_int8_t entry_count; 558 u_int8_t seqno; 559 u_int8_t flags; 560 561 u_int32_t handle; 562 u_int16_t scsi_status; 563 u_int16_t completion; 564 u_int16_t state_flags; 565 u_int16_t status_flags; 566 u_int16_t rsp_len; 567 u_int16_t sense_len; 568 u_int32_t resid; 569 u_int8_t fcp_rsp[8]; 570 u_int8_t sense_data[32]; 571} __packed; 572 573/* completion */ 574#define QLA_IOCB_STATUS_COMPLETE 0x0000 575#define QLA_IOCB_STATUS_DMA_ERROR 0x0002 576#define QLA_IOCB_STATUS_RESET 0x0004 577#define QLA_IOCB_STATUS_ABORTED 0x0005 578#define QLA_IOCB_STATUS_TIMEOUT 0x0006 579#define QLA_IOCB_STATUS_DATA_OVERRUN 0x0007 580#define QLA_IOCB_STATUS_DATA_UNDERRUN 0x0015 581#define QLA_IOCB_STATUS_QUEUE_FULL 0x001C 582#define QLA_IOCB_STATUS_PORT_UNAVAIL 0x0028 583#define QLA_IOCB_STATUS_PORT_LOGGED_OUT 0x0029 584#define QLA_IOCB_STATUS_PORT_CHANGED 0x002A 585#define QLA_IOCB_STATUS_PORT_BUSY 0x002B 586 587#define QLA_SCSI_STATUS_FCP_LEN_VALID 0x0100 588#define QLA_SCSI_STATUS_SENSE_VALID 0x0200 589#define QLA_SCSI_STATUS_RESID_OVER 0x0400 590#define QLA_SCSI_STATUS_RESID_UNDER 0x0800 591 592 593struct qla_iocb_marker { 594 u_int8_t entry_type; /* QLA_IOCB_MARKER */ 595 u_int8_t entry_count; 596 u_int8_t seqno; 597 u_int8_t flags; 598 599 u_int32_t handle; 600 u_int8_t reserved; 601 u_int8_t target; 602 u_int8_t modifier; 603 u_int8_t vp_index; 604 u_int16_t marker_flags; 605 u_int16_t lun; 606 u_int8_t reserved2[48]; 607} __packed; 608 609struct qla_iocb_status_cont { 610 u_int8_t entry_type; /* QLA_IOCB_STATUS_CONT */ 611 u_int8_t entry_count; 612 u_int8_t seqno; 613 u_int8_t flags; 614 615 u_int8_t sense[44]; 616} __packed; 617 618struct qla_iocb_req34 { 619 u_int8_t entry_type; /* QLA_IOCB_CMD_TYPE_3 or 4 */ 620 u_int8_t entry_count; 621 u_int8_t seqno; 622 u_int8_t flags; 623 624 u_int32_t req_handle; 625 u_int16_t req_target; 626 u_int16_t req_scclun; 627 u_int16_t req_flags; 628 u_int16_t req_reserved; 629 u_int16_t req_time; 630 u_int16_t req_seg_count; 631 u_int8_t req_cdb[16]; 632 u_int32_t req_totalcnt; 633 union { 634 struct qla_iocb_seg req3_segs[2]; 635 struct { 636 u_int16_t req4_seg_type; 637 u_int32_t req4_seg_base; 638 u_int64_t req4_seg_addr; 639 u_int8_t req4_reserved[10]; 640 } __packed req4; 641 } req_type; 642} __packed; 643 644