mtd8xx.c revision 1.19
1/* $OpenBSD: mtd8xx.c,v 1.19 2012/11/29 21:10:32 brad Exp $ */ 2 3/* 4 * Copyright (c) 2003 Oleg Safiullin <form@pdp11.org.ru> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31#include "bpfilter.h" 32 33#include <sys/param.h> 34#include <sys/mbuf.h> 35#include <sys/systm.h> 36#include <sys/device.h> 37#include <sys/socket.h> 38#include <sys/ioctl.h> 39 40#include <net/if.h> 41#include <net/if_media.h> 42 43#if NBPFILTER > 0 44#include <net/bpf.h> 45#endif 46 47#ifdef INET 48#include <netinet/in.h> 49#include <netinet/if_ether.h> 50#endif 51 52#include <machine/bus.h> 53 54#include <dev/mii/mii.h> 55#include <dev/mii/miivar.h> 56 57#include <dev/pci/pcidevs.h> 58#include <dev/pci/pcivar.h> 59 60#include <dev/ic/mtd8xxreg.h> 61#include <dev/ic/mtd8xxvar.h> 62 63 64static int mtd_ifmedia_upd(struct ifnet *); 65static void mtd_ifmedia_sts(struct ifnet *, struct ifmediareq *); 66 67static u_int32_t mtd_mii_command(struct mtd_softc *, int, int, int); 68static int mtd_miibus_readreg(struct device *, int, int); 69static void mtd_miibus_writereg(struct device *, int, int, int); 70static void mtd_miibus_statchg(struct device *); 71static void mtd_setmulti(struct mtd_softc *); 72 73static int mtd_encap(struct mtd_softc *, struct mbuf *, u_int32_t *); 74static int mtd_list_rx_init(struct mtd_softc *); 75static void mtd_list_tx_init(struct mtd_softc *); 76static int mtd_newbuf(struct mtd_softc *, int, struct mbuf *); 77 78static void mtd_reset(struct mtd_softc *sc); 79static int mtd_ioctl(struct ifnet *, u_long, caddr_t); 80static void mtd_init(struct ifnet *); 81static void mtd_start(struct ifnet *); 82static void mtd_stop(struct ifnet *); 83static void mtd_watchdog(struct ifnet *); 84 85static void mtd_rxeof(struct mtd_softc *); 86static int mtd_rx_resync(struct mtd_softc *); 87static void mtd_txeof(struct mtd_softc *); 88 89 90void 91mtd_attach(struct mtd_softc *sc) 92{ 93 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 94 u_int32_t enaddr[2]; 95 int i; 96 97 /* Reset the adapter. */ 98 mtd_reset(sc); 99 100 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mtd_list_data), 101 PAGE_SIZE, 0, sc->sc_listseg, 1, &sc->sc_listnseg, 102 BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0) { 103 printf(": can't alloc list mem\n"); 104 return; 105 } 106 if (bus_dmamem_map(sc->sc_dmat, sc->sc_listseg, sc->sc_listnseg, 107 sizeof(struct mtd_list_data), &sc->sc_listkva, 108 BUS_DMA_NOWAIT) != 0) { 109 printf(": can't map list mem\n"); 110 return; 111 } 112 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mtd_list_data), 1, 113 sizeof(struct mtd_list_data), 0, BUS_DMA_NOWAIT, 114 &sc->sc_listmap) != 0) { 115 printf(": can't alloc list map\n"); 116 return; 117 } 118 if (bus_dmamap_load(sc->sc_dmat, sc->sc_listmap, sc->sc_listkva, 119 sizeof(struct mtd_list_data), NULL, BUS_DMA_NOWAIT) != 0) { 120 printf(": can't load list map\n"); 121 return; 122 } 123 sc->mtd_ldata = (struct mtd_list_data *)sc->sc_listkva; 124 125 for (i = 0; i < MTD_RX_LIST_CNT; i++) { 126 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 127 0, BUS_DMA_NOWAIT, 128 &sc->mtd_cdata.mtd_rx_chain[i].sd_map) != 0) { 129 printf(": can't create rx map\n"); 130 return; 131 } 132 } 133 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 134 BUS_DMA_NOWAIT, &sc->sc_rx_sparemap) != 0) { 135 printf(": can't create rx spare map\n"); 136 return; 137 } 138 139 for (i = 0; i < MTD_TX_LIST_CNT; i++) { 140 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 141 MTD_TX_LIST_CNT - 5, MCLBYTES, 0, BUS_DMA_NOWAIT, 142 &sc->mtd_cdata.mtd_tx_chain[i].sd_map) != 0) { 143 printf(": can't create tx map\n"); 144 return; 145 } 146 } 147 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, MTD_TX_LIST_CNT - 5, 148 MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_tx_sparemap) != 0) { 149 printf(": can't create tx spare map\n"); 150 return; 151 } 152 153 154 /* Get station address. */ 155 enaddr[0] = letoh32(CSR_READ_4(MTD_PAR0)); 156 enaddr[1] = letoh32(CSR_READ_4(MTD_PAR4)); 157 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 158 printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 159 160 /* Initialize interface */ 161 ifp->if_softc = sc; 162 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 163 ifp->if_ioctl = mtd_ioctl; 164 ifp->if_start = mtd_start; 165 ifp->if_watchdog = mtd_watchdog; 166 IFQ_SET_READY(&ifp->if_snd); 167 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 168 169 ifp->if_capabilities = IFCAP_VLAN_MTU; 170 171 /* 172 * Initialize our media structures and probe the MII. 173 */ 174 sc->sc_mii.mii_ifp = ifp; 175 sc->sc_mii.mii_readreg = mtd_miibus_readreg; 176 sc->sc_mii.mii_writereg = mtd_miibus_writereg; 177 sc->sc_mii.mii_statchg = mtd_miibus_statchg; 178 ifmedia_init(&sc->sc_mii.mii_media, 0, mtd_ifmedia_upd, 179 mtd_ifmedia_sts); 180 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 181 MII_OFFSET_ANY, 0); 182 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 183 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE, 0, 184 NULL); 185 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE); 186 } else 187 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 188 189 /* 190 * Attach us everywhere 191 */ 192 if_attach(ifp); 193 ether_ifattach(ifp); 194} 195 196 197static int 198mtd_ifmedia_upd(struct ifnet *ifp) 199{ 200 struct mtd_softc *sc = ifp->if_softc; 201 202 return (mii_mediachg(&sc->sc_mii)); 203} 204 205 206static void 207mtd_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 208{ 209 struct mtd_softc *sc = ifp->if_softc; 210 211 mii_pollstat(&sc->sc_mii); 212 ifmr->ifm_active = sc->sc_mii.mii_media_active; 213 ifmr->ifm_status = sc->sc_mii.mii_media_status; 214} 215 216 217static u_int32_t 218mtd_mii_command(struct mtd_softc *sc, int opcode, int phy, int reg) 219{ 220 u_int32_t miir, mask, data; 221 int i; 222 223 miir = (CSR_READ_4(MTD_MIIMGT) & ~MIIMGT_MASK) | MIIMGT_WRITE | 224 MIIMGT_MDO; 225 226 for (i = 0; i < 32; i++) { 227 miir &= ~MIIMGT_MDC; 228 CSR_WRITE_4(MTD_MIIMGT, miir); 229 miir |= MIIMGT_MDC; 230 CSR_WRITE_4(MTD_MIIMGT, miir); 231 } 232 233 data = opcode | (phy << 7) | (reg << 2); 234 235 for (mask = 0; mask; mask >>= 1) { 236 miir &= ~(MIIMGT_MDC | MIIMGT_MDO); 237 if (mask & data) 238 miir |= MIIMGT_MDO; 239 CSR_WRITE_4(MTD_MIIMGT, miir); 240 miir |= MIIMGT_MDC; 241 CSR_WRITE_4(MTD_MIIMGT, miir); 242 DELAY(30); 243 244 if (mask == 0x4 && opcode == MII_OPCODE_RD) 245 miir &= ~MIIMGT_WRITE; 246 } 247 return (miir); 248} 249 250 251 252static int 253mtd_miibus_readreg(struct device *self, int phy, int reg) 254{ 255 struct mtd_softc *sc = (void *)self; 256 257 if (sc->sc_devid == PCI_PRODUCT_MYSON_MTD803) 258 return (phy ? 0 : (int)CSR_READ_2(MTD_PHYCSR + (reg << 1))); 259 else { 260 u_int32_t miir, mask, data; 261 262 miir = mtd_mii_command(sc, MII_OPCODE_RD, phy, reg); 263 for (mask = 0x8000, data = 0; mask; mask >>= 1) { 264 miir &= ~MIIMGT_MDC; 265 CSR_WRITE_4(MTD_MIIMGT, miir); 266 miir = CSR_READ_4(MTD_MIIMGT); 267 if (miir & MIIMGT_MDI) 268 data |= mask; 269 miir |= MIIMGT_MDC; 270 CSR_WRITE_4(MTD_MIIMGT, miir); 271 DELAY(30); 272 } 273 miir &= ~MIIMGT_MDC; 274 CSR_WRITE_4(MTD_MIIMGT, miir); 275 276 return ((int)data); 277 } 278} 279 280 281static void 282mtd_miibus_writereg(struct device *self, int phy, int reg, int val) 283{ 284 struct mtd_softc *sc = (void *)self; 285 286 if (sc->sc_devid == PCI_PRODUCT_MYSON_MTD803) { 287 if (!phy) 288 CSR_WRITE_2(MTD_PHYCSR + (reg << 1), val); 289 } else { 290 u_int32_t miir, mask; 291 292 miir = mtd_mii_command(sc, MII_OPCODE_WR, phy, reg); 293 for (mask = 0x8000; mask; mask >>= 1) { 294 miir &= ~(MIIMGT_MDC | MIIMGT_MDO); 295 if (mask & (u_int32_t)val) 296 miir |= MIIMGT_MDO; 297 CSR_WRITE_4(MTD_MIIMGT, miir); 298 miir |= MIIMGT_MDC; 299 CSR_WRITE_4(MTD_MIIMGT, miir); 300 DELAY(1); 301 } 302 miir &= ~MIIMGT_MDC; 303 CSR_WRITE_4(MTD_MIIMGT, miir); 304 } 305} 306 307 308static void 309mtd_miibus_statchg(struct device *self) 310{ 311 /* NOTHING */ 312} 313 314 315void 316mtd_setmulti(struct mtd_softc *sc) 317{ 318 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 319 u_int32_t rxfilt, crc, hash[2] = { 0, 0 }; 320 struct ether_multistep step; 321 struct ether_multi *enm; 322 int mcnt = 0; 323 324allmulti: 325 rxfilt = CSR_READ_4(MTD_TCRRCR) & ~RCR_AM; 326 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 327 rxfilt |= RCR_AM; 328 CSR_WRITE_4(MTD_TCRRCR, rxfilt); 329 CSR_WRITE_4(MTD_MAR0, 0xffffffff); 330 CSR_WRITE_4(MTD_MAR4, 0xffffffff); 331 return; 332 } 333 334 /* First, zot all the existing hash bits. */ 335 CSR_WRITE_4(MTD_MAR0, 0); 336 CSR_WRITE_4(MTD_MAR4, 0); 337 338 /* Now program new ones. */ 339 ETHER_FIRST_MULTI(step, &sc->sc_arpcom, enm); 340 while (enm != NULL) { 341 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 342 ifp->if_flags |= IFF_ALLMULTI; 343 goto allmulti; 344 } 345 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 346 hash[crc >> 5] |= 1 << (crc & 0xf); 347 ++mcnt; 348 ETHER_NEXT_MULTI(step, enm); 349 } 350 351 if (mcnt) 352 rxfilt |= RCR_AM; 353 CSR_WRITE_4(MTD_MAR0, hash[0]); 354 CSR_WRITE_4(MTD_MAR4, hash[1]); 355 CSR_WRITE_4(MTD_TCRRCR, rxfilt); 356} 357 358 359/* 360 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 361 * pointers to the fragment pointers. 362 */ 363int 364mtd_encap(struct mtd_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 365{ 366 struct mtd_tx_desc *f = NULL; 367 int frag, cur, cnt = 0, i, total_len = 0; 368 bus_dmamap_t map; 369 370 /* 371 * Start packing the mbufs in this chain into 372 * the fragment pointers. Stop when we run out 373 * of fragments or hit the end of the mbuf chain. 374 */ 375 map = sc->sc_tx_sparemap; 376 377 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, 378 m_head, BUS_DMA_NOWAIT) != 0) 379 return (1); 380 381 cur = frag = *txidx; 382 383 for (i = 0; i < map->dm_nsegs; i++) { 384 if ((MTD_TX_LIST_CNT - 385 (sc->mtd_cdata.mtd_tx_cnt + cnt)) < 5) { 386 bus_dmamap_unload(sc->sc_dmat, map); 387 return (1); 388 } 389 390 f = &sc->mtd_ldata->mtd_tx_list[frag]; 391 f->td_tcw = htole32(map->dm_segs[i].ds_len); 392 total_len += map->dm_segs[i].ds_len; 393 if (cnt == 0) { 394 f->td_tsw = 0; 395 f->td_tcw |= htole32(TCW_FD | TCW_CRC | TCW_PAD); 396 } else 397 f->td_tsw = htole32(TSW_OWN); 398 f->td_buf = htole32(map->dm_segs[i].ds_addr); 399 cur = frag; 400 frag = (frag + 1) % MTD_TX_LIST_CNT; 401 cnt++; 402 } 403 404 sc->mtd_cdata.mtd_tx_cnt += cnt; 405 sc->mtd_cdata.mtd_tx_chain[cur].sd_mbuf = m_head; 406 sc->sc_tx_sparemap = sc->mtd_cdata.mtd_tx_chain[cur].sd_map; 407 sc->mtd_cdata.mtd_tx_chain[cur].sd_map = map; 408 sc->mtd_ldata->mtd_tx_list[cur].td_tcw |= htole32(TCW_LD | TCW_IC); 409 if (sc->sc_devid == PCI_PRODUCT_MYSON_MTD891) 410 sc->mtd_ldata->mtd_tx_list[cur].td_tcw |= 411 htole32(TCW_EIC | TCW_RTLC); 412 413 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 414 BUS_DMASYNC_PREWRITE); 415 416 sc->mtd_ldata->mtd_tx_list[*txidx].td_tsw = htole32(TSW_OWN); 417 sc->mtd_ldata->mtd_tx_list[*txidx].td_tcw |= 418 htole32(total_len << TCW_PKTS_SHIFT); 419 420 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 421 offsetof(struct mtd_list_data, mtd_tx_list[0]), 422 sizeof(struct mtd_tx_desc) * MTD_TX_LIST_CNT, 423 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 424 425 *txidx = frag; 426 427 return (0); 428} 429 430 431/* 432 * Initialize the transmit descriptors. 433 */ 434static void 435mtd_list_tx_init(struct mtd_softc *sc) 436{ 437 struct mtd_chain_data *cd; 438 struct mtd_list_data *ld; 439 int i; 440 441 cd = &sc->mtd_cdata; 442 ld = sc->mtd_ldata; 443 for (i = 0; i < MTD_TX_LIST_CNT; i++) { 444 cd->mtd_tx_chain[i].sd_mbuf = NULL; 445 ld->mtd_tx_list[i].td_tsw = 0; 446 ld->mtd_tx_list[i].td_tcw = 0; 447 ld->mtd_tx_list[i].td_buf = 0; 448 ld->mtd_tx_list[i].td_next = htole32( 449 sc->sc_listmap->dm_segs[0].ds_addr + 450 offsetof(struct mtd_list_data, 451 mtd_tx_list[(i + 1) % MTD_TX_LIST_CNT])); 452 } 453 454 cd->mtd_tx_prod = cd->mtd_tx_cons = cd->mtd_tx_cnt = 0; 455} 456 457 458/* 459 * Initialize the RX descriptors and allocate mbufs for them. Note that 460 * we arrange the descriptors in a closed ring, so that the last descriptor 461 * points back to the first. 462 */ 463static int 464mtd_list_rx_init(struct mtd_softc *sc) 465{ 466 struct mtd_list_data *ld; 467 int i; 468 469 ld = sc->mtd_ldata; 470 471 for (i = 0; i < MTD_RX_LIST_CNT; i++) { 472 if (mtd_newbuf(sc, i, NULL)) 473 return (1); 474 ld->mtd_rx_list[i].rd_next = htole32( 475 sc->sc_listmap->dm_segs[0].ds_addr + 476 offsetof(struct mtd_list_data, 477 mtd_rx_list[(i + 1) % MTD_RX_LIST_CNT]) 478 ); 479 } 480 481 sc->mtd_cdata.mtd_rx_prod = 0; 482 483 return (0); 484} 485 486 487/* 488 * Initialize an RX descriptor and attach an MBUF cluster. 489 */ 490static int 491mtd_newbuf(struct mtd_softc *sc, int i, struct mbuf *m) 492{ 493 struct mbuf *m_new = NULL; 494 struct mtd_rx_desc *c; 495 bus_dmamap_t map; 496 497 c = &sc->mtd_ldata->mtd_rx_list[i]; 498 499 if (m == NULL) { 500 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 501 if (m_new == NULL) 502 return (1); 503 504 MCLGET(m_new, M_DONTWAIT); 505 if (!(m_new->m_flags & M_EXT)) { 506 m_freem(m_new); 507 return (1); 508 } 509 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 510 if (bus_dmamap_load(sc->sc_dmat, sc->sc_rx_sparemap, 511 mtod(m_new, caddr_t), MCLBYTES, NULL, 512 BUS_DMA_NOWAIT) != 0) { 513 m_freem(m_new); 514 return (1); 515 } 516 map = sc->mtd_cdata.mtd_rx_chain[i].sd_map; 517 sc->mtd_cdata.mtd_rx_chain[i].sd_map = sc->sc_rx_sparemap; 518 sc->sc_rx_sparemap = map; 519 } else { 520 m_new = m; 521 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 522 m_new->m_data = m_new->m_ext.ext_buf; 523 } 524 525 m_adj(m_new, sizeof(u_int64_t)); 526 527 bus_dmamap_sync(sc->sc_dmat, sc->mtd_cdata.mtd_rx_chain[i].sd_map, 0, 528 sc->mtd_cdata.mtd_rx_chain[i].sd_map->dm_mapsize, 529 BUS_DMASYNC_PREREAD); 530 531 sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf = m_new; 532 c->rd_buf = htole32( 533 sc->mtd_cdata.mtd_rx_chain[i].sd_map->dm_segs[0].ds_addr + 534 sizeof(u_int64_t)); 535 c->rd_rcw = htole32(ETHER_MAX_DIX_LEN); 536 c->rd_rsr = htole32(RSR_OWN); 537 538 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 539 offsetof(struct mtd_list_data, mtd_rx_list[i]), 540 sizeof(struct mtd_rx_desc), 541 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 542 543 return (0); 544} 545 546 547static void 548mtd_reset(struct mtd_softc *sc) 549{ 550 int i; 551 552 /* Set software reset bit */ 553 CSR_WRITE_4(MTD_BCR, BCR_SWR); 554 555 /* 556 * Wait until software reset completed. 557 */ 558 for (i = 0; i < MTD_TIMEOUT; ++i) { 559 DELAY(10); 560 if (!(CSR_READ_4(MTD_BCR) & BCR_SWR)) { 561 /* 562 * Wait a little while for the chip to get 563 * its brains in order. 564 */ 565 DELAY(1000); 566 return; 567 } 568 } 569 570 /* Reset timed out. */ 571 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 572} 573 574 575static int 576mtd_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 577{ 578 struct mtd_softc *sc = ifp->if_softc; 579 struct ifaddr *ifa = (struct ifaddr *)data; 580 struct ifreq *ifr = (struct ifreq *)data; 581 int s, error = 0; 582 583 s = splnet(); 584 585 switch (command) { 586 case SIOCSIFADDR: 587 ifp->if_flags |= IFF_UP; 588 mtd_init(ifp); 589 switch (ifa->ifa_addr->sa_family) { 590#ifdef INET 591 case AF_INET: 592 arp_ifinit(&sc->sc_arpcom, ifa); 593 break; 594#endif /* INET */ 595 } 596 break; 597 598 case SIOCSIFFLAGS: 599 if (ifp->if_flags & IFF_UP) 600 mtd_init(ifp); 601 else { 602 if (ifp->if_flags & IFF_RUNNING) 603 mtd_stop(ifp); 604 } 605 error = 0; 606 break; 607 608 case SIOCGIFMEDIA: 609 case SIOCSIFMEDIA: 610 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 611 break; 612 default: 613 error = ether_ioctl(ifp, &sc->sc_arpcom, command, data); 614 } 615 616 if (error == ENETRESET) { 617 if (ifp->if_flags & IFF_RUNNING) 618 mtd_setmulti(sc); 619 error = 0; 620 } 621 622 splx(s); 623 return (error); 624} 625 626 627static void 628mtd_init(struct ifnet *ifp) 629{ 630 struct mtd_softc *sc = ifp->if_softc; 631 int s; 632 633 s = splnet(); 634 635 /* 636 * Cancel pending I/O and free all RX/TX buffers. 637 */ 638 mtd_stop(ifp); 639 640 /* 641 * Set cache alignment and burst length. 642 */ 643 CSR_WRITE_4(MTD_BCR, BCR_PBL8); 644 CSR_WRITE_4(MTD_TCRRCR, TCR_TFTSF | RCR_RBLEN | RCR_RPBL512); 645 if (sc->sc_devid == PCI_PRODUCT_MYSON_MTD891) { 646 CSR_SETBIT(MTD_BCR, BCR_PROG); 647 CSR_SETBIT(MTD_TCRRCR, TCR_ENHANCED); 648 } 649 650 if (ifp->if_flags & IFF_PROMISC) 651 CSR_SETBIT(MTD_TCRRCR, RCR_PROM); 652 else 653 CSR_CLRBIT(MTD_TCRRCR, RCR_PROM); 654 655 if (ifp->if_flags & IFF_BROADCAST) 656 CSR_SETBIT(MTD_TCRRCR, RCR_AB); 657 else 658 CSR_CLRBIT(MTD_TCRRCR, RCR_AB); 659 660 mtd_setmulti(sc); 661 662 if (mtd_list_rx_init(sc)) { 663 printf("%s: can't allocate memeory for rx buffers\n", 664 sc->sc_dev.dv_xname); 665 splx(s); 666 return; 667 } 668 mtd_list_tx_init(sc); 669 670 CSR_WRITE_4(MTD_RXLBA, sc->sc_listmap->dm_segs[0].ds_addr + 671 offsetof(struct mtd_list_data, mtd_rx_list[0])); 672 CSR_WRITE_4(MTD_TXLBA, sc->sc_listmap->dm_segs[0].ds_addr + 673 offsetof(struct mtd_list_data, mtd_tx_list[0])); 674 675 /* 676 * Enable interrupts. 677 */ 678 CSR_WRITE_4(MTD_IMR, IMR_INTRS); 679 CSR_WRITE_4(MTD_ISR, 0xffffffff); 680 681 /* Enable receiver and transmitter */ 682 CSR_SETBIT(MTD_TCRRCR, TCR_TE | RCR_RE); 683 CSR_WRITE_4(MTD_RXPDR, 0xffffffff); 684 685 ifp->if_flags |= IFF_RUNNING; 686 ifp->if_flags &= ~IFF_OACTIVE; 687 splx(s); 688} 689 690 691/* 692 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 693 * to the mbuf data regions directly in the transmit lists. We also save a 694 * copy of the pointers since the transmit list fragment pointers are 695 * physical addresses. 696 */ 697static void 698mtd_start(struct ifnet *ifp) 699{ 700 struct mtd_softc *sc = ifp->if_softc; 701 struct mbuf *m_head = NULL; 702 int idx; 703 704 if (sc->mtd_cdata.mtd_tx_cnt) { 705 ifp->if_flags |= IFF_OACTIVE; 706 return; 707 } 708 709 idx = sc->mtd_cdata.mtd_tx_prod; 710 while (sc->mtd_cdata.mtd_tx_chain[idx].sd_mbuf == NULL) { 711 IFQ_DEQUEUE(&ifp->if_snd, m_head); 712 if (m_head == NULL) 713 break; 714 715 if (mtd_encap(sc, m_head, &idx)) { 716 ifp->if_flags |= IFF_OACTIVE; 717 break; 718 } 719 720 /* 721 * If there's a BPF listener, bounce a copy of this frame 722 * to him. 723 */ 724#if NBPFILTER > 0 725 if (ifp->if_bpf != NULL) 726 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 727#endif 728 } 729 730 if (idx == sc->mtd_cdata.mtd_tx_prod) 731 return; 732 733 /* Transmit */ 734 sc->mtd_cdata.mtd_tx_prod = idx; 735 CSR_WRITE_4(MTD_TXPDR, 0xffffffff); 736 737 /* 738 * Set a timeout in case the chip goes out to lunch. 739 */ 740 ifp->if_timer = 5; 741} 742 743 744static void 745mtd_stop(struct ifnet *ifp) 746{ 747 struct mtd_softc *sc = ifp->if_softc; 748 int i; 749 750 ifp->if_timer = 0; 751 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 752 753 CSR_CLRBIT(MTD_TCRRCR, (RCR_RE | TCR_TE)); 754 CSR_WRITE_4(MTD_IMR, 0); 755 CSR_WRITE_4(MTD_TXLBA, 0); 756 CSR_WRITE_4(MTD_RXLBA, 0); 757 758 /* 759 * Free data in the RX lists. 760 */ 761 for (i = 0; i < MTD_RX_LIST_CNT; i++) { 762 if (sc->mtd_cdata.mtd_rx_chain[i].sd_map->dm_nsegs != 0) { 763 bus_dmamap_t map = sc->mtd_cdata.mtd_rx_chain[i].sd_map; 764 765 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 766 BUS_DMASYNC_POSTREAD); 767 bus_dmamap_unload(sc->sc_dmat, map); 768 } 769 if (sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf != NULL) { 770 m_freem(sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf); 771 sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf = NULL; 772 } 773 } 774 bzero(&sc->mtd_ldata->mtd_rx_list, sizeof(sc->mtd_ldata->mtd_rx_list)); 775 776 /* 777 * Free the TX list buffers. 778 */ 779 for (i = 0; i < MTD_TX_LIST_CNT; i++) { 780 if (sc->mtd_cdata.mtd_tx_chain[i].sd_map->dm_nsegs != 0) { 781 bus_dmamap_t map = sc->mtd_cdata.mtd_tx_chain[i].sd_map; 782 783 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 784 BUS_DMASYNC_POSTWRITE); 785 bus_dmamap_unload(sc->sc_dmat, map); 786 } 787 if (sc->mtd_cdata.mtd_tx_chain[i].sd_mbuf != NULL) { 788 m_freem(sc->mtd_cdata.mtd_tx_chain[i].sd_mbuf); 789 sc->mtd_cdata.mtd_tx_chain[i].sd_mbuf = NULL; 790 } 791 } 792 793 bzero(&sc->mtd_ldata->mtd_tx_list, sizeof(sc->mtd_ldata->mtd_tx_list)); 794 795} 796 797 798static void 799mtd_watchdog(struct ifnet *ifp) 800{ 801 struct mtd_softc *sc = ifp->if_softc; 802 803 ifp->if_oerrors++; 804 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 805 806 mtd_stop(ifp); 807 mtd_reset(sc); 808 mtd_init(ifp); 809 810 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 811 mtd_start(ifp); 812} 813 814 815int 816mtd_intr(void *xsc) 817{ 818 struct mtd_softc *sc = xsc; 819 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 820 u_int32_t status; 821 int claimed = 0; 822 823 /* Suppress unwanted interrupts */ 824 if (!(ifp->if_flags & IFF_RUNNING)) { 825 if (CSR_READ_4(MTD_ISR) & ISR_INTRS) 826 mtd_stop(ifp); 827 return (claimed); 828 } 829 830 /* Disable interrupts. */ 831 CSR_WRITE_4(MTD_IMR, 0); 832 833 while((status = CSR_READ_4(MTD_ISR)) & ISR_INTRS) { 834 claimed = 1; 835 836 CSR_WRITE_4(MTD_ISR, status); 837 838 /* RX interrupt. */ 839 if (status & ISR_RI) { 840 int curpkts = ifp->if_ipackets; 841 842 mtd_rxeof(sc); 843 if (curpkts == ifp->if_ipackets) 844 while(mtd_rx_resync(sc)) 845 mtd_rxeof(sc); 846 } 847 848 /* RX error interrupt. */ 849 if (status & (ISR_RXERI | ISR_RBU)) 850 ifp->if_ierrors++; 851 852 /* TX interrupt. */ 853 if (status & (ISR_TI | ISR_ETI | ISR_TBU)) 854 mtd_txeof(sc); 855 856 /* Fatal bus error interrupt. */ 857 if (status & ISR_FBE) { 858 mtd_reset(sc); 859 mtd_start(ifp); 860 } 861 } 862 863 /* Re-enable interrupts. */ 864 CSR_WRITE_4(MTD_IMR, IMR_INTRS); 865 866 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 867 mtd_start(ifp); 868 869 return (claimed); 870} 871 872 873/* 874 * A frame has been uploaded: pass the resulting mbuf chain up to 875 * the higher level protocols. 876 */ 877static void 878mtd_rxeof(struct mtd_softc *sc) 879{ 880 struct mbuf *m; 881 struct ifnet *ifp; 882 struct mtd_rx_desc *cur_rx; 883 int i, total_len = 0; 884 u_int32_t rxstat; 885 886 ifp = &sc->sc_arpcom.ac_if; 887 i = sc->mtd_cdata.mtd_rx_prod; 888 889 while(!(sc->mtd_ldata->mtd_rx_list[i].rd_rsr & htole32(RSR_OWN))) { 890 struct mbuf *m0 = NULL; 891 892 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 893 offsetof(struct mtd_list_data, mtd_rx_list[i]), 894 sizeof(struct mtd_rx_desc), 895 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 896 897 cur_rx = &sc->mtd_ldata->mtd_rx_list[i]; 898 rxstat = letoh32(cur_rx->rd_rsr); 899 m = sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf; 900 total_len = RSR_FLNG_GET(rxstat); 901 902 sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf = NULL; 903 904 /* 905 * If an error occurs, update stats, clear the 906 * status word and leave the mbuf cluster in place: 907 * it should simply get re-used next time this descriptor 908 * comes up in the ring. 909 */ 910 if (rxstat & RSR_RXER) { 911 ifp->if_ierrors++; 912 mtd_newbuf(sc, i, m); 913 if (rxstat & RSR_CRC) { 914 i = (i + 1) % MTD_RX_LIST_CNT; 915 continue; 916 } else { 917 mtd_init(ifp); 918 return; 919 } 920 } 921 922 /* No errors; receive the packet. */ 923 total_len -= ETHER_CRC_LEN; 924 925 bus_dmamap_sync(sc->sc_dmat, sc->mtd_cdata.mtd_rx_chain[i].sd_map, 926 0, sc->mtd_cdata.mtd_rx_chain[i].sd_map->dm_mapsize, 927 BUS_DMASYNC_POSTREAD); 928 929 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 930 ifp, NULL); 931 mtd_newbuf(sc, i, m); 932 i = (i + 1) % MTD_RX_LIST_CNT; 933 if (m0 == NULL) { 934 ifp->if_ierrors++; 935 continue; 936 } 937 m = m0; 938 939 ifp->if_ipackets++; 940 941#if NBPFILTER > 0 942 if (ifp->if_bpf) 943 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 944#endif 945 ether_input_mbuf(ifp, m); 946 } 947 948 sc->mtd_cdata.mtd_rx_prod = i; 949} 950 951 952/* 953 * This routine searches the RX ring for dirty descriptors in the 954 * event that the rxeof routine falls out of sync with the chip's 955 * current descriptor pointer. This may happen sometimes as a result 956 * of a "no RX buffer available" condition that happens when the chip 957 * consumes all of the RX buffers before the driver has a chance to 958 * process the RX ring. This routine may need to be called more than 959 * once to bring the driver back in sync with the chip, however we 960 * should still be getting RX DONE interrupts to drive the search 961 * for new packets in the RX ring, so we should catch up eventually. 962 */ 963static int 964mtd_rx_resync(sc) 965 struct mtd_softc *sc; 966{ 967 int i, pos; 968 struct mtd_rx_desc *cur_rx; 969 970 pos = sc->mtd_cdata.mtd_rx_prod; 971 972 for (i = 0; i < MTD_RX_LIST_CNT; i++) { 973 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 974 offsetof(struct mtd_list_data, mtd_rx_list[pos]), 975 sizeof(struct mtd_rx_desc), 976 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 977 978 cur_rx = &sc->mtd_ldata->mtd_rx_list[pos]; 979 if (!(cur_rx->rd_rsr & htole32(RSR_OWN))) 980 break; 981 pos = (pos + 1) % MTD_RX_LIST_CNT; 982 } 983 984 /* If the ring really is empty, then just return. */ 985 if (i == MTD_RX_LIST_CNT) 986 return (0); 987 988 /* We've fallen behind the chip: catch it. */ 989 sc->mtd_cdata.mtd_rx_prod = pos; 990 991 return (EAGAIN); 992} 993 994 995/* 996 * A frame was downloaded to the chip. It's safe for us to clean up 997 * the list buffers. 998 */ 999static void 1000mtd_txeof(struct mtd_softc *sc) 1001{ 1002 struct mtd_tx_desc *cur_tx = NULL; 1003 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1004 int idx; 1005 1006 /* Clear the timeout timer. */ 1007 ifp->if_timer = 0; 1008 1009 /* 1010 * Go through our tx list and free mbufs for those 1011 * frames that have been transmitted. 1012 */ 1013 idx = sc->mtd_cdata.mtd_tx_cons; 1014 while(idx != sc->mtd_cdata.mtd_tx_prod) { 1015 u_int32_t txstat; 1016 1017 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 1018 offsetof(struct mtd_list_data, mtd_tx_list[idx]), 1019 sizeof(struct mtd_tx_desc), 1020 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1021 1022 cur_tx = &sc->mtd_ldata->mtd_tx_list[idx]; 1023 txstat = letoh32(cur_tx->td_tsw); 1024 1025 if (txstat & TSW_OWN || txstat == TSW_UNSENT) 1026 break; 1027 1028 if (!(cur_tx->td_tcw & htole32(TCW_LD))) { 1029 sc->mtd_cdata.mtd_tx_cnt--; 1030 idx = (idx + 1) % MTD_TX_LIST_CNT; 1031 continue; 1032 } 1033 1034 if (CSR_READ_4(MTD_TCRRCR) & TCR_ENHANCED) 1035 ifp->if_collisions += TSR_NCR_GET(CSR_READ_4(MTD_TSR)); 1036 else { 1037 if (txstat & TSW_TXERR) { 1038 ifp->if_oerrors++; 1039 if (txstat & TSW_EC) 1040 ifp->if_collisions++; 1041 if (txstat & TSW_LC) 1042 ifp->if_collisions++; 1043 } 1044 ifp->if_collisions += TSW_NCR_GET(txstat); 1045 } 1046 1047 ifp->if_opackets++; 1048 if (sc->mtd_cdata.mtd_tx_chain[idx].sd_map->dm_nsegs != 0) { 1049 bus_dmamap_t map = 1050 sc->mtd_cdata.mtd_tx_chain[idx].sd_map; 1051 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1052 BUS_DMASYNC_POSTWRITE); 1053 bus_dmamap_unload(sc->sc_dmat, map); 1054 } 1055 if (sc->mtd_cdata.mtd_tx_chain[idx].sd_mbuf != NULL) { 1056 m_freem(sc->mtd_cdata.mtd_tx_chain[idx].sd_mbuf); 1057 sc->mtd_cdata.mtd_tx_chain[idx].sd_mbuf = NULL; 1058 } 1059 sc->mtd_cdata.mtd_tx_cnt--; 1060 idx = (idx + 1) % MTD_TX_LIST_CNT; 1061 } 1062 1063 if (cur_tx != NULL) { 1064 ifp->if_flags &= ~IFF_OACTIVE; 1065 sc->mtd_cdata.mtd_tx_cons = idx; 1066 } else 1067 if (sc->mtd_ldata->mtd_tx_list[idx].td_tsw == 1068 htole32(TSW_UNSENT)) { 1069 sc->mtd_ldata->mtd_tx_list[idx].td_tsw = 1070 htole32(TSW_OWN); 1071 ifp->if_timer = 5; 1072 CSR_WRITE_4(MTD_TXPDR, 0xffffffff); 1073 } 1074} 1075 1076struct cfdriver mtd_cd = { 1077 0, "mtd", DV_IFNET 1078}; 1079