mtd8xx.c revision 1.15
1/* $OpenBSD: mtd8xx.c,v 1.15 2008/10/14 18:01:53 naddy Exp $ */ 2 3/* 4 * Copyright (c) 2003 Oleg Safiullin <form@pdp11.org.ru> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31#include "bpfilter.h" 32 33#include <sys/param.h> 34#include <sys/mbuf.h> 35#include <sys/systm.h> 36#include <sys/device.h> 37#include <sys/socket.h> 38#include <sys/ioctl.h> 39 40#include <net/if.h> 41#include <net/if_media.h> 42 43#if NBPFILTER > 0 44#include <net/bpf.h> 45#endif 46 47#ifdef INET 48#include <netinet/in.h> 49#include <netinet/if_ether.h> 50#endif 51 52#include <machine/bus.h> 53 54#include <dev/mii/mii.h> 55#include <dev/mii/miivar.h> 56 57#include <dev/pci/pcidevs.h> 58#include <dev/pci/pcivar.h> 59 60#include <dev/ic/mtd8xxreg.h> 61#include <dev/ic/mtd8xxvar.h> 62 63 64static int mtd_ifmedia_upd(struct ifnet *); 65static void mtd_ifmedia_sts(struct ifnet *, struct ifmediareq *); 66 67static u_int32_t mtd_mii_command(struct mtd_softc *, int, int, int); 68static int mtd_miibus_readreg(struct device *, int, int); 69static void mtd_miibus_writereg(struct device *, int, int, int); 70static void mtd_miibus_statchg(struct device *); 71static void mtd_setmulti(struct mtd_softc *); 72 73static int mtd_encap(struct mtd_softc *, struct mbuf *, u_int32_t *); 74static int mtd_list_rx_init(struct mtd_softc *); 75static void mtd_list_tx_init(struct mtd_softc *); 76static int mtd_newbuf(struct mtd_softc *, int, struct mbuf *); 77 78static void mtd_reset(struct mtd_softc *sc); 79static int mtd_ioctl(struct ifnet *, u_long, caddr_t); 80static void mtd_init(struct ifnet *); 81static void mtd_start(struct ifnet *); 82static void mtd_stop(struct ifnet *); 83static void mtd_watchdog(struct ifnet *); 84 85static void mtd_rxeof(struct mtd_softc *); 86static int mtd_rx_resync(struct mtd_softc *); 87static void mtd_txeof(struct mtd_softc *); 88 89 90void 91mtd_attach(struct mtd_softc *sc) 92{ 93 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 94 u_int32_t enaddr[2]; 95 int i; 96 97 /* Reset the adapter. */ 98 mtd_reset(sc); 99 100 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct mtd_list_data), 101 PAGE_SIZE, 0, sc->sc_listseg, 1, &sc->sc_listnseg, 102 BUS_DMA_NOWAIT) != 0) { 103 printf(": can't alloc list mem\n"); 104 return; 105 } 106 if (bus_dmamem_map(sc->sc_dmat, sc->sc_listseg, sc->sc_listnseg, 107 sizeof(struct mtd_list_data), &sc->sc_listkva, 108 BUS_DMA_NOWAIT) != 0) { 109 printf(": can't map list mem\n"); 110 return; 111 } 112 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct mtd_list_data), 1, 113 sizeof(struct mtd_list_data), 0, BUS_DMA_NOWAIT, 114 &sc->sc_listmap) != 0) { 115 printf(": can't alloc list map\n"); 116 return; 117 } 118 if (bus_dmamap_load(sc->sc_dmat, sc->sc_listmap, sc->sc_listkva, 119 sizeof(struct mtd_list_data), NULL, BUS_DMA_NOWAIT) != 0) { 120 printf(": can't load list map\n"); 121 return; 122 } 123 sc->mtd_ldata = (struct mtd_list_data *)sc->sc_listkva; 124 bzero(sc->mtd_ldata, sizeof(struct mtd_list_data)); 125 126 for (i = 0; i < MTD_RX_LIST_CNT; i++) { 127 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 128 0, BUS_DMA_NOWAIT, 129 &sc->mtd_cdata.mtd_rx_chain[i].sd_map) != 0) { 130 printf(": can't create rx map\n"); 131 return; 132 } 133 } 134 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, 135 BUS_DMA_NOWAIT, &sc->sc_rx_sparemap) != 0) { 136 printf(": can't create rx spare map\n"); 137 return; 138 } 139 140 for (i = 0; i < MTD_TX_LIST_CNT; i++) { 141 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 142 MTD_TX_LIST_CNT - 5, MCLBYTES, 0, BUS_DMA_NOWAIT, 143 &sc->mtd_cdata.mtd_tx_chain[i].sd_map) != 0) { 144 printf(": can't create tx map\n"); 145 return; 146 } 147 } 148 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, MTD_TX_LIST_CNT - 5, 149 MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_tx_sparemap) != 0) { 150 printf(": can't create tx spare map\n"); 151 return; 152 } 153 154 155 /* Get station address. */ 156 enaddr[0] = letoh32(CSR_READ_4(MTD_PAR0)); 157 enaddr[1] = letoh32(CSR_READ_4(MTD_PAR4)); 158 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 159 printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); 160 161 /* Initialize interface */ 162 ifp->if_softc = sc; 163 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 164 ifp->if_ioctl = mtd_ioctl; 165 ifp->if_start = mtd_start; 166 ifp->if_watchdog = mtd_watchdog; 167 ifp->if_baudrate = 10000000; 168 IFQ_SET_READY(&ifp->if_snd); 169 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 170 171 ifp->if_capabilities = IFCAP_VLAN_MTU; 172 173 /* 174 * Initialize our media structures and probe the MII. 175 */ 176 sc->sc_mii.mii_ifp = ifp; 177 sc->sc_mii.mii_readreg = mtd_miibus_readreg; 178 sc->sc_mii.mii_writereg = mtd_miibus_writereg; 179 sc->sc_mii.mii_statchg = mtd_miibus_statchg; 180 ifmedia_init(&sc->sc_mii.mii_media, 0, mtd_ifmedia_upd, 181 mtd_ifmedia_sts); 182 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 183 MII_OFFSET_ANY, 0); 184 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 185 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE, 0, 186 NULL); 187 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE); 188 } else 189 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 190 191 /* 192 * Attach us everywhere 193 */ 194 if_attach(ifp); 195 ether_ifattach(ifp); 196} 197 198 199static int 200mtd_ifmedia_upd(struct ifnet *ifp) 201{ 202 struct mtd_softc *sc = ifp->if_softc; 203 204 return (mii_mediachg(&sc->sc_mii)); 205} 206 207 208static void 209mtd_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 210{ 211 struct mtd_softc *sc = ifp->if_softc; 212 213 mii_pollstat(&sc->sc_mii); 214 ifmr->ifm_active = sc->sc_mii.mii_media_active; 215 ifmr->ifm_status = sc->sc_mii.mii_media_status; 216} 217 218 219static u_int32_t 220mtd_mii_command(struct mtd_softc *sc, int opcode, int phy, int reg) 221{ 222 u_int32_t miir, mask, data; 223 int i; 224 225 miir = (CSR_READ_4(MTD_MIIMGT) & ~MIIMGT_MASK) | MIIMGT_WRITE | 226 MIIMGT_MDO; 227 228 for (i = 0; i < 32; i++) { 229 miir &= ~MIIMGT_MDC; 230 CSR_WRITE_4(MTD_MIIMGT, miir); 231 miir |= MIIMGT_MDC; 232 CSR_WRITE_4(MTD_MIIMGT, miir); 233 } 234 235 data = opcode | (phy << 7) | (reg << 2); 236 237 for (mask = 0; mask; mask >>= 1) { 238 miir &= ~(MIIMGT_MDC | MIIMGT_MDO); 239 if (mask & data) 240 miir |= MIIMGT_MDO; 241 CSR_WRITE_4(MTD_MIIMGT, miir); 242 miir |= MIIMGT_MDC; 243 CSR_WRITE_4(MTD_MIIMGT, miir); 244 DELAY(30); 245 246 if (mask == 0x4 && opcode == MII_OPCODE_RD) 247 miir &= ~MIIMGT_WRITE; 248 } 249 return (miir); 250} 251 252 253 254static int 255mtd_miibus_readreg(struct device *self, int phy, int reg) 256{ 257 struct mtd_softc *sc = (void *)self; 258 259 if (sc->sc_devid == PCI_PRODUCT_MYSON_MTD803) 260 return (phy ? 0 : (int)CSR_READ_2(MTD_PHYCSR + (reg << 1))); 261 else { 262 u_int32_t miir, mask, data; 263 264 miir = mtd_mii_command(sc, MII_OPCODE_RD, phy, reg); 265 for (mask = 0x8000, data = 0; mask; mask >>= 1) { 266 miir &= ~MIIMGT_MDC; 267 CSR_WRITE_4(MTD_MIIMGT, miir); 268 miir = CSR_READ_4(MTD_MIIMGT); 269 if (miir & MIIMGT_MDI) 270 data |= mask; 271 miir |= MIIMGT_MDC; 272 CSR_WRITE_4(MTD_MIIMGT, miir); 273 DELAY(30); 274 } 275 miir &= ~MIIMGT_MDC; 276 CSR_WRITE_4(MTD_MIIMGT, miir); 277 278 return ((int)data); 279 } 280} 281 282 283static void 284mtd_miibus_writereg(struct device *self, int phy, int reg, int val) 285{ 286 struct mtd_softc *sc = (void *)self; 287 288 if (sc->sc_devid == PCI_PRODUCT_MYSON_MTD803) { 289 if (!phy) 290 CSR_WRITE_2(MTD_PHYCSR + (reg << 1), val); 291 } else { 292 u_int32_t miir, mask; 293 294 miir = mtd_mii_command(sc, MII_OPCODE_WR, phy, reg); 295 for (mask = 0x8000; mask; mask >>= 1) { 296 miir &= ~(MIIMGT_MDC | MIIMGT_MDO); 297 if (mask & (u_int32_t)val) 298 miir |= MIIMGT_MDO; 299 CSR_WRITE_4(MTD_MIIMGT, miir); 300 miir |= MIIMGT_MDC; 301 CSR_WRITE_4(MTD_MIIMGT, miir); 302 DELAY(1); 303 } 304 miir &= ~MIIMGT_MDC; 305 CSR_WRITE_4(MTD_MIIMGT, miir); 306 } 307} 308 309 310static void 311mtd_miibus_statchg(struct device *self) 312{ 313 /* NOTHING */ 314} 315 316 317void 318mtd_setmulti(struct mtd_softc *sc) 319{ 320 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 321 u_int32_t rxfilt, crc, hash[2] = { 0, 0 }; 322 struct ether_multistep step; 323 struct ether_multi *enm; 324 int mcnt = 0; 325 326allmulti: 327 rxfilt = CSR_READ_4(MTD_TCRRCR) & ~RCR_AM; 328 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 329 rxfilt |= RCR_AM; 330 CSR_WRITE_4(MTD_TCRRCR, rxfilt); 331 CSR_WRITE_4(MTD_MAR0, 0xffffffff); 332 CSR_WRITE_4(MTD_MAR4, 0xffffffff); 333 return; 334 } 335 336 /* First, zot all the existing hash bits. */ 337 CSR_WRITE_4(MTD_MAR0, 0); 338 CSR_WRITE_4(MTD_MAR4, 0); 339 340 /* Now program new ones. */ 341 ETHER_FIRST_MULTI(step, &sc->sc_arpcom, enm); 342 while (enm != NULL) { 343 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 344 ifp->if_flags |= IFF_ALLMULTI; 345 goto allmulti; 346 } 347 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 348 hash[crc >> 5] |= 1 << (crc & 0xf); 349 ++mcnt; 350 ETHER_NEXT_MULTI(step, enm); 351 } 352 353 if (mcnt) 354 rxfilt |= RCR_AM; 355 CSR_WRITE_4(MTD_MAR0, hash[0]); 356 CSR_WRITE_4(MTD_MAR4, hash[1]); 357 CSR_WRITE_4(MTD_TCRRCR, rxfilt); 358} 359 360 361/* 362 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 363 * pointers to the fragment pointers. 364 */ 365int 366mtd_encap(struct mtd_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 367{ 368 struct mtd_tx_desc *f = NULL; 369 int frag, cur, cnt = 0, i, total_len = 0; 370 bus_dmamap_t map; 371 372 /* 373 * Start packing the mbufs in this chain into 374 * the fragment pointers. Stop when we run out 375 * of fragments or hit the end of the mbuf chain. 376 */ 377 map = sc->sc_tx_sparemap; 378 379 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, 380 m_head, BUS_DMA_NOWAIT) != 0) 381 return (1); 382 383 cur = frag = *txidx; 384 385 for (i = 0; i < map->dm_nsegs; i++) { 386 if ((MTD_TX_LIST_CNT - 387 (sc->mtd_cdata.mtd_tx_cnt + cnt)) < 5) { 388 bus_dmamap_unload(sc->sc_dmat, map); 389 return (1); 390 } 391 392 f = &sc->mtd_ldata->mtd_tx_list[frag]; 393 f->td_tcw = htole32(map->dm_segs[i].ds_len); 394 total_len += map->dm_segs[i].ds_len; 395 if (cnt == 0) { 396 f->td_tsw = 0; 397 f->td_tcw |= htole32(TCW_FD | TCW_CRC | TCW_PAD); 398 } else 399 f->td_tsw = htole32(TSW_OWN); 400 f->td_buf = htole32(map->dm_segs[i].ds_addr); 401 cur = frag; 402 frag = (frag + 1) % MTD_TX_LIST_CNT; 403 cnt++; 404 } 405 406 sc->mtd_cdata.mtd_tx_cnt += cnt; 407 sc->mtd_cdata.mtd_tx_chain[cur].sd_mbuf = m_head; 408 sc->sc_tx_sparemap = sc->mtd_cdata.mtd_tx_chain[cur].sd_map; 409 sc->mtd_cdata.mtd_tx_chain[cur].sd_map = map; 410 sc->mtd_ldata->mtd_tx_list[cur].td_tcw |= htole32(TCW_LD | TCW_IC); 411 if (sc->sc_devid == PCI_PRODUCT_MYSON_MTD891) 412 sc->mtd_ldata->mtd_tx_list[cur].td_tcw |= 413 htole32(TCW_EIC | TCW_RTLC); 414 415 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 416 BUS_DMASYNC_PREWRITE); 417 418 sc->mtd_ldata->mtd_tx_list[*txidx].td_tsw = htole32(TSW_OWN); 419 sc->mtd_ldata->mtd_tx_list[*txidx].td_tcw |= 420 htole32(total_len << TCW_PKTS_SHIFT); 421 422 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 423 offsetof(struct mtd_list_data, mtd_tx_list[0]), 424 sizeof(struct mtd_tx_desc) * MTD_TX_LIST_CNT, 425 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 426 427 *txidx = frag; 428 429 return (0); 430} 431 432 433/* 434 * Initialize the transmit descriptors. 435 */ 436static void 437mtd_list_tx_init(struct mtd_softc *sc) 438{ 439 struct mtd_chain_data *cd; 440 struct mtd_list_data *ld; 441 int i; 442 443 cd = &sc->mtd_cdata; 444 ld = sc->mtd_ldata; 445 for (i = 0; i < MTD_TX_LIST_CNT; i++) { 446 cd->mtd_tx_chain[i].sd_mbuf = NULL; 447 ld->mtd_tx_list[i].td_tsw = 0; 448 ld->mtd_tx_list[i].td_tcw = 0; 449 ld->mtd_tx_list[i].td_buf = 0; 450 ld->mtd_tx_list[i].td_next = htole32( 451 sc->sc_listmap->dm_segs[0].ds_addr + 452 offsetof(struct mtd_list_data, 453 mtd_tx_list[(i + 1) % MTD_TX_LIST_CNT])); 454 } 455 456 cd->mtd_tx_prod = cd->mtd_tx_cons = cd->mtd_tx_cnt = 0; 457} 458 459 460/* 461 * Initialize the RX descriptors and allocate mbufs for them. Note that 462 * we arrange the descriptors in a closed ring, so that the last descriptor 463 * points back to the first. 464 */ 465static int 466mtd_list_rx_init(struct mtd_softc *sc) 467{ 468 struct mtd_list_data *ld; 469 int i; 470 471 ld = sc->mtd_ldata; 472 473 for (i = 0; i < MTD_RX_LIST_CNT; i++) { 474 if (mtd_newbuf(sc, i, NULL)) 475 return (1); 476 ld->mtd_rx_list[i].rd_next = htole32( 477 sc->sc_listmap->dm_segs[0].ds_addr + 478 offsetof(struct mtd_list_data, 479 mtd_rx_list[(i + 1) % MTD_RX_LIST_CNT]) 480 ); 481 } 482 483 sc->mtd_cdata.mtd_rx_prod = 0; 484 485 return (0); 486} 487 488 489/* 490 * Initialize an RX descriptor and attach an MBUF cluster. 491 */ 492static int 493mtd_newbuf(struct mtd_softc *sc, int i, struct mbuf *m) 494{ 495 struct mbuf *m_new = NULL; 496 struct mtd_rx_desc *c; 497 bus_dmamap_t map; 498 499 c = &sc->mtd_ldata->mtd_rx_list[i]; 500 501 if (m == NULL) { 502 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 503 if (m_new == NULL) 504 return (1); 505 506 MCLGET(m_new, M_DONTWAIT); 507 if (!(m_new->m_flags & M_EXT)) { 508 m_freem(m_new); 509 return (1); 510 } 511 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 512 if (bus_dmamap_load(sc->sc_dmat, sc->sc_rx_sparemap, 513 mtod(m_new, caddr_t), MCLBYTES, NULL, 514 BUS_DMA_NOWAIT) != 0) { 515 m_freem(m_new); 516 return (1); 517 } 518 map = sc->mtd_cdata.mtd_rx_chain[i].sd_map; 519 sc->mtd_cdata.mtd_rx_chain[i].sd_map = sc->sc_rx_sparemap; 520 sc->sc_rx_sparemap = map; 521 } else { 522 m_new = m; 523 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 524 m_new->m_data = m_new->m_ext.ext_buf; 525 } 526 527 m_adj(m_new, sizeof(u_int64_t)); 528 529 bus_dmamap_sync(sc->sc_dmat, sc->mtd_cdata.mtd_rx_chain[i].sd_map, 0, 530 sc->mtd_cdata.mtd_rx_chain[i].sd_map->dm_mapsize, 531 BUS_DMASYNC_PREREAD); 532 533 sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf = m_new; 534 c->rd_buf = htole32( 535 sc->mtd_cdata.mtd_rx_chain[i].sd_map->dm_segs[0].ds_addr + 536 sizeof(u_int64_t)); 537 c->rd_rcw = htole32(ETHER_MAX_DIX_LEN); 538 c->rd_rsr = htole32(RSR_OWN); 539 540 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 541 offsetof(struct mtd_list_data, mtd_rx_list[i]), 542 sizeof(struct mtd_rx_desc), 543 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 544 545 return (0); 546} 547 548 549static void 550mtd_reset(struct mtd_softc *sc) 551{ 552 int i; 553 554 /* Set software reset bit */ 555 CSR_WRITE_4(MTD_BCR, BCR_SWR); 556 557 /* 558 * Wait until software reset completed. 559 */ 560 for (i = 0; i < MTD_TIMEOUT; ++i) { 561 DELAY(10); 562 if (!(CSR_READ_4(MTD_BCR) & BCR_SWR)) { 563 /* 564 * Wait a little while for the chip to get 565 * its brains in order. 566 */ 567 DELAY(1000); 568 return; 569 } 570 } 571 572 /* Reset timed out. */ 573 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 574} 575 576 577static int 578mtd_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 579{ 580 struct mtd_softc *sc = ifp->if_softc; 581 struct ifreq *ifr = (struct ifreq *)data; 582 struct ifaddr *ifa = (struct ifaddr *)data; 583 int s, error = 0; 584 585 s = splnet(); 586 587 switch (command) { 588 case SIOCSIFADDR: 589 ifp->if_flags |= IFF_UP; 590 mtd_init(ifp); 591 switch (ifa->ifa_addr->sa_family) { 592#ifdef INET 593 case AF_INET: 594 arp_ifinit(&sc->sc_arpcom, ifa); 595 break; 596#endif /* INET */ 597 } 598 break; 599 case SIOCSIFMTU: 600 if (ifr->ifr_mtu >= ETHERMIN && ifr->ifr_mtu <= ETHERMTU) 601 ifp->if_mtu = ifr->ifr_mtu; 602 else 603 error = EINVAL; 604 break; 605 606 case SIOCSIFFLAGS: 607 if (ifp->if_flags & IFF_UP) 608 mtd_init(ifp); 609 else { 610 if (ifp->if_flags & IFF_RUNNING) 611 mtd_stop(ifp); 612 } 613 error = 0; 614 break; 615 case SIOCADDMULTI: 616 case SIOCDELMULTI: 617 error = (command == SIOCADDMULTI) ? 618 ether_addmulti(ifr, &sc->sc_arpcom) : 619 ether_delmulti(ifr, &sc->sc_arpcom); 620 621 if (error == ENETRESET) { 622 /* 623 * Multicast list has changed; set the hardware 624 * filter accordingly. 625 */ 626 if (ifp->if_flags & IFF_RUNNING) 627 mtd_setmulti(sc); 628 error = 0; 629 } 630 break; 631 case SIOCGIFMEDIA: 632 case SIOCSIFMEDIA: 633 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 634 break; 635 default: 636 error = ether_ioctl(ifp, &sc->sc_arpcom, command, data); 637 } 638 639 splx(s); 640 return (error); 641} 642 643 644static void 645mtd_init(struct ifnet *ifp) 646{ 647 struct mtd_softc *sc = ifp->if_softc; 648 int s; 649 650 s = splnet(); 651 652 /* 653 * Cancel pending I/O and free all RX/TX buffers. 654 */ 655 mtd_stop(ifp); 656 657 /* 658 * Set cache alignment and burst length. 659 */ 660 CSR_WRITE_4(MTD_BCR, BCR_PBL8); 661 CSR_WRITE_4(MTD_TCRRCR, TCR_TFTSF | RCR_RBLEN | RCR_RPBL512); 662 if (sc->sc_devid == PCI_PRODUCT_MYSON_MTD891) { 663 CSR_SETBIT(MTD_BCR, BCR_PROG); 664 CSR_SETBIT(MTD_TCRRCR, TCR_ENHANCED); 665 } 666 667 if (ifp->if_flags & IFF_PROMISC) 668 CSR_SETBIT(MTD_TCRRCR, RCR_PROM); 669 else 670 CSR_CLRBIT(MTD_TCRRCR, RCR_PROM); 671 672 if (ifp->if_flags & IFF_BROADCAST) 673 CSR_SETBIT(MTD_TCRRCR, RCR_AB); 674 else 675 CSR_CLRBIT(MTD_TCRRCR, RCR_AB); 676 677 mtd_setmulti(sc); 678 679 if (mtd_list_rx_init(sc)) { 680 printf("%s: can't allocate memeory for rx buffers\n", 681 sc->sc_dev.dv_xname); 682 splx(s); 683 return; 684 } 685 mtd_list_tx_init(sc); 686 687 CSR_WRITE_4(MTD_RXLBA, sc->sc_listmap->dm_segs[0].ds_addr + 688 offsetof(struct mtd_list_data, mtd_rx_list[0])); 689 CSR_WRITE_4(MTD_TXLBA, sc->sc_listmap->dm_segs[0].ds_addr + 690 offsetof(struct mtd_list_data, mtd_tx_list[0])); 691 692 /* 693 * Enable interrupts. 694 */ 695 CSR_WRITE_4(MTD_IMR, IMR_INTRS); 696 CSR_WRITE_4(MTD_ISR, 0xffffffff); 697 698 /* Enable receiver and transmitter */ 699 CSR_SETBIT(MTD_TCRRCR, TCR_TE | RCR_RE); 700 CSR_WRITE_4(MTD_RXPDR, 0xffffffff); 701 702 ifp->if_flags |= IFF_RUNNING; 703 ifp->if_flags &= ~IFF_OACTIVE; 704 splx(s); 705} 706 707 708/* 709 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 710 * to the mbuf data regions directly in the transmit lists. We also save a 711 * copy of the pointers since the transmit list fragment pointers are 712 * physical addresses. 713 */ 714static void 715mtd_start(struct ifnet *ifp) 716{ 717 struct mtd_softc *sc = ifp->if_softc; 718 struct mbuf *m_head = NULL; 719 int idx; 720 721 if (sc->mtd_cdata.mtd_tx_cnt) { 722 ifp->if_flags |= IFF_OACTIVE; 723 return; 724 } 725 726 idx = sc->mtd_cdata.mtd_tx_prod; 727 while (sc->mtd_cdata.mtd_tx_chain[idx].sd_mbuf == NULL) { 728 IFQ_DEQUEUE(&ifp->if_snd, m_head); 729 if (m_head == NULL) 730 break; 731 732 if (mtd_encap(sc, m_head, &idx)) { 733 ifp->if_flags |= IFF_OACTIVE; 734 break; 735 } 736 737 /* 738 * If there's a BPF listener, bounce a copy of this frame 739 * to him. 740 */ 741#if NBPFILTER > 0 742 if (ifp->if_bpf != NULL) 743 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 744#endif 745 } 746 747 if (idx == sc->mtd_cdata.mtd_tx_prod) 748 return; 749 750 /* Transmit */ 751 sc->mtd_cdata.mtd_tx_prod = idx; 752 CSR_WRITE_4(MTD_TXPDR, 0xffffffff); 753 754 /* 755 * Set a timeout in case the chip goes out to lunch. 756 */ 757 ifp->if_timer = 5; 758} 759 760 761static void 762mtd_stop(struct ifnet *ifp) 763{ 764 struct mtd_softc *sc = ifp->if_softc; 765 int i; 766 767 ifp->if_timer = 0; 768 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 769 770 CSR_CLRBIT(MTD_TCRRCR, (RCR_RE | TCR_TE)); 771 CSR_WRITE_4(MTD_IMR, 0); 772 CSR_WRITE_4(MTD_TXLBA, 0); 773 CSR_WRITE_4(MTD_RXLBA, 0); 774 775 /* 776 * Free data in the RX lists. 777 */ 778 for (i = 0; i < MTD_RX_LIST_CNT; i++) { 779 if (sc->mtd_cdata.mtd_rx_chain[i].sd_map->dm_nsegs != 0) { 780 bus_dmamap_t map = sc->mtd_cdata.mtd_rx_chain[i].sd_map; 781 782 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 783 BUS_DMASYNC_POSTREAD); 784 bus_dmamap_unload(sc->sc_dmat, map); 785 } 786 if (sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf != NULL) { 787 m_freem(sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf); 788 sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf = NULL; 789 } 790 } 791 bzero((char *)&sc->mtd_ldata->mtd_rx_list, 792 sizeof(sc->mtd_ldata->mtd_rx_list)); 793 794 /* 795 * Free the TX list buffers. 796 */ 797 for (i = 0; i < MTD_TX_LIST_CNT; i++) { 798 if (sc->mtd_cdata.mtd_tx_chain[i].sd_map->dm_nsegs != 0) { 799 bus_dmamap_t map = sc->mtd_cdata.mtd_tx_chain[i].sd_map; 800 801 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 802 BUS_DMASYNC_POSTWRITE); 803 bus_dmamap_unload(sc->sc_dmat, map); 804 } 805 if (sc->mtd_cdata.mtd_tx_chain[i].sd_mbuf != NULL) { 806 m_freem(sc->mtd_cdata.mtd_tx_chain[i].sd_mbuf); 807 sc->mtd_cdata.mtd_tx_chain[i].sd_mbuf = NULL; 808 } 809 } 810 811 bzero((char *)&sc->mtd_ldata->mtd_tx_list, 812 sizeof(sc->mtd_ldata->mtd_tx_list)); 813 814} 815 816 817static void 818mtd_watchdog(struct ifnet *ifp) 819{ 820 struct mtd_softc *sc = ifp->if_softc; 821 822 ifp->if_oerrors++; 823 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 824 825 mtd_stop(ifp); 826 mtd_reset(sc); 827 mtd_init(ifp); 828 829 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 830 mtd_start(ifp); 831} 832 833 834int 835mtd_intr(void *xsc) 836{ 837 struct mtd_softc *sc = xsc; 838 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 839 u_int32_t status; 840 int claimed = 0; 841 842 /* Suppress unwanted interrupts */ 843 if (!(ifp->if_flags & IFF_RUNNING)) { 844 if (CSR_READ_4(MTD_ISR) & ISR_INTRS) 845 mtd_stop(ifp); 846 return (claimed); 847 } 848 849 /* Disable interrupts. */ 850 CSR_WRITE_4(MTD_IMR, 0); 851 852 while((status = CSR_READ_4(MTD_ISR)) & ISR_INTRS) { 853 claimed = 1; 854 855 CSR_WRITE_4(MTD_ISR, status); 856 857 /* RX interrupt. */ 858 if (status & ISR_RI) { 859 int curpkts = ifp->if_ipackets; 860 861 mtd_rxeof(sc); 862 if (curpkts == ifp->if_ipackets) 863 while(mtd_rx_resync(sc)) 864 mtd_rxeof(sc); 865 } 866 867 /* RX error interrupt. */ 868 if (status & (ISR_RXERI | ISR_RBU)) 869 ifp->if_ierrors++; 870 871 /* TX interrupt. */ 872 if (status & (ISR_TI | ISR_ETI | ISR_TBU)) 873 mtd_txeof(sc); 874 875 /* Fatal bus error interrupt. */ 876 if (status & ISR_FBE) { 877 mtd_reset(sc); 878 mtd_start(ifp); 879 } 880 } 881 882 /* Re-enable interrupts. */ 883 CSR_WRITE_4(MTD_IMR, IMR_INTRS); 884 885 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 886 mtd_start(ifp); 887 888 return (claimed); 889} 890 891 892/* 893 * A frame has been uploaded: pass the resulting mbuf chain up to 894 * the higher level protocols. 895 */ 896static void 897mtd_rxeof(struct mtd_softc *sc) 898{ 899 struct mbuf *m; 900 struct ifnet *ifp; 901 struct mtd_rx_desc *cur_rx; 902 int i, total_len = 0; 903 u_int32_t rxstat; 904 905 ifp = &sc->sc_arpcom.ac_if; 906 i = sc->mtd_cdata.mtd_rx_prod; 907 908 while(!(sc->mtd_ldata->mtd_rx_list[i].rd_rsr & htole32(RSR_OWN))) { 909 struct mbuf *m0 = NULL; 910 911 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 912 offsetof(struct mtd_list_data, mtd_rx_list[i]), 913 sizeof(struct mtd_rx_desc), 914 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 915 916 cur_rx = &sc->mtd_ldata->mtd_rx_list[i]; 917 rxstat = letoh32(cur_rx->rd_rsr); 918 m = sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf; 919 total_len = RSR_FLNG_GET(rxstat); 920 921 sc->mtd_cdata.mtd_rx_chain[i].sd_mbuf = NULL; 922 923 /* 924 * If an error occurs, update stats, clear the 925 * status word and leave the mbuf cluster in place: 926 * it should simply get re-used next time this descriptor 927 * comes up in the ring. 928 */ 929 if (rxstat & RSR_RXER) { 930 ifp->if_ierrors++; 931 mtd_newbuf(sc, i, m); 932 if (rxstat & RSR_CRC) { 933 i = (i + 1) % MTD_RX_LIST_CNT; 934 continue; 935 } else { 936 mtd_init(ifp); 937 return; 938 } 939 } 940 941 /* No errors; receive the packet. */ 942 total_len -= ETHER_CRC_LEN; 943 944 bus_dmamap_sync(sc->sc_dmat, sc->mtd_cdata.mtd_rx_chain[i].sd_map, 945 0, sc->mtd_cdata.mtd_rx_chain[i].sd_map->dm_mapsize, 946 BUS_DMASYNC_POSTREAD); 947 948 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 949 ifp, NULL); 950 mtd_newbuf(sc, i, m); 951 i = (i + 1) % MTD_RX_LIST_CNT; 952 if (m0 == NULL) { 953 ifp->if_ierrors++; 954 continue; 955 } 956 m = m0; 957 958 ifp->if_ipackets++; 959 960#if NBPFILTER > 0 961 if (ifp->if_bpf) 962 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 963#endif 964 ether_input_mbuf(ifp, m); 965 } 966 967 sc->mtd_cdata.mtd_rx_prod = i; 968} 969 970 971/* 972 * This routine searches the RX ring for dirty descriptors in the 973 * event that the rxeof routine falls out of sync with the chip's 974 * current descriptor pointer. This may happen sometimes as a result 975 * of a "no RX buffer available" condition that happens when the chip 976 * consumes all of the RX buffers before the driver has a chance to 977 * process the RX ring. This routine may need to be called more than 978 * once to bring the driver back in sync with the chip, however we 979 * should still be getting RX DONE interrupts to drive the search 980 * for new packets in the RX ring, so we should catch up eventually. 981 */ 982static int 983mtd_rx_resync(sc) 984 struct mtd_softc *sc; 985{ 986 int i, pos; 987 struct mtd_rx_desc *cur_rx; 988 989 pos = sc->mtd_cdata.mtd_rx_prod; 990 991 for (i = 0; i < MTD_RX_LIST_CNT; i++) { 992 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 993 offsetof(struct mtd_list_data, mtd_rx_list[pos]), 994 sizeof(struct mtd_rx_desc), 995 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 996 997 cur_rx = &sc->mtd_ldata->mtd_rx_list[pos]; 998 if (!(cur_rx->rd_rsr & htole32(RSR_OWN))) 999 break; 1000 pos = (pos + 1) % MTD_RX_LIST_CNT; 1001 } 1002 1003 /* If the ring really is empty, then just return. */ 1004 if (i == MTD_RX_LIST_CNT) 1005 return (0); 1006 1007 /* We've fallen behind the chip: catch it. */ 1008 sc->mtd_cdata.mtd_rx_prod = pos; 1009 1010 return (EAGAIN); 1011} 1012 1013 1014/* 1015 * A frame was downloaded to the chip. It's safe for us to clean up 1016 * the list buffers. 1017 */ 1018static void 1019mtd_txeof(struct mtd_softc *sc) 1020{ 1021 struct mtd_tx_desc *cur_tx = NULL; 1022 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1023 int idx; 1024 1025 /* Clear the timeout timer. */ 1026 ifp->if_timer = 0; 1027 1028 /* 1029 * Go through our tx list and free mbufs for those 1030 * frames that have been transmitted. 1031 */ 1032 idx = sc->mtd_cdata.mtd_tx_cons; 1033 while(idx != sc->mtd_cdata.mtd_tx_prod) { 1034 u_int32_t txstat; 1035 1036 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 1037 offsetof(struct mtd_list_data, mtd_tx_list[idx]), 1038 sizeof(struct mtd_tx_desc), 1039 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1040 1041 cur_tx = &sc->mtd_ldata->mtd_tx_list[idx]; 1042 txstat = letoh32(cur_tx->td_tsw); 1043 1044 if (txstat & TSW_OWN || txstat == TSW_UNSENT) 1045 break; 1046 1047 if (!(cur_tx->td_tcw & htole32(TCW_LD))) { 1048 sc->mtd_cdata.mtd_tx_cnt--; 1049 idx = (idx + 1) % MTD_TX_LIST_CNT; 1050 continue; 1051 } 1052 1053 if (CSR_READ_4(MTD_TCRRCR) & TCR_ENHANCED) 1054 ifp->if_collisions += TSR_NCR_GET(CSR_READ_4(MTD_TSR)); 1055 else { 1056 if (txstat & TSW_TXERR) { 1057 ifp->if_oerrors++; 1058 if (txstat & TSW_EC) 1059 ifp->if_collisions++; 1060 if (txstat & TSW_LC) 1061 ifp->if_collisions++; 1062 } 1063 ifp->if_collisions += TSW_NCR_GET(txstat); 1064 } 1065 1066 ifp->if_opackets++; 1067 if (sc->mtd_cdata.mtd_tx_chain[idx].sd_map->dm_nsegs != 0) { 1068 bus_dmamap_t map = 1069 sc->mtd_cdata.mtd_tx_chain[idx].sd_map; 1070 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1071 BUS_DMASYNC_POSTWRITE); 1072 bus_dmamap_unload(sc->sc_dmat, map); 1073 } 1074 if (sc->mtd_cdata.mtd_tx_chain[idx].sd_mbuf != NULL) { 1075 m_freem(sc->mtd_cdata.mtd_tx_chain[idx].sd_mbuf); 1076 sc->mtd_cdata.mtd_tx_chain[idx].sd_mbuf = NULL; 1077 } 1078 sc->mtd_cdata.mtd_tx_cnt--; 1079 idx = (idx + 1) % MTD_TX_LIST_CNT; 1080 } 1081 1082 if (cur_tx != NULL) { 1083 ifp->if_flags &= ~IFF_OACTIVE; 1084 sc->mtd_cdata.mtd_tx_cons = idx; 1085 } else 1086 if (sc->mtd_ldata->mtd_tx_list[idx].td_tsw == 1087 htole32(TSW_UNSENT)) { 1088 sc->mtd_ldata->mtd_tx_list[idx].td_tsw = 1089 htole32(TSW_OWN); 1090 ifp->if_timer = 5; 1091 CSR_WRITE_4(MTD_TXPDR, 0xffffffff); 1092 } 1093} 1094 1095struct cfdriver mtd_cd = { 1096 0, "mtd", DV_IFNET 1097}; 1098