lm78var.h revision 1.7 
1/*	$OpenBSD: lm78var.h,v 1.7 2006/12/23 17:46:39 deraadt Exp $	*/
2
3/*
4 * Copyright (c) 2005, 2006 Mark Kettenis
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/*
20 * National Semiconductor LM78/79/81 registers
21 */
22
23#define LM_POST_RAM	0x00	/* POST RAM occupies 0x00 -- 0x1f */
24#define LM_VALUE_RAM	0x20	/* Value RAM occupies 0x20 -- 0x3f */
25#define LM_FAN1		0x28	/* FAN1 reading */
26#define LM_FAN2		0x29	/* FAN2 reading */
27#define LM_FAN3		0x2a	/* FAN3 reading */
28
29#define LM_CONFIG	0x40	/* Configuration */
30#define LM_ISR1		0x41	/* Interrupt Status 1 */
31#define LM_ISR2		0x42	/* Interrupt Status 2 */
32#define LM_SMI1		0x43	/* SMI# Mask 1 */
33#define LM_SMI2		0x44	/* SMI# Mask 2 */
34#define LM_NMI1		0x45	/* NMI Mask 1 */
35#define LM_NMI2		0x46	/* NMI Mask 2 */
36#define LM_VIDFAN	0x47	/* VID/Fan Divisor */
37#define LM_SBUSADDR	0x48	/* Serial Bus Address */
38#define LM_CHIPID	0x49	/* Chip Reset/ID */
39
40/* Chip IDs */
41
42#define LM_CHIPID_LM78	0x00
43#define LM_CHIPID_LM78J	0x40
44#define LM_CHIPID_LM79	0xC0
45#define LM_CHIPID_LM81	0x80
46#define LM_CHIPID_MASK	0xfe
47
48/*
49 * Winbond registers
50 *
51 * Several models exists.  The W83781D is mostly compatible with the
52 * LM78, but has two extra temperatures.  Later models add extra
53 * voltage sensors, fans and bigger fan divisors to accomodate slow
54 * running fans.  To accomodate the extra sensors some models have
55 * different memory banks.
56 */
57
58#define WB_T23ADDR	0x4a	/* Temperature 2 and 3 Serial Bus Address */
59#define WB_PIN		0x4b	/* Pin Control */
60#define WB_BANKSEL	0x4e	/* Bank Select */
61#define WB_VENDID	0x4f	/* Vendor ID */
62
63/* Bank 0 regs */
64#define WB_BANK0_CHIPID	0x58	/* Chip ID */
65#define WB_BANK0_FAN45	0x5c	/* Fan 4/5 Divisor Control (W83791D only) */
66#define WB_BANK0_VBAT	0x5d	/* VBAT Monitor Control */
67#define WB_BANK0_FAN4	0xba	/* Fan 4 reading (W83791D only) */
68#define WB_BANK0_FAN5	0xbb	/* Fan 5 reading (W83791D only) */
69
70/* Bank 1 registers */
71#define WB_BANK1_T2H	0x50	/* Temperature 2 High Byte */
72#define WB_BANK1_T2L	0x51	/* Temperature 2 Low Byte */
73
74/* Bank 2 registers */
75#define WB_BANK2_T3H	0x50	/* Temperature 3 High Byte */
76#define WB_BANK2_T3L	0x51	/* Temperature 3 Low Byte */
77
78/* Bank 4 registers (W83782D/W83627HF and later models only) */
79#define WB_BANK4_T1OFF	0x54	/* Temperature 1 Offset */
80#define WB_BANK4_T2OFF	0x55	/* Temperature 2 Offset */
81#define WB_BANK4_T3OFF	0x56	/* Temperature 3 Offset */
82
83/* Bank 5 registers (W83782D/W83627HF and later models only) */
84#define WB_BANK5_5VSB	0x50	/* 5VSB reading */
85#define WB_BANK5_VBAT	0x51	/* VBAT reading */
86
87/* Bank selection */
88#define WB_BANKSEL_B0	0x00	/* Bank 0 */
89#define WB_BANKSEL_B1	0x01	/* Bank 1 */
90#define WB_BANKSEL_B2	0x02	/* Bank 2 */
91#define WB_BANKSEL_B3	0x03	/* Bank 3 */
92#define WB_BANKSEL_B4	0x04	/* Bank 4 */
93#define WB_BANKSEL_B5	0x05	/* Bank 5 */
94#define WB_BANKSEL_HBAC	0x80	/* Register 0x4f Hight Byte Access */
95
96/* Vendor IDs */
97#define WB_VENDID_WINBOND	0x5ca3	/* Winbond */
98#define WB_VENDID_ASUS		0x12c3	/* ASUS */
99
100/* Chip IDs */
101#define WB_CHIPID_W83781D	0x10
102#define WB_CHIPID_W83781D_2	0x11
103#define WB_CHIPID_W83627HF	0x21
104#define WB_CHIPID_AS99127F	0x31 /* Asus W83781D clone */
105#define WB_CHIPID_W83782D	0x30
106#define WB_CHIPID_W83783S	0x40
107#define WB_CHIPID_W83697HF	0x60
108#define WB_CHIPID_W83791D	0x71
109#define WB_CHIPID_W83791SD	0x72
110#define WB_CHIPID_W83792D	0x7a
111#define WB_CHIPID_W83637HF	0x80
112#define WB_CHIPID_W83627THF	0x90
113
114/* Reference voltage (mV) */
115#define WB_VREF		3600
116
117#define WB_MAX_SENSORS  19
118
119struct lm_softc;
120
121struct lm_sensor {
122	char *desc;
123	enum sensor_type type;
124	u_int8_t bank;
125	u_int8_t reg;
126	void (*refresh)(struct lm_softc *, int);
127	int rfact;
128};
129
130struct lm_softc {
131	struct device sc_dev;
132
133	struct sensor sensors[WB_MAX_SENSORS];
134	struct sensordev sensordev;
135	struct lm_sensor *lm_sensors;
136	u_int numsensors;
137	void (*refresh_sensor_data) (struct lm_softc *);
138
139	u_int8_t (*lm_readreg)(struct lm_softc *, int);
140	void (*lm_writereg)(struct lm_softc *, int, int);
141
142	u_int8_t sbusaddr;
143	u_int8_t chipid;
144};
145
146void lm_attach(struct lm_softc *);
147int lm_detach(struct lm_softc *);
148