1/* $OpenBSD: lancereg.h,v 1.3 2022/01/09 05:42:38 jsg Exp $ */ 2/* $NetBSD: lancereg.h,v 1.11 2003/11/02 11:07:45 wiz Exp $ */ 3 4/*- 5 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum and Jason R. Thorpe. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/*- 34 * Copyright (c) 1992, 1993 35 * The Regents of the University of California. All rights reserved. 36 * 37 * This code is derived from software contributed to Berkeley by 38 * Ralph Campbell and Rick Macklem. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. Neither the name of the University nor the names of its contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 * @(#)if_lereg.h 8.1 (Berkeley) 6/10/93 65 */ 66 67/* 68 * Register description for the following Advanced Micro Devices 69 * Ethernet chips: 70 * 71 * - Am7990 Local Area Network Controller for Ethernet (LANCE) 72 * (and its descendent Am79c90 C-LANCE). 73 * 74 * - Am79c900 Integrated Local Area Communications Controller (ILACC) 75 * 76 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA 77 * 78 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller 79 * for ISA 80 * 81 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip 82 * Ethernet Controller for ISA 83 * 84 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller 85 * (for VESA and 486 local busses) 86 * 87 * - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 88 * Local Bus 89 * 90 * - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 91 * for PCI Local Bus 92 * 93 * - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 94 * Ethernet Controller for PCI Local Bus 95 * 96 * - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 97 * with OnNow Support 98 * 99 * - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 100 * Ethernet Controller with Integrated PHY 101 * 102 * - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home 103 * Networking Controller. 104 * 105 * Initialization block, transmit descriptor, and receive descriptor 106 * formats are described in two separate files: 107 * 108 * 16-bit software model (LANCE) am7990reg.h 109 * 110 * 32-bit software model (ILACC) am79900reg.h 111 * 112 * Note that the vast majority of the registers described in this file 113 * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are 114 * valid on the LANCE. 115 */ 116 117#define LEBLEN 1536 /* ETHERMTU + header + CRC */ 118#define LEMINSIZE 60 /* should be 64 if mode DTCR is set */ 119 120#define LE_INITADDR(sc) (sc->sc_initaddr) 121#define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix)) 122#define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix)) 123#define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr[bix]) 124#define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr[bix]) 125 126/* 127 * The byte count fields in descriptors are in two's complement. 128 * This macro does the conversion for us on unsigned numbers. 129 */ 130#define LE_BCNT(x) (~(x) + 1) 131 132/* 133 * Control and Status Register addresses 134 */ 135#define LE_CSR0 0x0000 /* Control and status register */ 136#define LE_CSR1 0x0001 /* low address of init block */ 137#define LE_CSR2 0x0002 /* high address of init block */ 138#define LE_CSR3 0x0003 /* Bus master and control */ 139#define LE_CSR4 0x0004 /* Test and features control */ 140#define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */ 141#define LE_CSR6 0x0006 /* Rx/Tx Descriptor table length */ 142#define LE_CSR7 0x0007 /* Extended control and interrupt 2 */ 143#define LE_CSR8 0x0008 /* Logical Address Filter 0 */ 144#define LE_CSR9 0x0009 /* Logical Address Filter 1 */ 145#define LE_CSR10 0x000a /* Logical Address Filter 2 */ 146#define LE_CSR11 0x000b /* Logical Address Filter 3 */ 147#define LE_CSR12 0x000c /* Physical Address 0 */ 148#define LE_CSR13 0x000d /* Physical Address 1 */ 149#define LE_CSR14 0x000e /* Physical Address 2 */ 150#define LE_CSR15 0x000f /* Mode */ 151#define LE_CSR16 0x0010 /* Initialization Block addr lower */ 152#define LE_CSR17 0x0011 /* Initialization Block addr upper */ 153#define LE_CSR18 0x0012 /* Current Rx Buffer addr lower */ 154#define LE_CSR19 0x0013 /* Current Rx Buffer addr upper */ 155#define LE_CSR20 0x0014 /* Current Tx Buffer addr lower */ 156#define LE_CSR21 0x0015 /* Current Tx Buffer addr upper */ 157#define LE_CSR22 0x0016 /* Next Rx Buffer addr lower */ 158#define LE_CSR23 0x0017 /* Next Rx Buffer addr upper */ 159#define LE_CSR24 0x0018 /* Base addr of Rx ring lower */ 160#define LE_CSR25 0x0019 /* Base addr of Rx ring upper */ 161#define LE_CSR26 0x001a /* Next Rx Desc addr lower */ 162#define LE_CSR27 0x001b /* Next Rx Desc addr upper */ 163#define LE_CSR28 0x001c /* Current Rx Desc addr lower */ 164#define LE_CSR29 0x001d /* Current Rx Desc addr upper */ 165#define LE_CSR30 0x001e /* Base addr of Tx ring lower */ 166#define LE_CSR31 0x001f /* Base addr of Tx ring upper */ 167#define LE_CSR32 0x0020 /* Next Tx Desc addr lower */ 168#define LE_CSR33 0x0021 /* Next Tx Desc addr upper */ 169#define LE_CSR34 0x0022 /* Current Tx Desc addr lower */ 170#define LE_CSR35 0x0023 /* Current Tx Desc addr upper */ 171#define LE_CSR36 0x0024 /* Next Next Rx Desc addr lower */ 172#define LE_CSR37 0x0025 /* Next Next Rx Desc addr upper */ 173#define LE_CSR38 0x0026 /* Next Next Tx Desc addr lower */ 174#define LE_CSR39 0x0027 /* Next Next Tx Desc adddr upper */ 175#define LE_CSR40 0x0028 /* Current Rx Byte Count */ 176#define LE_CSR41 0x0029 /* Current Rx Status */ 177#define LE_CSR42 0x002a /* Current Tx Byte Count */ 178#define LE_CSR43 0x002b /* Current Tx Status */ 179#define LE_CSR44 0x002c /* Next Rx Byte Count */ 180#define LE_CSR45 0x002d /* Next Rx Status */ 181#define LE_CSR46 0x002e /* Tx Poll Time Counter */ 182#define LE_CSR47 0x002f /* Tx Polling Interval */ 183#define LE_CSR48 0x0030 /* Rx Poll Time Counter */ 184#define LE_CSR49 0x0031 /* Rx Polling Interval */ 185#define LE_CSR58 0x003a /* Software Style */ 186#define LE_CSR60 0x003c /* Previous Tx Desc addr lower */ 187#define LE_CSR61 0x003d /* Previous Tx Desc addr upper */ 188#define LE_CSR62 0x003e /* Previous Tx Byte Count */ 189#define LE_CSR63 0x003f /* Previous Tx Status */ 190#define LE_CSR64 0x0040 /* Next Tx Buffer addr lower */ 191#define LE_CSR65 0x0041 /* Next Tx Buffer addr upper */ 192#define LE_CSR66 0x0042 /* Next Tx Byte Count */ 193#define LE_CSR67 0x0043 /* Next Tx Status */ 194#define LE_CSR72 0x0048 /* Receive Ring Counter */ 195#define LE_CSR74 0x004a /* Transmit Ring Counter */ 196#define LE_CSR76 0x004c /* Receive Ring Length */ 197#define LE_CSR78 0x004e /* Transmit Ring Length */ 198#define LE_CSR80 0x0050 /* DMA Transfer Counter and FIFO 199 Threshold Control */ 200#define LE_CSR82 0x0052 /* Tx Desc addr Pointer lower */ 201#define LE_CSR84 0x0054 /* DMA addr register lower */ 202#define LE_CSR85 0x0055 /* DMA addr register upper */ 203#define LE_CSR86 0x0056 /* Buffer Byte Counter */ 204#define LE_CSR88 0x0058 /* Chip ID Register lower */ 205#define LE_CSR89 0x0059 /* Chip ID Register upper */ 206#define LE_CSR92 0x005c /* Ring Length Conversion */ 207#define LE_CSR100 0x0064 /* Bus Timeout */ 208#define LE_CSR112 0x0070 /* Missed Frame Count */ 209#define LE_CSR114 0x0072 /* Receive Collision Count */ 210#define LE_CSR116 0x0074 /* OnNow Power Mode Register */ 211#define LE_CSR122 0x007a /* Advanced Feature Control */ 212#define LE_CSR124 0x007c /* Test Register 1 */ 213#define LE_CSR125 0x007d /* MAC Enhanced Configuration Control */ 214 215/* 216 * Bus Configuration Register addresses 217 */ 218#define LE_BCR0 0x0000 /* Master Mode Read Active */ 219#define LE_BCR1 0x0001 /* Master Mode Write Active */ 220#define LE_BCR2 0x0002 /* Misc. Configuration */ 221#define LE_BCR4 0x0004 /* LED0 Status */ 222#define LE_BCR5 0x0005 /* LED1 Status */ 223#define LE_BCR6 0x0006 /* LED2 Status */ 224#define LE_BCR7 0x0007 /* LED3 Status */ 225#define LE_BCR9 0x0009 /* Full-duplex Control */ 226#define LE_BCR16 0x0010 /* I/O Base Address lower */ 227#define LE_BCR17 0x0011 /* I/O Base Address upper */ 228#define LE_BCR18 0x0012 /* Burst and Bus Control Register */ 229#define LE_BCR19 0x0013 /* EEPROM Control and Status */ 230#define LE_BCR20 0x0014 /* Software Style */ 231#define LE_BCR22 0x0016 /* PCI Latency Register */ 232#define LE_BCR23 0x0017 /* PCI Subsystem Vendor ID */ 233#define LE_BCR24 0x0018 /* PCI Subsystem ID */ 234#define LE_BCR25 0x0019 /* SRAM Size Register */ 235#define LE_BCR26 0x001a /* SRAM Boundary Register */ 236#define LE_BCR27 0x001b /* SRAM Interface Control Register */ 237#define LE_BCR28 0x001c /* Exp. Bus Port Addr lower */ 238#define LE_BCR29 0x001d /* Exp. Bus Port Addr upper */ 239#define LE_BCR30 0x001e /* Exp. Bus Data Port */ 240#define LE_BCR31 0x001f /* Software Timer Register */ 241#define LE_BCR32 0x0020 /* PHY Control and Status Register */ 242#define LE_BCR33 0x0021 /* PHY Address Register */ 243#define LE_BCR34 0x0022 /* PHY Management Data Register */ 244#define LE_BCR35 0x0023 /* PCI Vendor ID Register */ 245#define LE_BCR36 0x0024 /* PCI Power Management Cap. Alias */ 246#define LE_BCR37 0x0025 /* PCI DATA0 Alias */ 247#define LE_BCR38 0x0026 /* PCI DATA1 Alias */ 248#define LE_BCR39 0x0027 /* PCI DATA2 Alias */ 249#define LE_BCR40 0x0028 /* PCI DATA3 Alias */ 250#define LE_BCR41 0x0029 /* PCI DATA4 Alias */ 251#define LE_BCR42 0x002a /* PCI DATA5 Alias */ 252#define LE_BCR43 0x002b /* PCI DATA6 Alias */ 253#define LE_BCR44 0x002c /* PCI DATA7 Alias */ 254#define LE_BCR45 0x002d /* OnNow Pattern Matching 1 */ 255#define LE_BCR46 0x002e /* OnNow Pattern Matching 2 */ 256#define LE_BCR47 0x002f /* OnNow Pattern Matching 3 */ 257#define LE_BCR48 0x0030 /* LED4 Status */ 258#define LE_BCR49 0x0031 /* PHY Select */ 259 260/* Control and status register 0 (csr0) */ 261#define LE_C0_ERR 0x8000 /* error summary */ 262#define LE_C0_BABL 0x4000 /* transmitter timeout error */ 263#define LE_C0_CERR 0x2000 /* collision */ 264#define LE_C0_MISS 0x1000 /* missed a packet */ 265#define LE_C0_MERR 0x0800 /* memory error */ 266#define LE_C0_RINT 0x0400 /* receiver interrupt */ 267#define LE_C0_TINT 0x0200 /* transmitter interrupt */ 268#define LE_C0_IDON 0x0100 /* initialization done */ 269#define LE_C0_INTR 0x0080 /* interrupt condition */ 270#define LE_C0_INEA 0x0040 /* interrupt enable */ 271#define LE_C0_RXON 0x0020 /* receiver on */ 272#define LE_C0_TXON 0x0010 /* transmitter on */ 273#define LE_C0_TDMD 0x0008 /* transmit demand */ 274#define LE_C0_STOP 0x0004 /* disable all external activity */ 275#define LE_C0_STRT 0x0002 /* enable external activity */ 276#define LE_C0_INIT 0x0001 /* begin initialization */ 277 278#define LE_C0_BITS \ 279 "\20\20ERR\17BABL\16CERR\15MISS\14MERR\13RINT\ 280\12TINT\11IDON\10INTR\07INEA\06RXON\05TXON\04TDMD\03STOP\02STRT\01INIT" 281 282/* Control and status register 3 (csr3) */ 283#define LE_C3_BABLM 0x4000 /* babble mask */ 284#define LE_C3_MISSM 0x1000 /* missed frame mask */ 285#define LE_C3_MERRM 0x0800 /* memory error mask */ 286#define LE_C3_RINTM 0x0400 /* receive interrupt mask */ 287#define LE_C3_TINTM 0x0200 /* transmit interrupt mask */ 288#define LE_C3_IDONM 0x0100 /* initialization done mask */ 289#define LE_C3_DXSUFLO 0x0040 /* disable tx stop on underflow */ 290#define LE_C3_LAPPEN 0x0020 /* look ahead packet processing enbl */ 291#define LE_C3_DXMT2PD 0x0010 /* disable tx two part deferral */ 292#define LE_C3_EMBA 0x0008 /* enable modified backoff algorithm */ 293#define LE_C3_BSWP 0x0004 /* byte swap */ 294#define LE_C3_ACON 0x0002 /* ALE control, eh? */ 295#define LE_C3_BCON 0x0001 /* byte control */ 296 297/* Control and status register 4 (csr4) */ 298#define LE_C4_EN124 0x8000 /* enable CSR124 */ 299#define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */ 300#define LE_C4_TIMER 0x2000 /* enable bus activity timer */ 301#define LE_C4_TXDPOLL 0x1000 /* disable transmit polling */ 302#define LE_C4_APAD_XMT 0x0800 /* auto pad transmit */ 303#define LE_C4_ASTRP_RCV 0x0400 /* auto strip receive */ 304#define LE_C4_MFCO 0x0200 /* missed frame counter overflow */ 305#define LE_C4_MFCOM 0x0100 /* missed frame counter overflow mask */ 306#define LE_C4_UINTCMD 0x0080 /* user interrupt command */ 307#define LE_C4_UINT 0x0040 /* user interrupt */ 308#define LE_C4_RCVCCO 0x0020 /* receive collision counter overflow */ 309#define LE_C4_RCVCCOM 0x0010 /* receive collision counter overflow 310 mask */ 311#define LE_C4_TXSTRT 0x0008 /* transmit start status */ 312#define LE_C4_TXSTRTM 0x0004 /* transmit start mask */ 313 314/* Control and status register 5 (csr5) */ 315#define LE_C5_TOKINTD 0x8000 /* transmit ok interrupt disable */ 316#define LE_C5_LTINTEN 0x4000 /* last transmit interrupt enable */ 317#define LE_C5_SINT 0x0800 /* system interrupt */ 318#define LE_C5_SINTE 0x0400 /* system interrupt enable */ 319#define LE_C5_EXDINT 0x0080 /* excessive deferral interrupt */ 320#define LE_C5_EXDINTE 0x0040 /* excessive deferral interrupt enbl */ 321#define LE_C5_MPPLBA 0x0020 /* magic packet physical logical 322 broadcast accept */ 323#define LE_C5_MPINT 0x0010 /* magic packet interrupt */ 324#define LE_C5_MPINTE 0x0008 /* magic packet interrupt enable */ 325#define LE_C5_MPEN 0x0004 /* magic packet enable */ 326#define LE_C5_MPMODE 0x0002 /* magic packet mode */ 327#define LE_C5_SPND 0x0001 /* suspend */ 328 329/* Control and status register 6 (csr6) */ 330#define LE_C6_TLEN 0xf000 /* TLEN from init block */ 331#define LE_C6_RLEN 0x0f00 /* RLEN from init block */ 332 333/* Control and status register 7 (csr7) */ 334#define LE_C7_FASTSPNDE 0x8000 /* fast suspend enable */ 335#define LE_C7_RDMD 0x2000 /* receive demand */ 336#define LE_C7_RDXPOLL 0x1000 /* receive disable polling */ 337#define LE_C7_STINT 0x0800 /* software timer interrupt */ 338#define LE_C7_STINTE 0x0400 /* software timer interrupt enable */ 339#define LE_C7_MREINT 0x0200 /* PHY management read error intr */ 340#define LE_C7_MREINTE 0x0100 /* PHY management read error intr 341 enable */ 342#define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */ 343#define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr 344 enable */ 345#define LE_C7_MCCINT 0x0020 /* PHY management command complete 346 interrupt */ 347#define LE_C7_MCCINTE 0x0010 /* PHY management command complete 348 interrupt enable */ 349#define LE_C7_MCCIINT 0x0008 /* PHY management command complete 350 internal interrupt */ 351#define LE_C7_MCCIINTE 0x0004 /* PHY management command complete 352 internal interrupt enable */ 353#define LE_C7_MIIPDTINT 0x0002 /* PHY management detect transition 354 interrupt */ 355#define LE_C7_MIIPDTINTE 0x0001 /* PHY management detect transition 356 interrupt enable */ 357 358/* Control and status register 15 (csr15) */ 359#define LE_C15_PROM 0x8000 /* promiscuous mode */ 360#define LE_C15_DRCVBC 0x4000 /* disable Rx of broadcast */ 361#define LE_C15_DRCVPA 0x2000 /* disable Rx of physical address */ 362#define LE_C15_DLNKTST 0x1000 /* disable link status */ 363#define LE_C15_DAPC 0x0800 /* disable auto-polarity correction */ 364#define LE_C15_MENDECL 0x0400 /* MENDEC Loopback mode */ 365#define LE_C15_LRT 0x0200 /* low receive threshold (TMAU) */ 366#define LE_C15_TSEL 0x0200 /* transmit mode select (AUI) */ 367#define LE_C15_PORTSEL(x) ((x) << 7) /* port select */ 368#define LE_C15_INTL 0x0040 /* internal loopback */ 369#define LE_C15_DRTY 0x0020 /* disable retry */ 370#define LE_C15_FCOLL 0x0010 /* force collision */ 371#define LE_C15_DXMTFCS 0x0008 /* disable Tx FCS (ADD_FCS overrides) */ 372#define LE_C15_LOOP 0x0004 /* loopback enable */ 373#define LE_C15_DTX 0x0002 /* disable transmit */ 374#define LE_C15_DRX 0x0001 /* disable receiver */ 375 376#define PORTSEL_AUI 0 377#define PORTSEL_10T 1 378#define PORTSEL_GPSI 2 379#define PORTSEL_MII 3 380#define PORTSEL_MASK 3 381 382/* control and status register 80 (csr80) */ 383#define LE_C80_RCVFW(x) ((x) << 12) /* Receive FIFO Watermark */ 384#define LE_C80_RCVFW_MAX 3 385#define LE_C80_XMTSP(x) ((x) << 10) /* Transmit Start Point */ 386#define LE_C80_XMTSP_MAX 3 387#define LE_C80_XMTFW(x) ((x) << 8) /* Transmit FIFO Watermark */ 388#define LE_C80_XMTFW_MAX 3 389#define LE_C80_DMATC 0x00ff /* DMA transfer counter */ 390 391/* control and status register 116 (csr116) */ 392#define LE_C116_PME_EN_OVR 0x0400 /* PME_EN overwrite */ 393#define LE_C116_LCDET 0x0200 /* link change detected */ 394#define LE_C116_LCMODE 0x0100 /* link change wakeup mode */ 395#define LE_C116_PMAT 0x0080 /* pattern matched */ 396#define LE_C116_EMPPLBA 0x0040 /* magic packet physical logical 397 broadcast accept */ 398#define LE_C116_MPMAT 0x0020 /* magic packet match */ 399#define LE_C116_MPPEN 0x0010 /* magic packet pin enable */ 400#define LE_C116_RST_POL 0x0001 /* PHY_RST pin polarity */ 401 402/* control and status register 122 (csr122) */ 403#define LE_C122_RCVALGN 0x0001 /* receive packet align */ 404 405/* control and status register 124 (csr124) */ 406#define LE_C124_RPA 0x0008 /* runt packet accept */ 407 408/* control and status register 125 (csr125) */ 409#define LE_C125_IPG 0xff00 /* inter-packet gap */ 410#define LE_C125_IFS1 0x00ff /* inter-frame spacing part 1 */ 411 412/* bus configuration register 0 (bcr0) */ 413#define LE_B0_MSRDA 0xffff /* reserved locations */ 414 415/* bus configuration register 1 (bcr1) */ 416#define LE_B1_MSWRA 0xffff /* reserved locations */ 417 418/* bus configuration register 2 (bcr2) */ 419#define LE_B2_PHYSSELEN 0x2000 /* enable writes to BCR18[4:3] */ 420#define LE_B2_LEDPE 0x1000 /* LED program enable */ 421#define LE_B2_APROMWE 0x0100 /* Address PROM Write Enable */ 422#define LE_B2_INTLEVEL 0x0080 /* 1 == edge triggered */ 423#define LE_B2_DXCVRCTL 0x0020 /* DXCVR control */ 424#define LE_B2_DXCVRPOL 0x0010 /* DXCVR polarity */ 425#define LE_B2_EADISEL 0x0008 /* EADI select */ 426#define LE_B2_AWAKE 0x0004 /* power saving mode select */ 427#define LE_B2_ASEL 0x0002 /* auto-select PORTSEL */ 428#define LE_B2_XMAUSEL 0x0001 /* reserved location */ 429 430/* bus configuration register 4 (bcr4) */ 431/* bus configuration register 5 (bcr5) */ 432/* bus configuration register 6 (bcr6) */ 433/* bus configuration register 7 (bcr7) */ 434/* bus configuration register 48 (bcr48) */ 435#define LE_B4_LEDOUT 0x8000 /* LED output active */ 436#define LE_B4_LEDPOL 0x4000 /* LED polarity */ 437#define LE_B4_LEDDIS 0x2000 /* LED disable */ 438#define LE_B4_100E 0x1000 /* 100Mb/s enable */ 439#define LE_B4_MPSE 0x0200 /* magic packet status enable */ 440#define LE_B4_FDLSE 0x0100 /* full-duplex link status enable */ 441#define LE_B4_PSE 0x0080 /* pulse stretcher enable */ 442#define LE_B4_LNKSE 0x0040 /* link status enable */ 443#define LE_B4_RCVME 0x0020 /* receive match status enable */ 444#define LE_B4_XMTE 0x0010 /* transmit status enable */ 445#define LE_B4_POWER 0x0008 /* power enable */ 446#define LE_B4_RCVE 0x0004 /* receive status enable */ 447#define LE_B4_SPEED 0x0002 /* high speed enable */ 448#define LE_B4_COLE 0x0001 /* collision status enable */ 449 450/* bus configuration register 9 (bcr9) */ 451#define LE_B9_FDRPAD 0x0004 /* full-duplex runt packet accept 452 disable */ 453#define LE_B9_AUIFD 0x0002 /* AUI full-duplex */ 454#define LE_B9_FDEN 0x0001 /* full-duplex enable */ 455 456/* bus configuration register 18 (bcr18) */ 457#define LE_B18_ROMTMG 0xf000 /* expansion rom timing */ 458#define LE_B18_NOUFLO 0x0800 /* no underflow on transmit */ 459#define LE_B18_MEMCMD 0x0200 /* memory read multiple enable */ 460#define LE_B18_EXTREQ 0x0100 /* extended request */ 461#define LE_B18_DWIO 0x0080 /* double-word I/O */ 462#define LE_B18_BREADE 0x0040 /* burst read enable */ 463#define LE_B18_BWRITE 0x0020 /* burst write enable */ 464#define LE_B18_PHYSEL1 0x0010 /* PHYSEL 1 */ 465#define LE_B18_PHYSEL0 0x0008 /* PHYSEL 0 */ 466 /* 00 ex ROM/Flash */ 467 /* 01 EADI/MII snoop */ 468 /* 10 reserved */ 469 /* 11 reserved */ 470#define LE_B18_LINBC 0x0007 /* reserved locations */ 471 472/* bus configuration register 19 (bcr19) */ 473#define LE_B19_PVALID 0x8000 /* EEPROM status valid */ 474#define LE_B19_PREAD 0x4000 /* EEPROM read command */ 475#define LE_B19_EEDET 0x2000 /* EEPROM detect */ 476#define LE_B19_EEN 0x0010 /* EEPROM port enable */ 477#define LE_B19_ECS 0x0004 /* EEPROM chip select */ 478#define LE_B19_ESK 0x0002 /* EEPROM serial clock */ 479#define LE_B19_EDI 0x0001 /* EEPROM data in */ 480#define LE_B19_EDO 0x0001 /* EEPROM data out */ 481 482/* bus configuration register 20 (bcr20) */ 483#define LE_B20_APERREN 0x0400 /* Advanced parity error handling */ 484#define LE_B20_CSRPCNET 0x0200 /* PCnet-style CSRs (0 = ILACC) */ 485#define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */ 486#define LE_B20_SSTYLE 0x0007 /* Software Style */ 487#define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */ 488#define LE_B20_SSTYPE_ILACC 1 /* ILACC (32-bit) */ 489#define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */ 490#define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI II (32-bit) */ 491 492/* bus configuration register 25 (bcr25) */ 493#define LE_B25_SRAM_SIZE 0x00ff /* SRAM size */ 494 495/* bus configuration register 26 (bcr26) */ 496#define LE_B26_SRAM_BND 0x00ff /* SRAM boundary */ 497 498/* bus configuration register 27 (bcr27) */ 499#define LE_B27_PTRTST 0x8000 /* reserved for manuf. tests */ 500#define LE_B27_LOLATRX 0x4000 /* low latency receive */ 501#define LE_B27_EBCS 0x0038 /* expansion bus clock source */ 502 /* 000 CLK pin */ 503 /* 001 time base clock */ 504 /* 010 EBCLK pin */ 505 /* 011 reserved */ 506 /* 1xx reserved */ 507#define LE_B27_CLK_FAC 0x0007 /* clock factor */ 508 /* 000 1 */ 509 /* 001 1/2 */ 510 /* 010 reserved */ 511 /* 011 1/4 */ 512 /* 1xx reserved */ 513 514/* bus configuration register 28 (bcr28) */ 515#define LE_B28_EADDRL 0xffff /* expansion port address lower */ 516 517/* bus configuration register 29 (bcr29) */ 518#define LE_B29_FLASH 0x8000 /* flash access */ 519#define LE_B29_LAAINC 0x4000 /* lower address auto increment */ 520#define LE_B29_EPADDRU 0x0007 /* expansion port address upper */ 521 522/* bus configuration register 30 (bcr30) */ 523#define LE_B30_EBDATA 0xffff /* expansion bus data port */ 524 525/* bus configuration register 31 (bcr31) */ 526#define LE_B31_STVAL 0xffff /* software timer value */ 527 528/* bus configuration register 32 (bcr32) */ 529#define LE_B32_ANTST 0x8000 /* reserved for manuf. tests */ 530#define LE_B32_MIIPD 0x4000 /* MII PHY Detect (manuf. tests) */ 531#define LE_B32_FMDC 0x3000 /* fast management data clock */ 532#define LE_B32_APEP 0x0800 /* auto-poll PHY */ 533#define LE_B32_APDW 0x0700 /* auto-poll dwell time */ 534#define LE_B32_DANAS 0x0080 /* disable autonegotiation */ 535#define LE_B32_XPHYRST 0x0040 /* PHY reset */ 536#define LE_B32_XPHYANE 0x0020 /* PHY autonegotiation enable */ 537#define LE_B32_XPHYFD 0x0010 /* PHY full-duplex */ 538#define LE_B32_XPHYSP 0x0008 /* PHY speed */ 539#define LE_B32_MIIILP 0x0002 /* MII internal loopback */ 540 541/* bus configuration register 33 (bcr33) */ 542#define LE_B33_SHADOW 0x8000 /* shadow enable */ 543#define LE_B33_MII_SEL 0x4000 /* MII selected */ 544#define LE_B33_ACOMP 0x2000 /* internal PHY autonegotiation comp */ 545#define LE_B33_LINK 0x1000 /* link status */ 546#define LE_B33_FDX 0x0800 /* full-duplex */ 547#define LE_B33_SPEED 0x0400 /* 1 == high speed */ 548#define LE_B33_PHYAD 0x03e0 /* PHY address */ 549#define PHYAD_SHIFT 5 550#define LE_B33_REGAD 0x001f /* register address */ 551 552/* bus configuration register 34 (bcr34) */ 553#define LE_B34_MIIMD 0xffff /* MII data */ 554 555/* bus configuration register 49 (bcr49) */ 556#define LE_B49_PCNET 0x8000 /* PCnet mode - Must Be One */ 557#define LE_B49_PHYSEL_D 0x0300 /* PHY_SEL_Default */ 558#define LE_B49_PHYSEL_L 0x0010 /* PHY_SEL_Lock */ 559#define LE_B49_PHYSEL 0x0003 /* PHYSEL */ 560 /* 00 10baseT PHY */ 561 /* 01 HomePNA PYY */ 562 /* 10 external PHY */ 563 /* 11 reserved */ 564 565/* Initialization block (mode) */ 566#define LE_MODE_PROM 0x8000 /* promiscuous mode */ 567/* 0x7f80 reserved, must be zero */ 568/* 0x4000 - 0x0080 are not available on LANCE 7990 */ 569#define LE_MODE_DRCVBC 0x4000 /* disable receive broadcast */ 570#define LE_MODE_DRCVPA 0x2000 /* disable physical address detection */ 571#define LE_MODE_DLNKTST 0x1000 /* disable link status */ 572#define LE_MODE_DAPC 0x0800 /* disable automatic polarity correction */ 573#define LE_MODE_MENDECL 0x0400 /* MENDEC loopback mode */ 574#define LE_MODE_LRTTSEL 0x0200 /* lower receive threshold / 575 transmit mode selection */ 576#define LE_MODE_PSEL1 0x0100 /* port selection bit1 */ 577#define LE_MODE_PSEL0 0x0080 /* port selection bit0 */ 578#define LE_MODE_INTL 0x0040 /* internal loopback */ 579#define LE_MODE_DRTY 0x0020 /* disable retry */ 580#define LE_MODE_COLL 0x0010 /* force a collision */ 581#define LE_MODE_DTCR 0x0008 /* disable transmit CRC */ 582#define LE_MODE_LOOP 0x0004 /* loopback mode */ 583#define LE_MODE_DTX 0x0002 /* disable transmitter */ 584#define LE_MODE_DRX 0x0001 /* disable receiver */ 585#define LE_MODE_NORMAL 0 /* none of the above */ 586 587/* 588 * Chip ID (CSR88 IDL, CSR89 IDU) values for various AMD PCnet parts. 589 */ 590#define CHIPID_MANFID(x) (((x) >> 1) & 0x3ff) 591#define CHIPID_PARTID(x) (((x) >> 12) & 0xffff) 592#define CHIPID_VER(x) (((x) >> 28) & 0x7) 593 594#define PARTID_Am79c960 0x0003 595#define PARTID_Am79c961 0x2260 596#define PARTID_Am79c961A 0x2261 597#define PARTID_Am79c965 0x2430 /* yes, these... */ 598#define PARTID_Am79c970 0x2430 /* ...are the same */ 599#define PARTID_Am79c970A 0x2621 600#define PARTID_Am79c971 0x2623 601#define PARTID_Am79c972 0x2624 602#define PARTID_Am79c973 0x2625 603#define PARTID_Am79c978 0x2626 604#define PARTID_Am79c975 0x2627 605#define PARTID_Am79c976 0x2628 606