dwqevar.h revision 1.2 
1/*	$OpenBSD: dwqevar.h,v 1.2 2023/03/19 09:46:40 kettenis Exp $	*/
2/*
3 * Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org>
4 * Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19struct dwqe_buf {
20	bus_dmamap_t	tb_map;
21	struct mbuf	*tb_m;
22};
23
24#define DWQE_NTXDESC	256
25#define DWQE_NTXSEGS	16
26
27#define DWQE_NRXDESC	256
28
29struct dwqe_dmamem {
30	bus_dmamap_t		tdm_map;
31	bus_dma_segment_t	tdm_seg;
32	size_t			tdm_size;
33	caddr_t			tdm_kva;
34};
35#define DWQE_DMA_MAP(_tdm)	((_tdm)->tdm_map)
36#define DWQE_DMA_LEN(_tdm)	((_tdm)->tdm_size)
37#define DWQE_DMA_DVA(_tdm)	((_tdm)->tdm_map->dm_segs[0].ds_addr)
38#define DWQE_DMA_KVA(_tdm)	((void *)(_tdm)->tdm_kva)
39
40struct dwqe_softc {
41	struct device		sc_dev;
42	int			sc_node;
43	bus_space_tag_t		sc_iot;
44	bus_space_handle_t	sc_ioh;
45	bus_dma_tag_t		sc_dmat;
46	void			*sc_ih;
47
48	struct arpcom		sc_ac;
49#define sc_lladdr	sc_ac.ac_enaddr
50	struct mii_data		sc_mii;
51#define sc_media	sc_mii.mii_media
52	int			sc_link;
53	int			sc_phyloc;
54
55	struct dwqe_dmamem	*sc_txring;
56	struct dwqe_buf		*sc_txbuf;
57	struct dwqe_desc	*sc_txdesc;
58	int			sc_tx_prod;
59	int			sc_tx_cons;
60
61	struct dwqe_dmamem	*sc_rxring;
62	struct dwqe_buf		*sc_rxbuf;
63	struct dwqe_desc	*sc_rxdesc;
64	int			sc_rx_prod;
65	struct if_rxring	sc_rx_ring;
66	int			sc_rx_cons;
67
68	struct timeout		sc_tick;
69	struct timeout		sc_rxto;
70	struct task		sc_statchg_task;
71
72	uint32_t		sc_clk;
73
74	bus_size_t		sc_clk_sel;
75	uint32_t		sc_clk_sel_125;
76	uint32_t		sc_clk_sel_25;
77	uint32_t		sc_clk_sel_2_5;
78
79	int			sc_gmac_id;
80	int			sc_hw_feature[4];
81
82	int			sc_force_thresh_dma_mode;
83	int			sc_fixed_burst;
84	int			sc_mixed_burst;
85	int			sc_aal;
86	int			sc_8xpbl;
87	int			sc_pbl;
88	int			sc_txpbl;
89	int			sc_rxpbl;
90	int			sc_axi_config;
91	int			sc_lpi_en;
92	int			sc_xit_frm;
93	int			sc_wr_osr_lmt;
94	int			sc_rd_osr_lmt;
95
96	uint32_t		sc_blen[7];
97};
98
99#define DEVNAME(_s)	((_s)->sc_dev.dv_xname)
100
101int	dwqe_attach(struct dwqe_softc *);
102void	dwqe_reset(struct dwqe_softc *);
103int	dwqe_intr(void *);
104uint32_t dwqe_read(struct dwqe_softc *, bus_addr_t);
105void	dwqe_write(struct dwqe_softc *, bus_addr_t, uint32_t);
106void	dwqe_lladdr_read(struct dwqe_softc *, uint8_t *);
107void	dwqe_lladdr_write(struct dwqe_softc *);
108void	dwqe_mii_statchg(struct device *);
109