atwreg.h revision 1.6
1/* $OpenBSD: atwreg.h,v 1.6 2009/08/16 17:24:04 jsg Exp $ */ 2/* $NetBSD: atwreg.h,v 1.10 2004/07/23 05:01:29 dyoung Exp $ */ 3 4/* 5 * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32/* glossary */ 33 34/* DTIM Delivery Traffic Indication Map, sent by AP 35 * ATIM Ad Hoc Traffic Indication Map 36 * TU 1024 microseconds 37 * TSF time synchronization function 38 * TBTT target beacon transmission time 39 * DIFS distributed inter-frame space 40 * SIFS short inter-frame space 41 * EIFS extended inter-frame space 42 */ 43 44/* Macros for bit twiddling. */ 45 46#ifndef _BIT_TWIDDLE 47#define _BIT_TWIDDLE 48/* nth bit, BIT(0) == 0x1. */ 49#define BIT(n) (((n) == 32) ? 0 : ((u_int32_t) 1 << (n))) 50 51/* bits m through n, m < n. */ 52#define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1)) 53 54/* find least significant bit that is set */ 55#define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x)) 56 57/* for x a power of two and p a non-negative integer, is x a greater power than 2**p? */ 58#define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0) 59 60#define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0) 61 62#define MASK_TO_SHIFT4(m) \ 63 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \ 64 ? 2 + MASK_TO_SHIFT2((m) >> 2) \ 65 : MASK_TO_SHIFT2((m))) 66 67#define MASK_TO_SHIFT8(m) \ 68 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \ 69 ? 4 + MASK_TO_SHIFT4((m) >> 4) \ 70 : MASK_TO_SHIFT4((m))) 71 72#define MASK_TO_SHIFT16(m) \ 73 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \ 74 ? 8 + MASK_TO_SHIFT8((m) >> 8) \ 75 : MASK_TO_SHIFT8((m))) 76 77#define MASK_TO_SHIFT(m) \ 78 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \ 79 ? 16 + MASK_TO_SHIFT16((m) >> 16) \ 80 : MASK_TO_SHIFT16((m))) 81 82#define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask)) 83#define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask)) 84#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask)) 85#define PRESHIFT(m) MASK_AND_RSHIFT((m), (m)) 86 87#endif /* _BIT_TWIDDLE */ 88 89/* ADM8211 Host Control and Status Registers */ 90 91#define ATW_PAR 0x00 /* PCI access */ 92#define ATW_FRCTL 0x04 /* Frame control */ 93#define ATW_TDR 0x08 /* Transmit demand */ 94#define ATW_WTDP 0x0C /* Current transmit descriptor pointer */ 95#define ATW_RDR 0x10 /* Receive demand */ 96#define ATW_WRDP 0x14 /* Current receive descriptor pointer */ 97#define ATW_RDB 0x18 /* Receive descriptor base address */ 98#define ATW_CSR3A 0x1C /* Unused (on ADM8211A) */ 99#define ATW_C_TDBH 0x1C /* Transmit descriptor base address, 100 * high-priority packet 101 */ 102#define ATW_TDBD 0x20 /* Transmit descriptor base address, DCF */ 103#define ATW_TDBP 0x24 /* Transmit descriptor base address, PCF */ 104#define ATW_STSR 0x28 /* Status */ 105#define ATW_CSR5A 0x2C /* Unused */ 106#define ATW_C_TDBB 0x2C /* Transmit descriptor base address, buffered 107 * broadcast/multicast packet 108 */ 109#define ATW_NAR 0x30 /* Network access */ 110#define ATW_CSR6A 0x34 /* Unused */ 111#define ATW_IER 0x38 /* Interrupt enable */ 112#define ATW_CSR7A 0x3C 113#define ATW_LPC 0x40 /* Lost packet counter */ 114#define ATW_TEST1 0x44 /* Test register 1 */ 115#define ATW_SPR 0x48 /* Serial port */ 116#define ATW_TEST0 0x4C /* Test register 0 */ 117#define ATW_WCSR 0x50 /* Wake-up control/status */ 118#define ATW_WPDR 0x54 /* Wake-up pattern data */ 119#define ATW_GPTMR 0x58 /* General purpose timer */ 120#define ATW_GPIO 0x5C /* GPIO[5:0] configuration and control */ 121#define ATW_BBPCTL 0x60 /* BBP control port */ 122#define ATW_SYNCTL 0x64 /* synthesizer control port */ 123#define ATW_PLCPHD 0x68 /* PLCP header setting */ 124#define ATW_MMIWADDR 0x6C /* MMI write address */ 125#define ATW_MMIRADDR1 0x70 /* MMI read address 1 */ 126#define ATW_MMIRADDR2 0x74 /* MMI read address 2 */ 127#define ATW_TXBR 0x78 /* Transmit burst counter */ 128#define ATW_CSR15A 0x7C /* Unused */ 129#define ATW_ALCSTAT 0x80 /* ALC statistics */ 130#define ATW_TOFS2 0x84 /* Timing offset parameter 2, 16b */ 131#define ATW_CMDR 0x88 /* Command */ 132#define ATW_PCIC 0x8C /* PCI bus performance counter */ 133#define ATW_PMCSR 0x90 /* Power management command and status */ 134#define ATW_PAR0 0x94 /* Local MAC address register 0, 32b */ 135#define ATW_PAR1 0x98 /* Local MAC address register 1, 16b */ 136#define ATW_MAR0 0x9C /* Multicast address hash table register 0 */ 137#define ATW_MAR1 0xA0 /* Multicast address hash table register 1 */ 138#define ATW_ATIMDA0 0xA4 /* Ad Hoc Traffic Indication Map (ATIM) 139 * frame DA, byte[3:0] 140 */ 141#define ATW_ABDA1 0xA8 /* BSSID address byte[5:4]; 142 * ATIM frame DA byte[5:4] 143 */ 144#define ATW_BSSID0 0xAC /* BSSID address byte[3:0] */ 145#define ATW_TXLMT 0xB0 /* WLAN retry limit, 8b; 146 * Max TX MSDU lifetime, 16b 147 */ 148#define ATW_MIBCNT 0xB4 /* RTS/ACK/FCS MIB count, 32b */ 149#define ATW_BCNT 0xB8 /* Beacon transmission time, 32b */ 150#define ATW_TSFTH 0xBC /* TSFT[63:32], 32b */ 151#define ATW_TSC 0xC0 /* TSFT[39:32] down count value */ 152#define ATW_SYNRF 0xC4 /* SYN RF IF direct control */ 153#define ATW_BPLI 0xC8 /* Beacon interval, 16b. 154 * STA listen interval, 16b. 155 */ 156#define ATW_CAP0 0xCC /* Current channel, 4b. RCVDTIM, 1b. */ 157#define ATW_CAP1 0xD0 /* Capability information, 16b. 158 * ATIM window, 1b. 159 */ 160#define ATW_RMD 0xD4 /* RX max reception duration, 16b */ 161#define ATW_CFPP 0xD8 /* CFP parameter, 32b */ 162#define ATW_TOFS0 0xDC /* Timing offset parameter 0, 28b */ 163#define ATW_TOFS1 0xE0 /* Timing offset parameter 1, 24b */ 164#define ATW_IFST 0xE4 /* IFS timing parameter 1, 32b */ 165#define ATW_RSPT 0xE8 /* Response time, 24b */ 166#define ATW_TSFTL 0xEC /* TSFT[31:0], 32b */ 167#define ATW_WEPCTL 0xF0 /* WEP control */ 168#define ATW_WESK 0xF4 /* Write entry for shared/individual key */ 169#define ATW_WEPCNT 0xF8 /* WEP count */ 170#define ATW_MACTEST 0xFC 171 172#define ATW_FER 0x100 /* Function event */ 173#define ATW_FEMR 0x104 /* Function event mask */ 174#define ATW_FPSR 0x108 /* Function present state */ 175#define ATW_FFER 0x10C /* Function force event */ 176 177 178#define ATW_PAR_MWIE BIT(24) /* memory write and invalidate 179 * enable 180 */ 181#define ATW_PAR_MRLE BIT(23) /* memory read line enable */ 182#define ATW_PAR_MRME BIT(21) /* memory read multiple 183 * enable 184 */ 185#define ATW_PAR_RAP_MASK 0x60000 /* receive auto-polling in 186 * receive suspended state 187 */ 188#define ATW_PAR_CAL_MASK 0xc000 /* cache alignment */ 189#define ATW_PAR_CAL_PBL 0x0 190 /* min(8 DW, PBL) */ 191#define ATW_PAR_CAL_8DW LSHIFT(0x1, ATW_PAR_CAL_MASK) 192 /* min(16 DW, PBL) */ 193#define ATW_PAR_CAL_16DW LSHIFT(0x2, ATW_PAR_CAL_MASK) 194 /* min(32 DW, PBL) */ 195#define ATW_PAR_CAL_32DW LSHIFT(0x3, ATW_PAR_CAL_MASK) 196#define ATW_PAR_PBL_MASK 0x3f00 /* programmable burst length */ 197#define ATW_PAR_PBL_UNLIMITED 0x0 198#define ATW_PAR_PBL_1DW LSHIFT(0x1, ATW_PAR_PBL_MASK) 199#define ATW_PAR_PBL_2DW LSHIFT(0x2, ATW_PAR_PBL_MASK) 200#define ATW_PAR_PBL_4DW LSHIFT(0x4, ATW_PAR_PBL_MASK) 201#define ATW_PAR_PBL_8DW LSHIFT(0x8, ATW_PAR_PBL_MASK) 202#define ATW_PAR_PBL_16DW LSHIFT(0x16, ATW_PAR_PBL_MASK) 203#define ATW_PAR_PBL_32DW LSHIFT(0x32, ATW_PAR_PBL_MASK) 204#define ATW_PAR_BLE BIT(7) /* big/little endian selection */ 205#define ATW_PAR_DSL_MASK 0x7c /* descriptor skip length */ 206#define ATW_PAR_BAR BIT(1) /* bus arbitration */ 207#define ATW_PAR_SWR BIT(0) /* software reset */ 208 209#define ATW_FRCTL_PWRMGMT BIT(31) /* power management */ 210#define ATW_FRCTL_VER_MASK 0x60000000 /* protocol version */ 211#define ATW_FRCTL_ORDER BIT(28) /* order bit */ 212#define ATW_FRCTL_MAXPSP BIT(27) /* maximum power saving */ 213#define ATW_C_FRCTL_PRSP BIT(26) /* 1: driver sends probe 214 * response 215 * 0: ASIC sends prresp 216 */ 217#define ATW_C_FRCTL_DRVBCON BIT(25) /* 1: driver sends beacons 218 * 0: ASIC sends beacons 219 */ 220#define ATW_C_FRCTL_DRVLINKCTRL BIT(24) /* 1: driver controls link LED 221 * 0: ASIC controls link LED 222 */ 223#define ATW_C_FRCTL_DRVLINKON BIT(23) /* 1: turn on link LED 224 * 0: turn off link LED 225 */ 226#define ATW_C_FRCTL_CTX_DATA BIT(22) /* 0: set by CSR28 227 * 1: random 228 */ 229#define ATW_C_FRCTL_RSVFRM BIT(21) /* 1: receive "reserved" 230 * frames, 0: ignore 231 * reserved frames 232 */ 233#define ATW_C_FRCTL_CFEND BIT(19) /* write to send CF_END, 234 * ADM8211C/CR clears 235 */ 236#define ATW_FRCTL_DOZEFRM BIT(18) /* select pre-sleep frame */ 237#define ATW_FRCTL_PSAWAKE BIT(17) /* MAC is awake (?) */ 238#define ATW_FRCTL_PSMODE BIT(16) /* MAC is power-saving (?) */ 239#define ATW_FRCTL_AID_MASK 0xffff /* STA Association ID */ 240 241#define ATW_INTR_PCF BIT(31) /* started/ended CFP */ 242#define ATW_INTR_BCNTC BIT(30) /* transmitted IBSS beacon */ 243#define ATW_INTR_GPINT BIT(29) /* GPIO interrupt */ 244#define ATW_INTR_LINKOFF BIT(28) /* lost ATW_WCSR_BLN beacons */ 245#define ATW_INTR_ATIMTC BIT(27) /* transmitted ATIM */ 246#define ATW_INTR_TSFTF BIT(26) /* TSFT out of range */ 247#define ATW_INTR_TSCZ BIT(25) /* TSC countdown expired */ 248#define ATW_INTR_LINKON BIT(24) /* matched SSID, BSSID */ 249#define ATW_INTR_SQL BIT(23) /* Marvel signal quality */ 250#define ATW_INTR_WEPTD BIT(22) /* switched WEP table */ 251#define ATW_INTR_ATIME BIT(21) /* ended ATIM window */ 252#define ATW_INTR_TBTT BIT(20) /* (TBTT) Target Beacon TX Time 253 * passed 254 */ 255#define ATW_INTR_NISS BIT(16) /* normal interrupt status 256 * summary: any of 31, 30, 27, 257 * 24, 14, 12, 6, 2, 0. 258 */ 259#define ATW_INTR_AISS BIT(15) /* abnormal interrupt status 260 * summary: any of 29, 28, 26, 261 * 25, 23, 22, 13, 11, 8, 7, 5, 262 * 4, 3, 1. 263 */ 264#define ATW_INTR_TEIS BIT(14) /* transmit early interrupt 265 * status: moved TX packet to 266 * FIFO 267 */ 268#define ATW_INTR_FBE BIT(13) /* fatal bus error */ 269#define ATW_INTR_REIS BIT(12) /* receive early interrupt 270 * status: RX packet filled 271 * its first descriptor 272 */ 273#define ATW_INTR_GPTT BIT(11) /* general purpose timer expired */ 274#define ATW_INTR_RPS BIT(8) /* stopped receive process */ 275#define ATW_INTR_RDU BIT(7) /* receive descriptor 276 * unavailable 277 */ 278#define ATW_INTR_RCI BIT(6) /* completed packet reception */ 279#define ATW_INTR_TUF BIT(5) /* transmit underflow */ 280#define ATW_INTR_TRT BIT(4) /* transmit retry count 281 * expired 282 */ 283#define ATW_INTR_TLT BIT(3) /* transmit lifetime exceeded */ 284#define ATW_INTR_TDU BIT(2) /* transmit descriptor 285 * unavailable 286 */ 287#define ATW_INTR_TPS BIT(1) /* stopped transmit process */ 288#define ATW_INTR_TCI BIT(0) /* completed transmit */ 289#define ATW_NAR_TXCF BIT(31) /* stop process on TX failure */ 290#define ATW_NAR_HF BIT(30) /* flush TX FIFO to host (?) */ 291#define ATW_NAR_UTR BIT(29) /* select retry count source */ 292#define ATW_NAR_PCF BIT(28) /* use one/both transmit 293 * descriptor base addresses 294 */ 295#define ATW_NAR_CFP BIT(27) /* indicate more TX data to 296 * point coordinator 297 */ 298#define ATW_C_NAR_APSTA BIT(26) /* 0: STA mode 299 * 1: AP mode 300 */ 301#define ATW_C_NAR_TDBBE BIT(25) /* 0: disable TDBB 302 * 1: enable TDBB 303 */ 304#define ATW_C_NAR_TDBHE BIT(24) /* 0: disable TDBH 305 * 1: enable TDBH 306 */ 307#define ATW_C_NAR_TDBHT BIT(23) /* write 1 to make ASIC 308 * poll TDBH once; ASIC clears 309 */ 310#define ATW_NAR_SF BIT(21) /* store and forward: ignore 311 * TX threshold 312 */ 313#define ATW_NAR_TR_MASK 0xc000 /* TX threshold */ 314#define ATW_NAR_TR_L64 LSHIFT(0x0, ATW_NAR_TR_MASK) 315#define ATW_NAR_TR_L160 LSHIFT(0x2, ATW_NAR_TR_MASK) 316#define ATW_NAR_TR_L192 LSHIFT(0x3, ATW_NAR_TR_MASK) 317#define ATW_NAR_TR_H96 LSHIFT(0x0, ATW_NAR_TR_MASK) 318#define ATW_NAR_TR_H288 LSHIFT(0x2, ATW_NAR_TR_MASK) 319#define ATW_NAR_TR_H544 LSHIFT(0x3, ATW_NAR_TR_MASK) 320#define ATW_NAR_ST BIT(13) /* start/stop transmit */ 321#define ATW_NAR_OM_MASK 0xc00 /* operating mode */ 322#define ATW_NAR_OM_NORMAL 0x0 323#define ATW_NAR_OM_LOOPBACK LSHIFT(0x1, ATW_NAR_OM_MASK) 324#define ATW_NAR_MM BIT(7) /* RX any multicast */ 325#define ATW_NAR_PR BIT(6) /* promiscuous mode */ 326#define ATW_NAR_EA BIT(5) /* match ad hoc packets (?) */ 327#define ATW_NAR_DISPCF BIT(4) /* 1: PCF *not* supported 328 * 0: PCF supported 329 */ 330#define ATW_NAR_PB BIT(3) /* pass bad packets */ 331#define ATW_NAR_STPDMA BIT(2) /* stop DMA, abort packet */ 332#define ATW_NAR_SR BIT(1) /* start/stop receive */ 333#define ATW_NAR_CTX BIT(0) /* continuous TX mode */ 334 335/* IER bits are identical to STSR bits. Use ATW_INTR_*. */ 336#if 0 337#define ATW_IER_NIE BIT(16) /* normal interrupt enable */ 338#define ATW_IER_AIE BIT(15) /* abnormal interrupt enable */ 339/* normal interrupts: combine with ATW_IER_NIE */ 340#define ATW_IER_PCFIE BIT(31) /* STA entered CFP */ 341#define ATW_IER_BCNTCIE BIT(30) /* STA TX'd beacon */ 342#define ATW_IER_ATIMTCIE BIT(27) /* transmitted ATIM */ 343#define ATW_IER_LINKONIE BIT(24) /* matched beacon */ 344#define ATW_IER_ATIMIE BIT(21) /* ended ATIM window */ 345#define ATW_IER_TBTTIE BIT(20) /* TBTT */ 346#define ATW_IER_TEIE BIT(14) /* moved TX packet to FIFO */ 347#define ATW_IER_REIE BIT(12) /* RX packet filled its first 348 * descriptor 349 */ 350#define ATW_IER_RCIE BIT(6) /* completed RX */ 351#define ATW_IER_TDUIE BIT(2) /* transmit descriptor 352 * unavailable 353 */ 354#define ATW_IER_TCIE BIT(0) /* completed TX */ 355/* abnormal interrupts: combine with ATW_IER_AIE */ 356#define ATW_IER_GPIE BIT(29) /* GPIO interrupt */ 357#define ATW_IER_LINKOFFIE BIT(28) /* lost beacon */ 358#define ATW_IER_TSFTFIE BIT(26) /* TSFT out of range */ 359#define ATW_IER_TSCIE BIT(25) /* TSC countdown expired */ 360#define ATW_IER_SQLIE BIT(23) /* signal quality */ 361#define ATW_IER_WEPIE BIT(22) /* finished WEP table switch */ 362#define ATW_IER_FBEIE BIT(13) /* fatal bus error */ 363#define ATW_IER_GPTIE BIT(11) /* general purpose timer expired */ 364#define ATW_IER_RPSIE BIT(8) /* stopped receive process */ 365#define ATW_IER_RUIE BIT(7) /* receive descriptor unavailable */ 366#define ATW_IER_TUIE BIT(5) /* transmit underflow */ 367#define ATW_IER_TRTIE BIT(4) /* exceeded transmit retry count */ 368#define ATW_IER_TLTTIE BIT(3) /* transmit lifetime exceeded */ 369#define ATW_IER_TPSIE BIT(1) /* stopped transmit process */ 370#endif 371 372#define ATW_LPC_LPCO BIT(16) /* lost packet counter overflow */ 373#define ATW_LPC_LPC_MASK 0xffff /* lost packet counter */ 374 375#define ATW_TEST1_CONTROL BIT(31) /* "0: read from dxfer_control, 376 * 1: read from dxfer_state" 377 */ 378#define ATW_TEST1_DBGREAD_MASK 0x70000000 /* "control of read data, 379 * debug only" 380 */ 381#define ATW_TEST1_TXWP_MASK 0xe000000 /* select ATW_WTDP content? */ 382#define ATW_TEST1_TXWP_TDBD LSHIFT(0x0, ATW_TEST1_TXWP_MASK) 383#define ATW_TEST1_TXWP_TDBH LSHIFT(0x1, ATW_TEST1_TXWP_MASK) 384#define ATW_TEST1_TXWP_TDBB LSHIFT(0x2, ATW_TEST1_TXWP_MASK) 385#define ATW_TEST1_TXWP_TDBP LSHIFT(0x3, ATW_TEST1_TXWP_MASK) 386#define ATW_TEST1_RSVD0_MASK 0x1ffffc0 /* reserved */ 387#define ATW_TEST1_TESTMODE_MASK 0x30 388/* normal operation */ 389#define ATW_TEST1_TESTMODE_NORMAL LSHIFT(0x0, ATW_TEST1_TESTMODE_MASK) 390/* MAC-only mode */ 391#define ATW_TEST1_TESTMODE_MACONLY LSHIFT(0x1, ATW_TEST1_TESTMODE_MASK) 392/* normal operation */ 393#define ATW_TEST1_TESTMODE_NORMAL2 LSHIFT(0x2, ATW_TEST1_TESTMODE_MASK) 394/* monitor mode */ 395#define ATW_TEST1_TESTMODE_MONITOR LSHIFT(0x3, ATW_TEST1_TESTMODE_MASK) 396 397#define ATW_TEST1_DUMP_MASK 0xf /* select dump signal 398 * from dxfer (huh?) 399 */ 400 401#define ATW_SPR_SRS BIT(11) /* activate SEEPROM access */ 402#define ATW_SPR_SDO BIT(3) /* data out of SEEPROM */ 403#define ATW_SPR_SDI BIT(2) /* data into SEEPROM */ 404#define ATW_SPR_SCLK BIT(1) /* SEEPROM clock */ 405#define ATW_SPR_SCS BIT(0) /* SEEPROM chip select */ 406 407#define ATW_TEST0_BE_MASK 0xe0000000 /* Bus error state */ 408#define ATW_TEST0_TS_MASK 0x1c000000 /* Transmit process state */ 409 410/* Stopped */ 411#define ATW_TEST0_TS_STOPPED LSHIFT(0, ATW_TEST0_TS_MASK) 412/* Running - fetch transmit descriptor */ 413#define ATW_TEST0_TS_FETCH LSHIFT(1, ATW_TEST0_TS_MASK) 414/* Running - wait for end of transmission */ 415#define ATW_TEST0_TS_WAIT LSHIFT(2, ATW_TEST0_TS_MASK) 416/* Running - read buffer from memory and queue into FIFO */ 417#define ATW_TEST0_TS_READING LSHIFT(3, ATW_TEST0_TS_MASK) 418#define ATW_TEST0_TS_RESERVED1 LSHIFT(4, ATW_TEST0_TS_MASK) 419#define ATW_TEST0_TS_RESERVED2 LSHIFT(5, ATW_TEST0_TS_MASK) 420/* Suspended */ 421#define ATW_TEST0_TS_SUSPENDED LSHIFT(6, ATW_TEST0_TS_MASK) 422/* Running - close transmit descriptor */ 423#define ATW_TEST0_TS_CLOSE LSHIFT(7, ATW_TEST0_TS_MASK) 424 425/* ADM8211C/CR registers */ 426/* Suspended */ 427#define ATW_C_TEST0_TS_SUSPENDED LSHIFT(4, ATW_TEST0_TS_MASK) 428/* Descriptor write */ 429#define ATW_C_TEST0_TS_CLOSE LSHIFT(5, ATW_TEST0_TS_MASK) 430/* Last descriptor write */ 431#define ATW_C_TEST0_TS_CLOSELAST LSHIFT(6, ATW_TEST0_TS_MASK) 432/* FIFO full */ 433#define ATW_C_TEST0_TS_FIFOFULL LSHIFT(7, ATW_TEST0_TS_MASK) 434 435#define ATW_TEST0_RS_MASK 0x3800000 /* Receive process state */ 436 437/* Stopped */ 438#define ATW_TEST0_RS_STOPPED LSHIFT(0, ATW_TEST0_RS_MASK) 439/* Running - fetch receive descriptor */ 440#define ATW_TEST0_RS_FETCH LSHIFT(1, ATW_TEST0_RS_MASK) 441/* Running - check for end of receive */ 442#define ATW_TEST0_RS_CHECK LSHIFT(2, ATW_TEST0_RS_MASK) 443/* Running - wait for packet */ 444#define ATW_TEST0_RS_WAIT LSHIFT(3, ATW_TEST0_RS_MASK) 445/* Suspended */ 446#define ATW_TEST0_RS_SUSPENDED LSHIFT(4, ATW_TEST0_RS_MASK) 447/* Running - close receive descriptor */ 448#define ATW_TEST0_RS_CLOSE LSHIFT(5, ATW_TEST0_RS_MASK) 449/* Running - flush current frame from FIFO */ 450#define ATW_TEST0_RS_FLUSH LSHIFT(6, ATW_TEST0_RS_MASK) 451/* Running - queue current frame from FIFO into buffer */ 452#define ATW_TEST0_RS_QUEUE LSHIFT(7, ATW_TEST0_RS_MASK) 453 454#define ATW_TEST0_EPNE BIT(18) /* SEEPROM not detected */ 455#define ATW_TEST0_EPSNM BIT(17) /* SEEPROM bad signature */ 456#define ATW_TEST0_EPTYP_MASK BIT(16) /* SEEPROM type 457 * 1: 93c66, 458 * 0: 93c46 459 */ 460#define ATW_TEST0_EPTYP_93c66 ATW_TEST0_EPTYP_MASK 461#define ATW_TEST0_EPTYP_93c46 0 462#define ATW_TEST0_EPRLD BIT(15) /* recall SEEPROM (write 1) */ 463 464#define ATW_WCSR_CRCT BIT(30) /* CRC-16 type */ 465#define ATW_WCSR_WP1E BIT(29) /* match wake-up pattern 1 */ 466#define ATW_WCSR_WP2E BIT(28) /* match wake-up pattern 2 */ 467#define ATW_WCSR_WP3E BIT(27) /* match wake-up pattern 3 */ 468#define ATW_WCSR_WP4E BIT(26) /* match wake-up pattern 4 */ 469#define ATW_WCSR_WP5E BIT(25) /* match wake-up pattern 5 */ 470#define ATW_WCSR_BLN_MASK 0xe00000 /* lose link after BLN lost 471 * beacons 472 */ 473#define ATW_WCSR_TSFTWE BIT(20) /* wake up on TSFT out of 474 * range 475 */ 476#define ATW_WCSR_TIMWE BIT(19) /* wake up on TIM */ 477#define ATW_WCSR_ATIMWE BIT(18) /* wake up on ATIM */ 478#define ATW_WCSR_KEYWE BIT(17) /* wake up on key update */ 479#define ATW_WCSR_WFRE BIT(10) /* wake up on wake-up frame */ 480#define ATW_WCSR_MPRE BIT(9) /* wake up on magic packet */ 481#define ATW_WCSR_LSOE BIT(8) /* wake up on link loss */ 482/* wake-up reasons correspond to enable bits */ 483#define ATW_WCSR_KEYUP BIT(6) /* */ 484#define ATW_WCSR_TSFTW BIT(5) /* */ 485#define ATW_WCSR_TIMW BIT(4) /* */ 486#define ATW_WCSR_ATIMW BIT(3) /* */ 487#define ATW_WCSR_WFR BIT(2) /* */ 488#define ATW_WCSR_MPR BIT(1) /* */ 489#define ATW_WCSR_LSO BIT(0) /* */ 490 491#define ATW_GPTMR_COM_MASK BIT(16) /* continuous operation mode */ 492#define ATW_GPTMR_GTV_MASK 0xffff /* set countdown in 204us ticks */ 493 494#define ATW_GPIO_EC1_MASK 0x3000000 /* GPIO1 event configuration */ 495#define ATW_GPIO_LAT_MASK 0x300000 /* input latch */ 496#define ATW_GPIO_INTEN_MASK 0xc0000 /* interrupt enable */ 497#define ATW_GPIO_EN_MASK 0x3f000 /* output enable */ 498#define ATW_GPIO_O_MASK 0xfc0 /* output value */ 499#define ATW_GPIO_I_MASK 0x3f /* pin static input */ 500 501#define ATW_BBPCTL_TWI BIT(31) /* Intersil 3-wire interface */ 502#define ATW_BBPCTL_RF3KADDR_MASK 0x7f000000 /* Address for RF3000 */ 503#define ATW_BBPCTL_RF3KADDR_ADDR LSHIFT(0x20, ATW_BBPCTL_RF3KADDR_MASK) 504#define ATW_BBPCTL_NEGEDGE_DO BIT(23) /* data-out on negative edge */ 505#define ATW_BBPCTL_NEGEDGE_DI BIT(22) /* data-in on negative edge */ 506#define ATW_BBPCTL_CCA_ACTLO BIT(21) /* CCA low when busy */ 507#define ATW_BBPCTL_TYPE_MASK 0x1c0000 /* BBP type */ 508#define ATW_BBPCTL_WR BIT(17) /* start write; reset on 509 * completion 510 */ 511#define ATW_BBPCTL_RD BIT(16) /* start read; reset on 512 * completion 513 */ 514#define ATW_BBPCTL_ADDR_MASK 0xff00 /* BBP address */ 515#define ATW_BBPCTL_DATA_MASK 0xff /* BBP data */ 516 517#define ATW_SYNCTL_WR BIT(31) /* start write; reset on 518 * completion 519 */ 520#define ATW_SYNCTL_RD BIT(30) /* start read; reset on 521 * completion 522 */ 523#define ATW_SYNCTL_CS0 BIT(29) /* chip select */ 524#define ATW_SYNCTL_CS1 BIT(28) 525#define ATW_SYNCTL_CAL BIT(27) /* generate RF CAL pulse after 526 * Rx 527 */ 528#define ATW_SYNCTL_SELCAL BIT(26) /* RF CAL source, 0: CAL bit, 529 * 1: MAC; needed by Intersil 530 * BBP 531 */ 532#define ATW_C_SYNCTL_MMICE BIT(25) /* ADM8211C/CR define this 533 * bit. 0: latch data on 534 * negative edge, 1: positive 535 * edge. 536 */ 537#define ATW_SYNCTL_RFTYPE_MASK 0x1c00000 /* RF type */ 538#define ATW_SYNCTL_DATA_MASK 0x3fffff /* synthesizer setting */ 539 540#define ATW_PLCPHD_SIGNAL_MASK 0xff000000 /* signal field in PLCP header, 541 * only for beacon, ATIM, and 542 * RTS. 543 */ 544#define ATW_PLCPHD_SERVICE_MASK 0xff0000 /* service field in PLCP 545 * header; with RFMD BBP, 546 * sets Tx power for beacon, 547 * RTS, ATIM. 548 */ 549#define ATW_PLCPHD_PMBL BIT(15) /* 0: long preamble, 1: short */ 550 551#define ATW_MMIWADDR_LENLO_MASK 0xff000000 /* tx: written 4th */ 552#define ATW_MMIWADDR_LENHI_MASK 0xff0000 /* tx: written 3rd */ 553#define ATW_MMIWADDR_GAIN_MASK 0xff00 /* tx: written 2nd */ 554#define ATW_MMIWADDR_RATE_MASK 0xff /* tx: written 1st */ 555 556/* was magic 0x100E0C0A */ 557#define ATW_MMIWADDR_INTERSIL \ 558 (LSHIFT(0x0c, ATW_MMIWADDR_GAIN_MASK) | \ 559 LSHIFT(0x0a, ATW_MMIWADDR_RATE_MASK) | \ 560 LSHIFT(0x0e, ATW_MMIWADDR_LENHI_MASK) | \ 561 LSHIFT(0x10, ATW_MMIWADDR_LENLO_MASK)) 562 563/* was magic 0x00009101 564 * 565 * ADMtek sets the AI bit on the ATW_MMIWADDR_GAIN_MASK address to 566 * put the RF3000 into auto-increment mode so that it can write Tx gain, 567 * Tx length (high) and Tx length (low) registers back-to-back. 568 */ 569#define ATW_MMIWADDR_RFMD \ 570 (LSHIFT(RF3000_TWI_AI|RF3000_GAINCTL, ATW_MMIWADDR_GAIN_MASK) | \ 571 LSHIFT(RF3000_CTL, ATW_MMIWADDR_RATE_MASK)) 572 573#define ATW_MMIRADDR1_RSVD_MASK 0xff000000 574#define ATW_MMIRADDR1_PWRLVL_MASK 0xff0000 575#define ATW_MMIRADDR1_RSSI_MASK 0xff00 576#define ATW_MMIRADDR1_RXSTAT_MASK 0xff 577 578/* was magic 0x00007c7e 579 * 580 * TBD document registers for Intersil 3861 baseband 581 */ 582#define ATW_MMIRADDR1_INTERSIL \ 583 (LSHIFT(0x7c, ATW_MMIRADDR1_RSSI_MASK) | \ 584 LSHIFT(0x7e, ATW_MMIRADDR1_RXSTAT_MASK)) 585 586/* was magic 0x00000301 */ 587#define ATW_MMIRADDR1_RFMD \ 588 (LSHIFT(RF3000_RSSI, ATW_MMIRADDR1_RSSI_MASK) | \ 589 LSHIFT(RF3000_RXSTAT, ATW_MMIRADDR1_RXSTAT_MASK)) 590 591/* was magic 0x00100000 */ 592#define ATW_MMIRADDR2_INTERSIL \ 593 (LSHIFT(0x0, ATW_MMIRADDR2_ID_MASK) | \ 594 LSHIFT(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) 595 596/* was magic 0x7e100000 */ 597#define ATW_MMIRADDR2_RFMD \ 598 (LSHIFT(0x7e, ATW_MMIRADDR2_ID_MASK) | \ 599 LSHIFT(0x10, ATW_MMIRADDR2_RXPECNT_MASK)) 600 601#define ATW_MMIRADDR2_ID_MASK 0xff000000 /* 1st element ID in WEP table 602 * for Probe Response (huh?) 603 */ 604/* RXPE is re-asserted after RXPECNT * 22MHz. */ 605#define ATW_MMIRADDR2_RXPECNT_MASK 0xff0000 606#define ATW_MMIRADDR2_PROREXT BIT(15) /* Probe Response 607 * 11Mb/s length 608 * extension. 609 */ 610#define ATW_MMIRADDR2_PRORLEN_MASK 0x7fff /* Probe Response 611 * microsecond length 612 */ 613 614#define ATW_TXBR_ALCUPDATE_MASK BIT(31) /* auto-update BBP with ALCSET */ 615#define ATW_TXBR_TBCNT_MASK 0x1f0000 /* transmit burst count */ 616#define ATW_TXBR_ALCSET_MASK 0xff00 /* TX power level set point */ 617#define ATW_TXBR_ALCREF_MASK 0xff /* TX power level reference point */ 618 619#define ATW_ALCSTAT_MCOV_MASK BIT(27) /* MPDU count overflow */ 620#define ATW_ALCSTAT_ESOV_MASK BIT(26) /* error sum overflow */ 621#define ATW_ALCSTAT_MCNT_MASK 0x3ff0000 /* MPDU count, unsigned integer */ 622#define ATW_ALCSTAT_ERSUM_MASK 0xffff /* power error sum, 623 * 2's complement signed integer 624 */ 625 626#define ATW_TOFS2_PWR1UP_MASK 0xf0000000 /* delay of Tx/Rx from PE1, 627 * Radio, PHYRST change after 628 * power-up, in 2ms units 629 */ 630#define ATW_TOFS2_PWR0PAPE_MASK 0xf000000 /* delay of PAPE going low 631 * after internal data 632 * transmit end, in us 633 */ 634#define ATW_TOFS2_PWR1PAPE_MASK 0xf00000 /* delay of PAPE going high 635 * after TXPE asserted, in us 636 */ 637#define ATW_TOFS2_PWR0TRSW_MASK 0xf0000 /* delay of TRSW going low 638 * after internal data transmit 639 * end, in us 640 */ 641#define ATW_TOFS2_PWR1TRSW_MASK 0xf000 /* delay of TRSW going high 642 * after TXPE asserted, in us 643 */ 644#define ATW_TOFS2_PWR0PE2_MASK 0xf00 /* delay of PE2 going low 645 * after internal data transmit 646 * end, in us 647 */ 648#define ATW_TOFS2_PWR1PE2_MASK 0xf0 /* delay of PE2 going high 649 * after TXPE asserted, in us 650 */ 651#define ATW_TOFS2_PWR0TXPE_MASK 0xf /* delay of TXPE going low 652 * after internal data transmit 653 * end, in us 654 */ 655 656#define ATW_CMDR_PM BIT(19) /* enables power mgmt 657 * capabilities. 658 */ 659#define ATW_CMDR_APM BIT(18) /* APM mode, effective when 660 * PM = 1. 661 */ 662#define ATW_CMDR_RTE BIT(4) /* enable Rx FIFO threshold */ 663#define ATW_CMDR_DRT_MASK 0xc /* drain Rx FIFO threshold */ 664/* 32 bytes */ 665#define ATW_CMDR_DRT_8DW LSHIFT(0x0, ATW_CMDR_DRT_MASK) 666/* 64 bytes */ 667#define ATW_CMDR_DRT_16DW LSHIFT(0x1, ATW_CMDR_DRT_MASK) 668/* Store & Forward */ 669#define ATW_CMDR_DRT_SF LSHIFT(0x2, ATW_CMDR_DRT_MASK) 670/* Reserved */ 671#define ATW_CMDR_DRT_RSVD LSHIFT(0x3, ATW_CMDR_DRT_MASK) 672#define ATW_CMDR_SINT_MASK BIT(1) /* software interrupt---huh? */ 673 674/* TBD PCIC */ 675 676/* TBD PMCSR */ 677 678 679#define ATW_PAR0_PAB0_MASK 0xff /* MAC address byte 0 */ 680#define ATW_PAR0_PAB1_MASK 0xff00 /* MAC address byte 1 */ 681#define ATW_PAR0_PAB2_MASK 0xff0000 /* MAC address byte 2 */ 682#define ATW_PAR0_PAB3_MASK 0xff000000 /* MAC address byte 3 */ 683 684#define ATW_C_PAR1_CTD 0xffff0000 /* Continuous Tx pattern */ 685#define ATW_PAR1_PAB5_MASK 0xff00 /* MAC address byte 5 */ 686#define ATW_PAR1_PAB4_MASK 0xff /* MAC address byte 4 */ 687 688#define ATW_MAR0_MAB3_MASK 0xff000000 /* multicast table bits 31:24 */ 689#define ATW_MAR0_MAB2_MASK 0xff0000 /* multicast table bits 23:16 */ 690#define ATW_MAR0_MAB1_MASK 0xff00 /* multicast table bits 15:8 */ 691#define ATW_MAR0_MAB0_MASK 0xff /* multicast table bits 7:0 */ 692 693#define ATW_MAR1_MAB7_MASK 0xff000000 /* multicast table bits 63:56 */ 694#define ATW_MAR1_MAB6_MASK 0xff0000 /* multicast table bits 55:48 */ 695#define ATW_MAR1_MAB5_MASK 0xff00 /* multicast table bits 47:40 */ 696#define ATW_MAR1_MAB4_MASK 0xff /* multicast table bits 39:32 */ 697 698/* ATIM destination address */ 699#define ATW_ATIMDA0_ATIMB3_MASK 0xff000000 700#define ATW_ATIMDA0_ATIMB2_MASK 0xff0000 701#define ATW_ATIMDA0_ATIMB1_MASK 0xff00 702#define ATW_ATIMDA0_ATIMB0_MASK 0xff 703 704/* ATIM destination address, BSSID */ 705#define ATW_ABDA1_BSSIDB5_MASK 0xff000000 706#define ATW_ABDA1_BSSIDB4_MASK 0xff0000 707#define ATW_ABDA1_ATIMB5_MASK 0xff00 708#define ATW_ABDA1_ATIMB4_MASK 0xff 709 710/* BSSID */ 711#define ATW_BSSID0_BSSIDB3_MASK 0xff000000 712#define ATW_BSSID0_BSSIDB2_MASK 0xff0000 713#define ATW_BSSID0_BSSIDB1_MASK 0xff00 714#define ATW_BSSID0_BSSIDB0_MASK 0xff 715 716#define ATW_TXLMT_MTMLT_MASK 0xffff0000 /* max TX MSDU lifetime in TU */ 717#define ATW_TXLMT_SRTYLIM_MASK 0xff /* short retry limit */ 718 719#define ATW_MIBCNT_FFCNT_MASK 0xff000000 /* FCS failure count */ 720#define ATW_MIBCNT_AFCNT_MASK 0xff0000 /* ACK failure count */ 721#define ATW_MIBCNT_RSCNT_MASK 0xff00 /* RTS success count */ 722#define ATW_MIBCNT_RFCNT_MASK 0xff /* RTS failure count */ 723 724#define ATW_BCNT_PLCPH_MASK 0xff0000 /* 11M PLCP length (us) */ 725#define ATW_BCNT_PLCPL_MASK 0xff00 /* 5.5M PLCP length (us) */ 726#define ATW_BCNT_BCNT_MASK 0xff /* byte count of beacon frame */ 727 728/* For ADM8211C/CR */ 729/* ATW_C_TSC_TIMTABSEL = 1 */ 730#define ATW_C_BCNT_EXTEN1 BIT(31) /* 11M beacon len. extension */ 731#define ATW_C_BCNT_BEANLEN1 0x7fff0000 /* beacon length in us */ 732/* ATW_C_TSC_TIMTABSEL = 0 */ 733#define ATW_C_BCNT_EXTEN0 BIT(15) /* 11M beacon len. extension */ 734#define ATW_C_BCNT_BEANLEN0 BIT(14,0) /* beacon length in us */ 735 736#define ATW_C_TSC_TIMOFS 0xff000000 /* I think this is the 737 * SRAM offset for the TIM 738 */ 739#define ATW_C_TSC_TIMLEN 0x3ff000 /* length of TIM */ 740#define ATW_C_TSC_TIMTABSEL BIT(4) /* select TIM table 0 or 1 */ 741#define ATW_TSC_TSC_MASK 0xf /* TSFT countdown value, 0 742 * disables 743 */ 744 745#define ATW_SYNRF_SELSYN BIT(31) /* 0: MAC controls SYN IF pins, 746 * 1: ATW_SYNRF controls SYN IF pins. 747 */ 748#define ATW_SYNRF_SELRF BIT(30) /* 0: MAC controls RF IF pins, 749 * 1: ATW_SYNRF controls RF IF pins. 750 */ 751#define ATW_SYNRF_LERF BIT(29) /* if SELSYN = 1, direct control of 752 * LERF# pin 753 */ 754#define ATW_SYNRF_LEIF BIT(28) /* if SELSYN = 1, direct control of 755 * LEIF# pin 756 */ 757#define ATW_SYNRF_SYNCLK BIT(27) /* if SELSYN = 1, direct control of 758 * SYNCLK pin 759 */ 760#define ATW_SYNRF_SYNDATA BIT(26) /* if SELSYN = 1, direct control of 761 * SYNDATA pin 762 */ 763#define ATW_SYNRF_PE1 BIT(25) /* if SELRF = 1, direct control of 764 * PE1 pin 765 */ 766#define ATW_SYNRF_PE2 BIT(24) /* if SELRF = 1, direct control of 767 * PE2 pin 768 */ 769#define ATW_SYNRF_PAPE BIT(23) /* if SELRF = 1, direct control of 770 * PAPE pin 771 */ 772#define ATW_C_SYNRF_TRSW BIT(22) /* if SELRF = 1, direct control of 773 * TRSW pin 774 */ 775#define ATW_C_SYNRF_TRSWN BIT(21) /* if SELRF = 1, direct control of 776 * TRSWn pin 777 */ 778#define ATW_SYNRF_INTERSIL_EN BIT(20) /* if SELRF = 1, enables 779 * some signal used by the 780 * Intersil RF front-end? 781 * Undocumented. 782 */ 783#define ATW_SYNRF_PHYRST BIT(18) /* if SELRF = 1, direct control of 784 * PHYRST# pin 785 */ 786/* 1: force TXPE = RXPE = 1 if ATW_CMDR[27] = 0. */ 787#define ATW_C_SYNRF_RF2958PD ATW_SYNRF_PHYRST 788 789#define ATW_BPLI_BP_MASK 0xffff0000 /* beacon interval in TU */ 790#define ATW_BPLI_LI_MASK 0xffff /* STA listen interval in 791 * beacon intervals 792 */ 793 794#define ATW_C_CAP0_TIMLEN1 0xff000000 /* TIM table 1 len in bytes 795 * including TIM ID (XXX huh?) 796 */ 797#define ATW_C_CAP0_TIMLEN0 0xff0000 /* TIM table 0 len in bytes, 798 * including TIM ID (XXX huh?) 799 */ 800#define ATW_C_CAP0_CWMAX 0xf00 /* 1 <= CWMAX <= 5 fixes CW? 801 * 5 < CWMAX <= 9 sets max? 802 * 10? 803 * default 0 804 */ 805#define ATW_CAP0_RCVDTIM BIT(4) /* receive every DTIM */ 806#define ATW_CAP0_CHN_MASK 0xf /* current DSSS channel */ 807 808#define ATW_CAP1_CAPI_MASK 0xffff0000 /* capability information */ 809#define ATW_CAP1_ATIMW_MASK 0xffff /* ATIM window in TU */ 810 811#define ATW_RMD_ATIMST BIT(31) /* ATIM frame TX status */ 812#define ATW_RMD_CFP BIT(30) /* CFP indicator */ 813#define ATW_RMD_PCNT 0xfff0000 /* idle time between 814 * awake/ps mode, in seconds 815 */ 816#define ATW_RMD_RMRD_MASK 0xffff /* max RX reception duration 817 * in us 818 */ 819 820#define ATW_CFPP_CFPP 0xff000000 /* CFP unit DTIM */ 821#define ATW_CFPP_CFPMD 0xffff00 /* CFP max duration in TU */ 822#define ATW_CFPP_DTIMP 0xff /* DTIM period in beacon 823 * intervals 824 */ 825#define ATW_TOFS0_USCNT_MASK 0x3f000000 /* number of system clocks 826 * in 1 microsecond. 827 * Depends PCI bus speed? 828 */ 829#define ATW_C_TOFS0_TUCNT_MASK 0x7c00 /* PIFS (microseconds) */ 830#define ATW_TOFS0_TUCNT_MASK 0x3ff /* TU counter in microseconds */ 831 832/* TBD TOFS1 */ 833#define ATW_TOFS1_TSFTOFSR_MASK 0xff000000 /* RX TSFT offset in 834 * microseconds: RF+BBP 835 * latency 836 */ 837#define ATW_TOFS1_TBTTPRE_MASK 0xffff00 /* prediction time, (next 838 * Nth TBTT - TBTTOFS) in 839 * microseconds (huh?). To 840 * match TSFT[25:10] (huh?). 841 */ 842#define ATW_TBTTPRE_MASK 0x3fffc00 843#define ATW_TOFS1_TBTTOFS_MASK 0xff /* wake-up time offset before 844 * TBTT in TU 845 */ 846#define ATW_IFST_SLOT_MASK 0xf800000 /* SLOT time in us */ 847#define ATW_IFST_SIFS_MASK 0x7f8000 /* SIFS time in us */ 848#define ATW_IFST_DIFS_MASK 0x7e00 /* DIFS time in us */ 849#define ATW_IFST_EIFS_MASK 0x1ff /* EIFS time in us */ 850 851#define ATW_RSPT_MART_MASK 0xffff0000 /* max response time in us */ 852#define ATW_RSPT_MIRT_MASK 0xff00 /* min response time in us */ 853#define ATW_RSPT_TSFTOFST_MASK 0xff /* TX TSFT offset in us */ 854 855#define ATW_WEPCTL_WEPENABLE BIT(31) /* enable WEP engine */ 856#define ATW_WEPCTL_AUTOSWITCH BIT(30) /* auto-switch enable (huh?) */ 857#define ATW_WEPCTL_CURTBL BIT(29) /* current table in use */ 858#define ATW_WEPCTL_WR BIT(28) /* */ 859#define ATW_WEPCTL_RD BIT(27) /* */ 860#define ATW_WEPCTL_WEPRXBYP BIT(25) /* bypass WEP on RX */ 861#define ATW_WEPCTL_SHKEY BIT(24) /* 1: pass to host if tbl 862 * lookup fails, 0: use 863 * shared-key 864 */ 865#define ATW_WEPCTL_UNKNOWN0 BIT(23) /* has something to do with 866 * revision 0x20. Possibly 867 * selects a different WEP 868 * table. 869 */ 870#define ATW_WEPCTL_TBLADD_MASK 0x1ff /* add to table */ 871 872/* set these bits in the second byte of a SRAM shared key record to affect 873 * the use and interpretation of the key in the record. 874 */ 875#define ATW_WEP_ENABLED BIT(7) 876#define ATW_WEP_104BIT BIT(6) 877 878#define ATW_WESK_DATA_MASK 0xffff /* data */ 879#define ATW_WEPCNT_WIEC_MASK 0xffff /* WEP ICV error count */ 880 881#define ATW_MACTEST_FORCE_IV BIT(23) 882#define ATW_MACTEST_FORCE_KEYID BIT(22) 883#define ATW_MACTEST_KEYID_MASK 0x300000 884#define ATW_MACTEST_MMI_USETXCLK BIT(11) 885 886/* Function Event/Status registers */ 887 888#define ATW_FER_INTR BIT(15) /* interrupt: set regardless of mask */ 889#define ATW_FER_GWAKE BIT(4) /* general wake-up: set regardless of mask */ 890 891#define ATW_FEMR_INTR_EN BIT(15) /* enable INTA# */ 892#define ATW_FEMR_WAKEUP_EN BIT(14) /* enable wake-up */ 893#define ATW_FEMR_GWAKE_EN BIT(4) /* enable general wake-up */ 894 895#define ATW_FPSR_INTR_STATUS BIT(15) /* interrupt status */ 896#define ATW_FPSR_WAKEUP_STATUS BIT(4) /* CSTSCHG state */ 897#define ATW_FFER_INTA_FORCE BIT(15) /* activate INTA (if not masked) */ 898#define ATW_FFER_GWAKE_FORCE BIT(4) /* activate CSTSCHG (if not masked) */ 899 900/* Serial EEPROM offsets */ 901#define ATW_SR_CLASS_CODE (0x00/2) 902#define ATW_SR_FORMAT_VERSION (0x02/2) 903#define ATW_SR_MAJOR_MASK 0xff 904#define ATW_SR_MINOR_MASK 0xff00 905#define ATW_SR_MAC00 (0x08/2) /* CSR21 */ 906#define ATW_SR_MAC01 (0x0A/2) /* CSR21/22 */ 907#define ATW_SR_MAC10 (0x0C/2) /* CSR22 */ 908#define ATW_SR_CSR20 (0x16/2) 909#define ATW_SR_ANT_MASK 0x1c00 910#define ATW_SR_PWRSCALE_MASK 0x300 911#define ATW_SR_CLKSAVE_MASK 0xc0 912#define ATW_SR_RFTYPE_MASK 0x38 913#define ATW_SR_BBPTYPE_MASK 0x7 914#define ATW_SR_CR28_CR03 (0x18/2) 915#define ATW_SR_CR28_MASK 0xff00 916#define ATW_SR_CR03_MASK 0xff 917#define ATW_SR_CTRY_CR29 (0x1A/2) 918#define ATW_SR_CTRY_MASK 0xff00 /* country code */ 919#define COUNTRY_FCC 0 920#define COUNTRY_IC 1 921#define COUNTRY_ETSI 2 922#define COUNTRY_SPAIN 3 923#define COUNTRY_FRANCE 4 924#define COUNTRY_MMK 5 925#define COUNTRY_MMK2 6 926#define ATW_SR_CR29_MASK 0xff 927#define ATW_SR_PCI_DEVICE (0x20/2) /* CR0 */ 928#define ATW_SR_PCI_VENDOR (0x22/2) /* CR0 */ 929#define ATW_SR_SUB_DEVICE (0x24/2) /* CR11 */ 930#define ATW_SR_SUB_VENDOR (0x26/2) /* CR11 */ 931#define ATW_SR_CR15 (0x28/2) 932#define ATW_SR_LOCISPTR (0x2A/2) /* CR10 */ 933#define ATW_SR_HICISPTR (0x2C/2) /* CR10 */ 934#define ATW_SR_CSR18 (0x2E/2) 935#define ATW_SR_D0_D1_PWR (0x40/2) /* CR49 */ 936#define ATW_SR_D2_D3_PWR (0x42/2) /* CR49 */ 937#define ATW_SR_CIS_WORDS (0x52/2) 938/* CR17 of RFMD RF3000 BBP: returns TWO channels */ 939#define ATW_SR_TXPOWER(chnl) (0x54/2 + ((chnl) - 1)/2) 940/* CR20 of RFMD RF3000 BBP: returns TWO channels */ 941#define ATW_SR_LPF_CUTOFF(chnl) (0x62/2 + ((chnl) - 1)/2) 942/* CR21 of RFMD RF3000 BBP: returns TWO channels */ 943#define ATW_SR_LNA_GS_THRESH(chnl) (0x70/2 + ((chnl) - 1)/2) 944#define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */ 945#define ATW_SR_CIS (0x80/2) /* Cardbus CIS */ 946 947/* Tx descriptor */ 948struct atw_txdesc { 949 u_int32_t at_ctl; 950#define at_stat at_ctl 951 u_int32_t at_flags; 952 u_int32_t at_buf1; 953 u_int32_t at_buf2; 954}; 955 956#define ATW_TXCTL_OWN BIT(31) /* 1: ready to transmit */ 957#define ATW_TXCTL_DONE BIT(30) /* 0: not processed */ 958#define ATW_TXCTL_TXDR_MASK 0xff00000 /* TX data rate (?) */ 959#define ATW_TXCTL_TL_MASK 0xfffff /* retry limit, 0 - 255 */ 960 961#define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */ 962#define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */ 963#define ATW_TXSTAT_ES BIT(29) /* 0: TX successful */ 964#define ATW_TXSTAT_TLT BIT(28) /* TX lifetime expired */ 965#define ATW_TXSTAT_TRT BIT(27) /* TX retry limit expired */ 966#define ATW_TXSTAT_TUF BIT(26) /* TX under-run error */ 967#define ATW_TXSTAT_TRO BIT(25) /* TX over-run error */ 968#define ATW_TXSTAT_SOFBR BIT(24) /* packet size != buffer size 969 * (?) 970 */ 971#define ATW_TXSTAT_ARC_MASK 0xfff /* accumulated retry count */ 972 973#define ATW_TXFLAG_IC BIT(31) /* interrupt on completion */ 974#define ATW_TXFLAG_LS BIT(30) /* packet's last descriptor */ 975#define ATW_TXFLAG_FS BIT(29) /* packet's first descriptor */ 976#define ATW_TXFLAG_TER BIT(25) /* end of ring */ 977#define ATW_TXFLAG_TCH BIT(24) /* at_buf2 is 2nd chain */ 978#define ATW_TXFLAG_TBS2_MASK 0xfff000 /* at_buf2 byte count */ 979#define ATW_TXFLAG_TBS1_MASK 0xfff /* at_buf1 byte count */ 980 981/* Rx descriptor */ 982struct atw_rxdesc { 983 u_int32_t ar_stat; 984 u_int32_t ar_ctl; 985 u_int32_t ar_buf1; 986 u_int32_t ar_buf2; 987}; 988 989#define ar_rssi ar_ctl 990 991#define ATW_RXCTL_RER BIT(25) /* end of ring */ 992#define ATW_RXCTL_RCH BIT(24) /* ar_buf2 is 2nd chain */ 993#define ATW_RXCTL_RBS2_MASK 0xfff000 /* ar_buf2 byte count */ 994#define ATW_RXCTL_RBS1_MASK 0xfff /* ar_buf1 byte count */ 995 996#define ATW_RXSTAT_OWN BIT(31) /* 1: NIC may fill descriptor */ 997#define ATW_RXSTAT_ES BIT(30) /* error summary, 0 on 998 * success 999 */ 1000#define ATW_RXSTAT_SQL BIT(29) /* has signal quality (?) */ 1001#define ATW_RXSTAT_DE BIT(28) /* descriptor error---packet is 1002 * truncated. last descriptor 1003 * only 1004 */ 1005#define ATW_RXSTAT_FS BIT(27) /* packet's first descriptor */ 1006#define ATW_RXSTAT_LS BIT(26) /* packet's last descriptor */ 1007#define ATW_RXSTAT_PCF BIT(25) /* received during CFP */ 1008#define ATW_RXSTAT_SFDE BIT(24) /* PLCP SFD error */ 1009#define ATW_RXSTAT_SIGE BIT(23) /* PLCP signal error */ 1010#define ATW_RXSTAT_CRC16E BIT(22) /* PLCP CRC16 error */ 1011#define ATW_RXSTAT_RXTOE BIT(21) /* RX time-out, last descriptor 1012 * only. 1013 */ 1014#define ATW_RXSTAT_CRC32E BIT(20) /* CRC32 error */ 1015#define ATW_RXSTAT_ICVE BIT(19) /* WEP ICV error */ 1016#define ATW_RXSTAT_DA1 BIT(17) /* DA bit 1, admin'd address */ 1017#define ATW_RXSTAT_DA0 BIT(16) /* DA bit 0, group address */ 1018#define ATW_RXSTAT_RXDR_MASK 0xf000 /* RX data rate */ 1019#define ATW_RXSTAT_FL_MASK 0xfff /* RX frame length, last 1020 * descriptor only 1021 */ 1022 1023/* Static RAM (contains WEP keys, beacon content). Addresses and size 1024 * are in 16-bit words. 1025 */ 1026#define ATW_SRAM_ADDR_INDIVL_KEY 0x0 1027#define ATW_SRAM_ADDR_SHARED_KEY (0x160 * 2) 1028#define ATW_SRAM_ADDR_SSID (0x180 * 2) 1029#define ATW_SRAM_ADDR_SUPRATES (0x191 * 2) 1030#define ATW_SRAM_MAXSIZE (0x200 * 2) 1031#define ATW_SRAM_A_SIZE ATW_SRAM_MAXSIZE 1032#define ATW_SRAM_B_SIZE (0x1c0 * 2) 1033 1034