atwreg.h revision 1.1
1/* $OpenBSD: atwreg.h,v 1.1 2004/06/23 01:27:59 millert Exp $ */ 2/* $NetBSD: atwreg.h,v 1.8 2004/05/31 11:40:56 dyoung Exp $ */ 3 4/* 5 * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of the author nor the names of any co-contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 36 * THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* glossary */ 40 41/* DTIM Delivery Traffic Indication Map, sent by AP 42 * ATIM Ad Hoc Traffic Indication Map 43 * TU 1024 microseconds 44 * TSF time synchronization function 45 * TBTT target beacon transmission time 46 * DIFS distributed inter-frame space 47 * SIFS short inter-frame space 48 * EIFS extended inter-frame space 49 */ 50 51/* Macros for bit twiddling. */ 52 53#ifndef _BIT_TWIDDLE 54#define _BIT_TWIDDLE 55/* nth bit, BIT(0) == 0x1. */ 56#define BIT(n) (((n) == 32) ? 0 : ((u_int32_t) 1 << (n))) 57 58/* bits m through n, m < n. */ 59#define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1)) 60 61/* find least significant bit that is set */ 62#define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x)) 63 64/* for x a power of two and p a non-negative integer, is x a greater power than 2**p? */ 65#define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0) 66 67#define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0) 68 69#define MASK_TO_SHIFT4(m) \ 70 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \ 71 ? 2 + MASK_TO_SHIFT2((m) >> 2) \ 72 : MASK_TO_SHIFT2((m))) 73 74#define MASK_TO_SHIFT8(m) \ 75 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \ 76 ? 4 + MASK_TO_SHIFT4((m) >> 4) \ 77 : MASK_TO_SHIFT4((m))) 78 79#define MASK_TO_SHIFT16(m) \ 80 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \ 81 ? 8 + MASK_TO_SHIFT8((m) >> 8) \ 82 : MASK_TO_SHIFT8((m))) 83 84#define MASK_TO_SHIFT(m) \ 85 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \ 86 ? 16 + MASK_TO_SHIFT16((m) >> 16) \ 87 : MASK_TO_SHIFT16((m))) 88 89#define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask)) 90#define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask)) 91#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask)) 92#define PRESHIFT(m) MASK_AND_RSHIFT((m), (m)) 93 94#endif /* _BIT_TWIDDLE */ 95 96/* ADM8211 Host Control and Status Registers */ 97 98#define ATW_PAR 0x00 /* PCI access */ 99#define ATW_FRCTL 0x04 /* Frame control */ 100#define ATW_TDR 0x08 /* Transmit demand */ 101#define ATW_WTDP 0x0C /* Current transmit descriptor pointer */ 102#define ATW_RDR 0x10 /* Receive demand */ 103#define ATW_WRDP 0x14 /* Current receive descriptor pointer */ 104#define ATW_RDB 0x18 /* Receive descriptor base address */ 105#define ATW_CSR3A 0x1C /* Unused (on ADM8211A) */ 106#define ATW_C_TDBH 0x1C /* Transmit descriptor base address, 107 * high-priority packet 108 */ 109#define ATW_TDBD 0x20 /* Transmit descriptor base address, DCF */ 110#define ATW_TDBP 0x24 /* Transmit descriptor base address, PCF */ 111#define ATW_STSR 0x28 /* Status */ 112#define ATW_CSR5A 0x2C /* Unused */ 113#define ATW_C_TDBB 0x2C /* Transmit descriptor base address, buffered 114 * broadcast/multicast packet 115 */ 116#define ATW_NAR 0x30 /* Network access */ 117#define ATW_CSR6A 0x34 /* Unused */ 118#define ATW_IER 0x38 /* Interrupt enable */ 119#define ATW_CSR7A 0x3C 120#define ATW_LPC 0x40 /* Lost packet counter */ 121#define ATW_TEST1 0x44 /* Test register 1 */ 122#define ATW_SPR 0x48 /* Serial port */ 123#define ATW_TEST0 0x4C /* Test register 0 */ 124#define ATW_WCSR 0x50 /* Wake-up control/status */ 125#define ATW_WPDR 0x54 /* Wake-up pattern data */ 126#define ATW_GPTMR 0x58 /* General purpose timer */ 127#define ATW_GPIO 0x5C /* GPIO[5:0] configuration and control */ 128#define ATW_BBPCTL 0x60 /* BBP control port */ 129#define ATW_SYNCTL 0x64 /* synthesizer control port */ 130#define ATW_PLCPHD 0x68 /* PLCP header setting */ 131#define ATW_MMIWADDR 0x6C /* MMI write address */ 132#define ATW_MMIRADDR1 0x70 /* MMI read address 1 */ 133#define ATW_MMIRADDR2 0x74 /* MMI read address 2 */ 134#define ATW_TXBR 0x78 /* Transmit burst counter */ 135#define ATW_CSR15A 0x7C /* Unused */ 136#define ATW_ALCSTAT 0x80 /* ALC statistics */ 137#define ATW_TOFS2 0x84 /* Timing offset parameter 2, 16b */ 138#define ATW_CMDR 0x88 /* Command */ 139#define ATW_PCIC 0x8C /* PCI bus performance counter */ 140#define ATW_PMCSR 0x90 /* Power management command and status */ 141#define ATW_PAR0 0x94 /* Local MAC address register 0, 32b */ 142#define ATW_PAR1 0x98 /* Local MAC address register 1, 16b */ 143#define ATW_MAR0 0x9C /* Multicast address hash table register 0 */ 144#define ATW_MAR1 0xA0 /* Multicast address hash table register 1 */ 145#define ATW_ATIMDA0 0xA4 /* Ad Hoc Traffic Indication Map (ATIM) 146 * frame DA, byte[3:0] 147 */ 148#define ATW_ABDA1 0xA8 /* BSSID address byte[5:4]; 149 * ATIM frame DA byte[5:4] 150 */ 151#define ATW_BSSID0 0xAC /* BSSID address byte[3:0] */ 152#define ATW_TXLMT 0xB0 /* WLAN retry limit, 8b; 153 * Max TX MSDU lifetime, 16b 154 */ 155#define ATW_MIBCNT 0xB4 /* RTS/ACK/FCS MIB count, 32b */ 156#define ATW_BCNT 0xB8 /* Beacon transmission time, 32b */ 157#define ATW_TSFTH 0xBC /* TSFT[63:32], 32b */ 158#define ATW_TSC 0xC0 /* TSFT[39:32] down count value */ 159#define ATW_SYNRF 0xC4 /* SYN RF IF direct control */ 160#define ATW_BPLI 0xC8 /* Beacon interval, 16b. 161 * STA listen interval, 16b. 162 */ 163#define ATW_CAP0 0xCC /* Current channel, 4b. RCVDTIM, 1b. */ 164#define ATW_CAP1 0xD0 /* Capability information, 16b. 165 * ATIM window, 1b. 166 */ 167#define ATW_RMD 0xD4 /* RX max reception duration, 16b */ 168#define ATW_CFPP 0xD8 /* CFP parameter, 32b */ 169#define ATW_TOFS0 0xDC /* Timing offset parameter 0, 28b */ 170#define ATW_TOFS1 0xE0 /* Timing offset parameter 1, 24b */ 171#define ATW_IFST 0xE4 /* IFS timing parameter 1, 32b */ 172#define ATW_RSPT 0xE8 /* Response time, 24b */ 173#define ATW_TSFTL 0xEC /* TSFT[31:0], 32b */ 174#define ATW_WEPCTL 0xF0 /* WEP control */ 175#define ATW_WESK 0xF4 /* Write entry for shared/individual key */ 176#define ATW_WEPCNT 0xF8 /* WEP count */ 177#define ATW_MACTEST 0xFC 178 179#define ATW_FER 0x100 /* Function event */ 180#define ATW_FEMR 0x104 /* Function event mask */ 181#define ATW_FPSR 0x108 /* Function present state */ 182#define ATW_FFER 0x10C /* Function force event */ 183 184 185#define ATW_PAR_MWIE BIT(24) /* memory write and invalidate 186 * enable 187 */ 188#define ATW_PAR_MRLE BIT(23) /* memory read line enable */ 189#define ATW_PAR_MRME BIT(21) /* memory read multiple 190 * enable 191 */ 192#define ATW_PAR_RAP_MASK BITS(17, 18) /* receive auto-polling in 193 * receive suspended state 194 */ 195#define ATW_PAR_CAL_MASK BITS(14, 15) /* cache alignment */ 196#define ATW_PAR_CAL_PBL 0x0 197 /* min(8 DW, PBL) */ 198#define ATW_PAR_CAL_8DW LSHIFT(0x1, ATW_PAR_CAL_MASK) 199 /* min(16 DW, PBL) */ 200#define ATW_PAR_CAL_16DW LSHIFT(0x2, ATW_PAR_CAL_MASK) 201 /* min(32 DW, PBL) */ 202#define ATW_PAR_CAL_32DW LSHIFT(0x3, ATW_PAR_CAL_MASK) 203#define ATW_PAR_PBL_MASK BITS(8, 13) /* programmable burst length */ 204#define ATW_PAR_PBL_UNLIMITED 0x0 205#define ATW_PAR_PBL_1DW LSHIFT(0x1, ATW_PAR_PBL_MASK) 206#define ATW_PAR_PBL_2DW LSHIFT(0x2, ATW_PAR_PBL_MASK) 207#define ATW_PAR_PBL_4DW LSHIFT(0x4, ATW_PAR_PBL_MASK) 208#define ATW_PAR_PBL_8DW LSHIFT(0x8, ATW_PAR_PBL_MASK) 209#define ATW_PAR_PBL_16DW LSHIFT(0x16, ATW_PAR_PBL_MASK) 210#define ATW_PAR_PBL_32DW LSHIFT(0x32, ATW_PAR_PBL_MASK) 211#define ATW_PAR_BLE BIT(7) /* big/little endian selection */ 212#define ATW_PAR_DSL_MASK BITS(2, 6) /* descriptor skip length */ 213#define ATW_PAR_BAR BIT(1) /* bus arbitration */ 214#define ATW_PAR_SWR BIT(0) /* software reset */ 215 216#define ATW_FRCTL_PWRMGMT BIT(31) /* power management */ 217#define ATW_FRCTL_VER_MASK BITS(29, 30) /* protocol version */ 218#define ATW_FRCTL_ORDER BIT(28) /* order bit */ 219#define ATW_FRCTL_MAXPSP BIT(27) /* maximum power saving */ 220#define ATW_C_FRCTL_PRSP BIT(26) /* 1: driver sends probe 221 * response 222 * 0: ASIC sends prresp 223 */ 224#define ATW_C_FRCTL_DRVBCON BIT(25) /* 1: driver sends beacons 225 * 0: ASIC sends beacons 226 */ 227#define ATW_C_FRCTL_DRVLINKCTRL BIT(24) /* 1: driver controls link LED 228 * 0: ASIC controls link LED 229 */ 230#define ATW_C_FRCTL_DRVLINKON BIT(23) /* 1: turn on link LED 231 * 0: turn off link LED 232 */ 233#define ATW_C_FRCTL_CTX_DATA BIT(22) /* 0: set by CSR28 234 * 1: random 235 */ 236#define ATW_C_FRCTL_RSVFRM BIT(21) /* 1: receive "reserved" 237 * frames, 0: ignore 238 * reserved frames 239 */ 240#define ATW_C_FRCTL_CFEND BIT(19) /* write to send CF_END, 241 * ADM8211C/CR clears 242 */ 243#define ATW_FRCTL_DOZEFRM BIT(18) /* select pre-sleep frame */ 244#define ATW_FRCTL_PSAWAKE BIT(17) /* MAC is awake (?) */ 245#define ATW_FRCTL_PSMODE BIT(16) /* MAC is power-saving (?) */ 246#define ATW_FRCTL_AID_MASK BITS(0, 15) /* STA Association ID */ 247 248#define ATW_INTR_PCF BIT(31) /* started/ended CFP */ 249#define ATW_INTR_BCNTC BIT(30) /* transmitted IBSS beacon */ 250#define ATW_INTR_GPINT BIT(29) /* GPIO interrupt */ 251#define ATW_INTR_LINKOFF BIT(28) /* lost ATW_WCSR_BLN beacons */ 252#define ATW_INTR_ATIMTC BIT(27) /* transmitted ATIM */ 253#define ATW_INTR_TSFTF BIT(26) /* TSFT out of range */ 254#define ATW_INTR_TSCZ BIT(25) /* TSC countdown expired */ 255#define ATW_INTR_LINKON BIT(24) /* matched SSID, BSSID */ 256#define ATW_INTR_SQL BIT(23) /* Marvel signal quality */ 257#define ATW_INTR_WEPTD BIT(22) /* switched WEP table */ 258#define ATW_INTR_ATIME BIT(21) /* ended ATIM window */ 259#define ATW_INTR_TBTT BIT(20) /* (TBTT) Target Beacon TX Time 260 * passed 261 */ 262#define ATW_INTR_NISS BIT(16) /* normal interrupt status 263 * summary: any of 31, 30, 27, 264 * 24, 14, 12, 6, 2, 0. 265 */ 266#define ATW_INTR_AISS BIT(15) /* abnormal interrupt status 267 * summary: any of 29, 28, 26, 268 * 25, 23, 22, 13, 11, 8, 7, 5, 269 * 4, 3, 1. 270 */ 271#define ATW_INTR_TEIS BIT(14) /* transmit early interrupt 272 * status: moved TX packet to 273 * FIFO 274 */ 275#define ATW_INTR_FBE BIT(13) /* fatal bus error */ 276#define ATW_INTR_REIS BIT(12) /* receive early interrupt 277 * status: RX packet filled 278 * its first descriptor 279 */ 280#define ATW_INTR_GPTT BIT(11) /* general purpose timer expired */ 281#define ATW_INTR_RPS BIT(8) /* stopped receive process */ 282#define ATW_INTR_RDU BIT(7) /* receive descriptor 283 * unavailable 284 */ 285#define ATW_INTR_RCI BIT(6) /* completed packet reception */ 286#define ATW_INTR_TUF BIT(5) /* transmit underflow */ 287#define ATW_INTR_TRT BIT(4) /* transmit retry count 288 * expired 289 */ 290#define ATW_INTR_TLT BIT(3) /* transmit lifetime exceeded */ 291#define ATW_INTR_TDU BIT(2) /* transmit descriptor 292 * unavailable 293 */ 294#define ATW_INTR_TPS BIT(1) /* stopped transmit process */ 295#define ATW_INTR_TCI BIT(0) /* completed transmit */ 296#define ATW_NAR_TXCF BIT(31) /* stop process on TX failure */ 297#define ATW_NAR_HF BIT(30) /* flush TX FIFO to host (?) */ 298#define ATW_NAR_UTR BIT(29) /* select retry count source */ 299#define ATW_NAR_PCF BIT(28) /* use one/both transmit 300 * descriptor base addresses 301 */ 302#define ATW_NAR_CFP BIT(27) /* indicate more TX data to 303 * point coordinator 304 */ 305#define ATW_C_NAR_APSTA BIT(26) /* 0: STA mode 306 * 1: AP mode 307 */ 308#define ATW_C_NAR_TDBBE BIT(25) /* 0: disable TDBB 309 * 1: enable TDBB 310 */ 311#define ATW_C_NAR_TDBHE BIT(24) /* 0: disable TDBH 312 * 1: enable TDBH 313 */ 314#define ATW_C_NAR_TDBHT BIT(23) /* write 1 to make ASIC 315 * poll TDBH once; ASIC clears 316 */ 317#define ATW_NAR_SF BIT(21) /* store and forward: ignore 318 * TX threshold 319 */ 320#define ATW_NAR_TR_MASK BITS(14, 15) /* TX threshold */ 321#define ATW_NAR_TR_L64 LSHIFT(0x0, ATW_NAR_TR_MASK) 322#define ATW_NAR_TR_L160 LSHIFT(0x2, ATW_NAR_TR_MASK) 323#define ATW_NAR_TR_L192 LSHIFT(0x3, ATW_NAR_TR_MASK) 324#define ATW_NAR_TR_H96 LSHIFT(0x0, ATW_NAR_TR_MASK) 325#define ATW_NAR_TR_H288 LSHIFT(0x2, ATW_NAR_TR_MASK) 326#define ATW_NAR_TR_H544 LSHIFT(0x3, ATW_NAR_TR_MASK) 327#define ATW_NAR_ST BIT(13) /* start/stop transmit */ 328#define ATW_NAR_OM_MASK BITS(10, 11) /* operating mode */ 329#define ATW_NAR_OM_NORMAL 0x0 330#define ATW_NAR_OM_LOOPBACK LSHIFT(0x1, ATW_NAR_OM_MASK) 331#define ATW_NAR_MM BIT(7) /* RX any multicast */ 332#define ATW_NAR_PR BIT(6) /* promiscuous mode */ 333#define ATW_NAR_EA BIT(5) /* match ad hoc packets (?) */ 334#define ATW_NAR_DISPCF BIT(4) /* 1: PCF *not* supported 335 * 0: PCF supported 336 */ 337#define ATW_NAR_PB BIT(3) /* pass bad packets */ 338#define ATW_NAR_STPDMA BIT(2) /* stop DMA, abort packet */ 339#define ATW_NAR_SR BIT(1) /* start/stop receive */ 340#define ATW_NAR_CTX BIT(0) /* continuous TX mode */ 341 342/* IER bits are identical to STSR bits. Use ATW_INTR_*. */ 343#if 0 344#define ATW_IER_NIE BIT(16) /* normal interrupt enable */ 345#define ATW_IER_AIE BIT(15) /* abnormal interrupt enable */ 346/* normal interrupts: combine with ATW_IER_NIE */ 347#define ATW_IER_PCFIE BIT(31) /* STA entered CFP */ 348#define ATW_IER_BCNTCIE BIT(30) /* STA TX'd beacon */ 349#define ATW_IER_ATIMTCIE BIT(27) /* transmitted ATIM */ 350#define ATW_IER_LINKONIE BIT(24) /* matched beacon */ 351#define ATW_IER_ATIMIE BIT(21) /* ended ATIM window */ 352#define ATW_IER_TBTTIE BIT(20) /* TBTT */ 353#define ATW_IER_TEIE BIT(14) /* moved TX packet to FIFO */ 354#define ATW_IER_REIE BIT(12) /* RX packet filled its first 355 * descriptor 356 */ 357#define ATW_IER_RCIE BIT(6) /* completed RX */ 358#define ATW_IER_TDUIE BIT(2) /* transmit descriptor 359 * unavailable 360 */ 361#define ATW_IER_TCIE BIT(0) /* completed TX */ 362/* abnormal interrupts: combine with ATW_IER_AIE */ 363#define ATW_IER_GPIE BIT(29) /* GPIO interrupt */ 364#define ATW_IER_LINKOFFIE BIT(28) /* lost beacon */ 365#define ATW_IER_TSFTFIE BIT(26) /* TSFT out of range */ 366#define ATW_IER_TSCIE BIT(25) /* TSC countdown expired */ 367#define ATW_IER_SQLIE BIT(23) /* signal quality */ 368#define ATW_IER_WEPIE BIT(22) /* finished WEP table switch */ 369#define ATW_IER_FBEIE BIT(13) /* fatal bus error */ 370#define ATW_IER_GPTIE BIT(11) /* general purpose timer expired */ 371#define ATW_IER_RPSIE BIT(8) /* stopped receive process */ 372#define ATW_IER_RUIE BIT(7) /* receive descriptor unavailable */ 373#define ATW_IER_TUIE BIT(5) /* transmit underflow */ 374#define ATW_IER_TRTIE BIT(4) /* exceeded transmit retry count */ 375#define ATW_IER_TLTTIE BIT(3) /* transmit lifetime exceeded */ 376#define ATW_IER_TPSIE BIT(1) /* stopped transmit process */ 377#endif 378 379#define ATW_LPC_LPCO BIT(16) /* lost packet counter overflow */ 380#define ATW_LPC_LPC_MASK BITS(0, 15) /* lost packet counter */ 381 382#define ATW_TEST1_CONTROL BIT(31) /* "0: read from dxfer_control, 383 * 1: read from dxfer_state" 384 */ 385#define ATW_TEST1_DBGREAD_MASK BITS(30,28) /* "control of read data, 386 * debug only" 387 */ 388#define ATW_TEST1_TXWP_MASK BITS(27,25) /* select ATW_WTDP content? */ 389#define ATW_TEST1_TXWP_TDBD LSHIFT(0x0, ATW_TEST1_TXWP_MASK) 390#define ATW_TEST1_TXWP_TDBH LSHIFT(0x1, ATW_TEST1_TXWP_MASK) 391#define ATW_TEST1_TXWP_TDBB LSHIFT(0x2, ATW_TEST1_TXWP_MASK) 392#define ATW_TEST1_TXWP_TDBP LSHIFT(0x3, ATW_TEST1_TXWP_MASK) 393#define ATW_TEST1_RSVD0_MASK BITS(24,6) /* reserved */ 394#define ATW_TEST1_TESTMODE_MASK BITS(5,4) 395#define ATW_TEST1_TESTMODE_NORMAL LSHIFT(0x0, ) /* normal operation */ 396#define ATW_TEST1_TESTMODE_MACONLY LSHIFT(0x1, ) /* MAC-only mode */ 397#define ATW_TEST1_TESTMODE_NORMAL2 LSHIFT(0x2, ) /* normal operation */ 398#define ATW_TEST1_TESTMODE_MONITOR LSHIFT(0x3, ) /* monitor mode */ 399 400#define ATW_TEST1_DUMP_MASK BITS(3,0) /* select dump signal 401 * from dxfer (huh?) 402 */ 403 404#define ATW_SPR_SRS BIT(11) /* activate SEEPROM access */ 405#define ATW_SPR_SDO BIT(3) /* data out of SEEPROM */ 406#define ATW_SPR_SDI BIT(2) /* data into SEEPROM */ 407#define ATW_SPR_SCLK BIT(1) /* SEEPROM clock */ 408#define ATW_SPR_SCS BIT(0) /* SEEPROM chip select */ 409 410/* TBD CSR_TEST0 */ 411#define ATW_TEST0_BE_MASK BITS(31, 29) /* Bus error state */ 412#define ATW_TEST0_TS_MASK BITS(28, 26) /* Transmit process state */ 413 414/* Stopped */ 415#define ATW_TEST0_TS_STOPPED LSHIFT(0, ATW_TEST0_TS_MASK) 416/* Running - fetch transmit descriptor */ 417#define ATW_TEST0_TS_FETCH LSHIFT(1, ATW_TEST0_TS_MASK) 418/* Running - wait for end of transmission */ 419#define ATW_TEST0_TS_WAIT LSHIFT(2, ATW_TEST0_TS_MASK) 420/* Running - read buffer from memory and queue into FIFO */ 421#define ATW_TEST0_TS_READING LSHIFT(3, ATW_TEST0_TS_MASK) 422#define ATW_TEST0_TS_RESERVED1 LSHIFT(4, ATW_TEST0_TS_MASK) 423#define ATW_TEST0_TS_RESERVED2 LSHIFT(5, ATW_TEST0_TS_MASK) 424/* Suspended */ 425#define ATW_TEST0_TS_SUSPENDED LSHIFT(6, ATW_TEST0_TS_MASK) 426/* Running - close transmit descriptor */ 427#define ATW_TEST0_TS_CLOSE LSHIFT(7, ATW_TEST0_TS_MASK) 428 429/* ADM8211C/CR registers */ 430/* Suspended */ 431#define ATW_C_TEST0_TS_SUSPENDED LSHIFT(4, ATW_TEST0_TS_MASK) 432/* Descriptor write */ 433#define ATW_C_TEST0_TS_CLOSE LSHIFT(5, ATW_TEST0_TS_MASK) 434/* Last descriptor write */ 435#define ATW_C_TEST0_TS_CLOSELAST LSHIFT(6, ATW_TEST0_TS_MASK) 436/* FIFO full */ 437#define ATW_C_TEST0_TS_FIFOFULL LSHIFT(7, ATW_TEST0_TS_MASK) 438 439#define ATW_TEST0_RS_MASK BITS(25, 23) /* Receive process state */ 440 441/* Stopped */ 442#define ATW_TEST0_RS_STOPPED LSHIFT(0, ATW_TEST0_RS_MASK) 443/* Running - fetch receive descriptor */ 444#define ATW_TEST0_RS_FETCH LSHIFT(1, ATW_TEST0_RS_MASK) 445/* Running - check for end of receive */ 446#define ATW_TEST0_RS_CHECK LSHIFT(2, ATW_TEST0_RS_MASK) 447/* Running - wait for packet */ 448#define ATW_TEST0_RS_WAIT LSHIFT(3, ATW_TEST0_RS_MASK) 449/* Suspended */ 450#define ATW_TEST0_RS_SUSPENDED LSHIFT(4, ATW_TEST0_RS_MASK) 451/* Running - close receive descriptor */ 452#define ATW_TEST0_RS_CLOSE LSHIFT(5, ATW_TEST0_RS_MASK) 453/* Running - flush current frame from FIFO */ 454#define ATW_TEST0_RS_FLUSH LSHIFT(6, ATW_TEST0_RS_MASK) 455/* Running - queue current frame from FIFO into buffer */ 456#define ATW_TEST0_RS_QUEUE LSHIFT(7, ATW_TEST0_RS_MASK) 457 458#define ATW_TEST0_EPNE BIT(18) /* SEEPROM not detected */ 459#define ATW_TEST0_EPSNM BIT(17) /* SEEPROM bad signature */ 460#define ATW_TEST0_EPTYP_MASK BIT(16) /* SEEPROM type 461 * 1: 93c66, 462 * 0: 93c46 463 */ 464#define ATW_TEST0_EPTYP_93c66 ATW_TEST0_EPTYP_MASK 465#define ATW_TEST0_EPTYP_93c46 0 466#define ATW_TEST0_EPRLD BIT(15) /* recall SEEPROM (write 1) */ 467 468#define ATW_WCSR_CRCT BIT(30) /* CRC-16 type */ 469#define ATW_WCSR_WP1E BIT(29) /* match wake-up pattern 1 */ 470#define ATW_WCSR_WP2E BIT(28) /* match wake-up pattern 2 */ 471#define ATW_WCSR_WP3E BIT(27) /* match wake-up pattern 3 */ 472#define ATW_WCSR_WP4E BIT(26) /* match wake-up pattern 4 */ 473#define ATW_WCSR_WP5E BIT(25) /* match wake-up pattern 5 */ 474#define ATW_WCSR_BLN_MASK BITS(21, 23) /* lose link after BLN lost 475 * beacons 476 */ 477#define ATW_WCSR_TSFTWE BIT(20) /* wake up on TSFT out of 478 * range 479 */ 480#define ATW_WCSR_TIMWE BIT(19) /* wake up on TIM */ 481#define ATW_WCSR_ATIMWE BIT(18) /* wake up on ATIM */ 482#define ATW_WCSR_KEYWE BIT(17) /* wake up on key update */ 483#define ATW_WCSR_WFRE BIT(10) /* wake up on wake-up frame */ 484#define ATW_WCSR_MPRE BIT(9) /* wake up on magic packet */ 485#define ATW_WCSR_LSOE BIT(8) /* wake up on link loss */ 486/* wake-up reasons correspond to enable bits */ 487#define ATW_WCSR_KEYUP BIT(6) /* */ 488#define ATW_WCSR_TSFTW BIT(5) /* */ 489#define ATW_WCSR_TIMW BIT(4) /* */ 490#define ATW_WCSR_ATIMW BIT(3) /* */ 491#define ATW_WCSR_WFR BIT(2) /* */ 492#define ATW_WCSR_MPR BIT(1) /* */ 493#define ATW_WCSR_LSO BIT(0) /* */ 494 495#define ATW_GPTMR_COM_MASK BIT(16) /* continuous operation mode */ 496#define ATW_GPTMR_GTV_MASK BITS(0, 15) /* set countdown in 204us ticks */ 497 498#define ATW_GPIO_EC1_MASK BITS(25, 24) /* GPIO1 event configuration */ 499#define ATW_GPIO_LAT_MASK BITS(21, 20) /* input latch */ 500#define ATW_GPIO_INTEN_MASK BITS(19, 18) /* interrupt enable */ 501#define ATW_GPIO_EN_MASK BITS(17, 12) /* output enable */ 502#define ATW_GPIO_O_MASK BITS(11, 6) /* output value */ 503#define ATW_GPIO_I_MASK BITS(5, 0) /* pin static input */ 504 505#define ATW_BBPCTL_TWI BIT(31) /* Intersil 3-wire interface */ 506#define ATW_BBPCTL_RF3KADDR_MASK BITS(30, 24) /* Address for RF3000 */ 507#define ATW_BBPCTL_RF3KADDR_ADDR LSHIFT(0x20, ATW_BBPCTL_RF3KADDR_MASK) 508#define ATW_BBPCTL_NEGEDGE_DO BIT(23) /* data-out on negative edge */ 509#define ATW_BBPCTL_NEGEDGE_DI BIT(22) /* data-in on negative edge */ 510#define ATW_BBPCTL_CCA_ACTLO BIT(21) /* CCA low when busy */ 511#define ATW_BBPCTL_TYPE_MASK BITS(20, 18) /* BBP type */ 512#define ATW_BBPCTL_WR BIT(17) /* start write; reset on 513 * completion 514 */ 515#define ATW_BBPCTL_RD BIT(16) /* start read; reset on 516 * completion 517 */ 518#define ATW_BBPCTL_ADDR_MASK BITS(15, 8) /* BBP address */ 519#define ATW_BBPCTL_DATA_MASK BITS(7, 0) /* BBP data */ 520 521#define ATW_SYNCTL_WR BIT(31) /* start write; reset on 522 * completion 523 */ 524#define ATW_SYNCTL_RD BIT(30) /* start read; reset on 525 * completion 526 */ 527#define ATW_SYNCTL_CS0 BIT(29) /* chip select */ 528#define ATW_SYNCTL_CS1 BIT(28) 529#define ATW_SYNCTL_CAL BIT(27) /* generate RF CAL pulse after 530 * Rx 531 */ 532#define ATW_SYNCTL_SELCAL BIT(26) /* RF CAL source, 0: CAL bit, 533 * 1: MAC; needed by Intersil 534 * BBP 535 */ 536#define ATW_C_SYNCTL_MMICE BIT(25) /* ADM8211C/CR define this 537 * bit. 0: latch data on 538 * negative edge, 1: positive 539 * edge. 540 */ 541#define ATW_SYNCTL_RFTYPE_MASK BITS(24, 22) /* RF type */ 542#define ATW_SYNCTL_DATA_MASK BITS(21, 0) /* synthesizer setting */ 543 544#define ATW_PLCPHD_SIGNAL_MASK BITS(31, 24) /* signal field in PLCP header, 545 * only for beacon, ATIM, and 546 * RTS. 547 */ 548#define ATW_PLCPHD_SERVICE_MASK BITS(23, 16) /* service field in PLCP 549 * header; with RFMD BBP, 550 * sets Tx power for beacon, 551 * RTS, ATIM. 552 */ 553#define ATW_PLCPHD_PMBL BIT(15) /* 0: long preamble, 1: short */ 554 555#define ATW_MMIWADDR_INTERSIL 0x100E0C0A 556#define ATW_MMIWADDR_RFMD 0x00009101 557 558#define ATW_MMIRADDR1_INTERSIL 0x00007c7e 559#define ATW_MMIRADDR1_RFMD 0x00000301 560 561#define ATW_MMIRADDR2_INTERSIL 0x00100000 562#define ATW_MMIRADDR2_RFMD 0x7e100000 563 564#define ATW_TXBR_ALCUPDATE_MASK BIT(31) /* auto-update BBP with ALCSET */ 565#define ATW_TXBR_TBCNT_MASK BITS(16, 20) /* transmit burst count */ 566#define ATW_TXBR_ALCSET_MASK BITS(8, 15) /* TX power level set point */ 567#define ATW_TXBR_ALCREF_MASK BITS(0, 7) /* TX power level reference point */ 568 569#define ATW_ALCSTAT_MCOV_MASK BIT(27) /* MPDU count overflow */ 570#define ATW_ALCSTAT_ESOV_MASK BIT(26) /* error sum overflow */ 571#define ATW_ALCSTAT_MCNT_MASK BITS(16, 25) /* MPDU count, unsigned integer */ 572#define ATW_ALCSTAT_ERSUM_MASK BITS(0, 15) /* power error sum, 573 * 2's complement signed integer 574 */ 575 576#define ATW_TOFS2_PWR1UP_MASK BITS(31, 28) /* delay of Tx/Rx from PE1, 577 * Radio, PHYRST change after 578 * power-up, in 2ms units 579 */ 580#define ATW_TOFS2_PWR0PAPE_MASK BITS(27, 24) /* delay of PAPE going low 581 * after internal data 582 * transmit end, in us 583 */ 584#define ATW_TOFS2_PWR1PAPE_MASK BITS(23, 20) /* delay of PAPE going high 585 * after TXPE asserted, in us 586 */ 587#define ATW_TOFS2_PWR0TRSW_MASK BITS(19, 16) /* delay of TRSW going low 588 * after internal data transmit 589 * end, in us 590 */ 591#define ATW_TOFS2_PWR1TRSW_MASK BITS(15, 12) /* delay of TRSW going high 592 * after TXPE asserted, in us 593 */ 594#define ATW_TOFS2_PWR0PE2_MASK BITS(11, 8) /* delay of PE2 going low 595 * after internal data transmit 596 * end, in us 597 */ 598#define ATW_TOFS2_PWR1PE2_MASK BITS(7, 4) /* delay of PE2 going high 599 * after TXPE asserted, in us 600 */ 601#define ATW_TOFS2_PWR0TXPE_MASK BITS(3, 0) /* delay of TXPE going low 602 * after internal data transmit 603 * end, in us 604 */ 605 606#define ATW_CMDR_PM BIT(19) /* enables power mgmt 607 * capabilities. 608 */ 609#define ATW_CMDR_APM BIT(18) /* APM mode, effective when 610 * PM = 1. 611 */ 612#define ATW_CMDR_RTE BIT(4) /* enable Rx FIFO threshold */ 613#define ATW_CMDR_DRT_MASK BITS(3, 2) /* drain Rx FIFO threshold */ 614#define ATW_CMDR_SINT_MASK BIT(1) /* software interrupt---huh? */ 615 616/* TBD PCIC */ 617 618/* TBD PMCSR */ 619 620 621#define ATW_PAR0_PAB0_MASK BITS(0, 7) /* MAC address byte 0 */ 622#define ATW_PAR0_PAB1_MASK BITS(8, 15) /* MAC address byte 1 */ 623#define ATW_PAR0_PAB2_MASK BITS(16, 23) /* MAC address byte 2 */ 624#define ATW_PAR0_PAB3_MASK BITS(24, 31) /* MAC address byte 3 */ 625 626#define ATW_C_PAR1_CTD BITS(16,31) /* Continuous Tx pattern */ 627#define ATW_PAR1_PAB5_MASK BITS(8, 15) /* MAC address byte 5 */ 628#define ATW_PAR1_PAB4_MASK BITS(0, 7) /* MAC address byte 4 */ 629 630#define ATW_MAR0_MAB3_MASK BITS(31, 24) /* multicast table bits 31:24 */ 631#define ATW_MAR0_MAB2_MASK BITS(23, 16) /* multicast table bits 23:16 */ 632#define ATW_MAR0_MAB1_MASK BITS(15, 8) /* multicast table bits 15:8 */ 633#define ATW_MAR0_MAB0_MASK BITS(7, 0) /* multicast table bits 7:0 */ 634 635#define ATW_MAR1_MAB7_MASK BITS(31, 24) /* multicast table bits 63:56 */ 636#define ATW_MAR1_MAB6_MASK BITS(23, 16) /* multicast table bits 55:48 */ 637#define ATW_MAR1_MAB5_MASK BITS(15, 8) /* multicast table bits 47:40 */ 638#define ATW_MAR1_MAB4_MASK BITS(7, 0) /* multicast table bits 39:32 */ 639 640/* ATIM destination address */ 641#define ATW_ATIMDA0_ATIMB3_MASK BITS(31,24) 642#define ATW_ATIMDA0_ATIMB2_MASK BITS(23,16) 643#define ATW_ATIMDA0_ATIMB1_MASK BITS(15,8) 644#define ATW_ATIMDA0_ATIMB0_MASK BITS(7,0) 645 646/* ATIM destination address, BSSID */ 647#define ATW_ABDA1_BSSIDB5_MASK BITS(31,24) 648#define ATW_ABDA1_BSSIDB4_MASK BITS(23,16) 649#define ATW_ABDA1_ATIMB5_MASK BITS(15,8) 650#define ATW_ABDA1_ATIMB4_MASK BITS(7,0) 651 652/* BSSID */ 653#define ATW_BSSID0_BSSIDB3_MASK BITS(31,24) 654#define ATW_BSSID0_BSSIDB2_MASK BITS(23,16) 655#define ATW_BSSID0_BSSIDB1_MASK BITS(15,8) 656#define ATW_BSSID0_BSSIDB0_MASK BITS(7,0) 657 658#define ATW_TXLMT_MTMLT_MASK BITS(31,16) /* max TX MSDU lifetime in TU */ 659#define ATW_TXLMT_SRTYLIM_MASK BITS(7,0) /* short retry limit */ 660 661#define ATW_MIBCNT_FFCNT_MASK BITS(31,24) /* FCS failure count */ 662#define ATW_MIBCNT_AFCNT_MASK BITS(23,16) /* ACK failure count */ 663#define ATW_MIBCNT_RSCNT_MASK BITS(15,8) /* RTS success count */ 664#define ATW_MIBCNT_RFCNT_MASK BITS(7,0) /* RTS failure count */ 665 666#define ATW_BCNT_PLCPH_MASK BITS(23,16) /* 11M PLCP length (us) */ 667#define ATW_BCNT_PLCPL_MASK BITS(15,8) /* 5.5M PLCP length (us) */ 668#define ATW_BCNT_BCNT_MASK BITS(7,0) /* byte count of beacon frame */ 669 670/* For ADM8211C/CR */ 671/* ATW_C_TSC_TIMTABSEL = 1 */ 672#define ATW_C_BCNT_EXTEN1 BIT(31) /* 11M beacon len. extension */ 673#define ATW_C_BCNT_BEANLEN1 BITS(30,16) /* beacon length in us */ 674/* ATW_C_TSC_TIMTABSEL = 0 */ 675#define ATW_C_BCNT_EXTEN0 BIT(15) /* 11M beacon len. extension */ 676#define ATW_C_BCNT_BEANLEN0 BIT(14,0) /* beacon length in us */ 677 678#define ATW_C_TSC_TIMOFS BITS(31,24) /* I think this is the 679 * SRAM offset for the TIM 680 */ 681#define ATW_C_TSC_TIMLEN BITS(21,12) /* length of TIM */ 682#define ATW_C_TSC_TIMTABSEL BIT(4) /* select TIM table 0 or 1 */ 683#define ATW_TSC_TSC_MASK BITS(3,0) /* TSFT countdown value, 0 684 * disables 685 */ 686 687#define ATW_SYNRF_SELSYN BIT(31) /* 0: MAC controls SYN IF pins, 688 * 1: ATW_SYNRF controls SYN IF pins. 689 */ 690#define ATW_SYNRF_SELRF BIT(30) /* 0: MAC controls RF IF pins, 691 * 1: ATW_SYNRF controls RF IF pins. 692 */ 693#define ATW_SYNRF_LERF BIT(29) /* if SELSYN = 1, direct control of 694 * LERF# pin 695 */ 696#define ATW_SYNRF_LEIF BIT(28) /* if SELSYN = 1, direct control of 697 * LEIF# pin 698 */ 699#define ATW_SYNRF_SYNCLK BIT(27) /* if SELSYN = 1, direct control of 700 * SYNCLK pin 701 */ 702#define ATW_SYNRF_SYNDATA BIT(26) /* if SELSYN = 1, direct control of 703 * SYNDATA pin 704 */ 705#define ATW_SYNRF_PE1 BIT(25) /* if SELRF = 1, direct control of 706 * PE1 pin 707 */ 708#define ATW_SYNRF_PE2 BIT(24) /* if SELRF = 1, direct control of 709 * PE2 pin 710 */ 711#define ATW_SYNRF_PAPE BIT(23) /* if SELRF = 1, direct control of 712 * PAPE pin 713 */ 714#define ATW_C_SYNRF_TRSW BIT(22) /* if SELRF = 1, direct control of 715 * TRSW pin 716 */ 717#define ATW_C_SYNRF_TRSWN BIT(21) /* if SELRF = 1, direct control of 718 * TRSWn pin 719 */ 720#define ATW_SYNRF_INTERSIL_EN BIT(20) /* if SELRF = 1, enables 721 * some signal used by the 722 * Intersil RF front-end? 723 * Undocumented. 724 */ 725#define ATW_SYNRF_PHYRST BIT(18) /* if SELRF = 1, direct control of 726 * PHYRST# pin 727 */ 728/* 1: force TXPE = RXPE = 1 if ATW_CMDR[27] = 0. */ 729#define ATW_C_SYNRF_RF2958PD ATW_SYNRF_PHYRST 730 731#define ATW_BPLI_BP_MASK BITS(31,16) /* beacon interval in TU */ 732#define ATW_BPLI_LI_MASK BITS(15,0) /* STA listen interval in 733 * beacon intervals 734 */ 735 736#define ATW_C_CAP0_TIMLEN1 BITS(31,24) /* TIM table 1 len in bytes 737 * including TIM ID (XXX huh?) 738 */ 739#define ATW_C_CAP0_TIMLEN0 BITS(23,16) /* TIM table 0 len in bytes, 740 * including TIM ID (XXX huh?) 741 */ 742#define ATW_C_CAP0_CWMAX BITS(11,8) /* 1 <= CWMAX <= 5 fixes CW? 743 * 5 < CWMAX <= 9 sets max? 744 * 10? 745 * default 0 746 */ 747#define ATW_CAP0_RCVDTIM BIT(4) /* receive every DTIM */ 748#define ATW_CAP0_CHN_MASK BITS(3,0) /* current DSSS channel */ 749 750#define ATW_CAP1_CAPI_MASK BITS(31,16) /* capability information */ 751#define ATW_CAP1_ATIMW_MASK BITS(15,0) /* ATIM window in TU */ 752 753#define ATW_RMD_ATIMST BIT(31) /* ATIM frame TX status */ 754#define ATW_RMD_CFP BIT(30) /* CFP indicator */ 755#define ATW_RMD_PCNT BITS(27,16) /* idle time between 756 * awake/ps mode 757 */ 758#define ATW_RMD_RMRD BITS(15,0) /* max RX reception duration 759 * in us 760 */ 761 762#define ATW_CFPP_CFPP BITS(31,24) /* CFP unit DTIM */ 763#define ATW_CFPP_CFPMD BITS(23,8) /* CFP max duration in TU */ 764#define ATW_CFPP_DTIMP BITS(7,0) /* DTIM period in beacon 765 * intervals 766 */ 767#define ATW_TOFS0_USCNT_MASK BITS(29,24) /* number of system clocks 768 * in 1 microsecond. 769 * Depends PCI bus speed? 770 */ 771#define ATW_C_TOFS0_TUCNT_MASK BITS(14,10) /* PIFS (microseconds) */ 772#define ATW_TOFS0_TUCNT_MASK BITS(9,0) /* TU counter in microseconds */ 773 774/* TBD TOFS1 */ 775#define ATW_TOFS1_TSFTOFSR_MASK BITS(31,24) /* RX TSFT offset in 776 * microseconds: RF+BBP 777 * latency 778 */ 779#define ATW_TOFS1_TBTTPRE_MASK BITS(23,8) /* prediction time, (next 780 * Nth TBTT - TBTTOFS) in 781 * microseconds (huh?). To 782 * match TSFT[25:10] (huh?). 783 */ 784#define ATW_TOFS1_TBTTOFS_MASK BITS(7,0) /* wake-up time offset before 785 * TBTT in TU 786 */ 787#define ATW_IFST_SLOT_MASK BITS(27,23) /* SLOT time in us */ 788#define ATW_IFST_SIFS_MASK BITS(22,15) /* SIFS time in us */ 789#define ATW_IFST_DIFS_MASK BITS(14,9) /* DIFS time in us */ 790#define ATW_IFST_EIFS_MASK BITS(8,0) /* EIFS time in us */ 791 792#define ATW_RSPT_MART_MASK BITS(31,16) /* max response time in us */ 793#define ATW_RSPT_MIRT_MASK BITS(15,8) /* min response time in us */ 794#define ATW_RSPT_TSFTOFST_MASK BITS(7,0) /* TX TSFT offset in us */ 795 796#define ATW_WEPCTL_WEPENABLE BIT(31) /* enable WEP engine */ 797#define ATW_WEPCTL_AUTOSWITCH BIT(30) /* auto-switch enable (huh?) */ 798#define ATW_WEPCTL_CURTBL BIT(29) /* current table in use */ 799#define ATW_WEPCTL_WR BIT(28) /* */ 800#define ATW_WEPCTL_RD BIT(27) /* */ 801#define ATW_WEPCTL_WEPRXBYP BIT(25) /* bypass WEP on RX */ 802#define ATW_WEPCTL_SHKEY BIT(24) /* 1: pass to host if tbl 803 * lookup fails, 0: use 804 * shared-key 805 */ 806#define ATW_WEPCTL_UNKNOWN0 BIT(23) /* has something to do with 807 * revision 0x20. Possibly 808 * selects a different WEP 809 * table. 810 */ 811#define ATW_WEPCTL_TBLADD_MASK BITS(8,0) /* add to table */ 812 813/* set these bits in the second byte of a SRAM shared key record to affect 814 * the use and interpretation of the key in the record. 815 */ 816#define ATW_WEP_ENABLED BIT(7) 817#define ATW_WEP_104BIT BIT(6) 818 819#define ATW_WESK_DATA_MASK BITS(15,0) /* data */ 820#define ATW_WEPCNT_WIEC_MASK BITS(15,0) /* WEP ICV error count */ 821 822#define ATW_MACTEST_FORCE_IV BIT(23) 823#define ATW_MACTEST_FORCE_KEYID BIT(22) 824#define ATW_MACTEST_KEYID_MASK BITS(21,20) 825#define ATW_MACTEST_MMI_USETXCLK BIT(11) 826 827/* Function Event/Status registers */ 828 829#define ATW_FER_INTR BIT(15) /* interrupt: set regardless of mask */ 830#define ATW_FER_GWAKE BIT(4) /* general wake-up: set regardless of mask */ 831 832#define ATW_FEMR_INTR_EN BIT(15) /* enable INTA# */ 833#define ATW_FEMR_WAKEUP_EN BIT(14) /* enable wake-up */ 834#define ATW_FEMR_GWAKE_EN BIT(4) /* enable general wake-up */ 835 836#define ATW_FPSR_INTR_STATUS BIT(15) /* interrupt status */ 837#define ATW_FPSR_WAKEUP_STATUS BIT(4) /* CSTSCHG state */ 838#define ATW_FFER_INTA_FORCE BIT(15) /* activate INTA (if not masked) */ 839#define ATW_FFER_GWAKE_FORCE BIT(4) /* activate CSTSCHG (if not masked) */ 840 841/* Serial EEPROM offsets */ 842#define ATW_SR_CLASS_CODE (0x00/2) 843#define ATW_SR_FORMAT_VERSION (0x02/2) 844#define ATW_SR_MAC00 (0x08/2) /* CSR21 */ 845#define ATW_SR_MAC01 (0x0A/2) /* CSR21/22 */ 846#define ATW_SR_MAC10 (0x0C/2) /* CSR22 */ 847#define ATW_SR_CSR20 (0x16/2) 848#define ATW_SR_ANT_MASK BITS(12, 10) 849#define ATW_SR_PWRSCALE_MASK BITS(9, 8) 850#define ATW_SR_CLKSAVE_MASK BITS(7, 6) 851#define ATW_SR_RFTYPE_MASK BITS(5, 3) 852#define ATW_SR_BBPTYPE_MASK BITS(2, 0) 853#define ATW_SR_CR28_CR03 (0x18/2) 854#define ATW_SR_CTRY_CR29 (0x1A/2) 855#define ATW_SR_CTRY_MASK BITS(15,8) /* country code */ 856#define COUNTRY_FCC 0 857#define COUNTRY_IC 1 858#define COUNTRY_ETSI 2 859#define COUNTRY_SPAIN 3 860#define COUNTRY_FRANCE 4 861#define COUNTRY_MMK 5 862#define COUNTRY_MMK2 6 863#define ATW_SR_PCI_DEVICE (0x20/2) /* CR0 */ 864#define ATW_SR_PCI_VENDOR (0x22/2) /* CR0 */ 865#define ATW_SR_SUB_DEVICE (0x24/2) /* CR11 */ 866#define ATW_SR_SUB_VENDOR (0x26/2) /* CR11 */ 867#define ATW_SR_CR15 (0x28/2) 868#define ATW_SR_LOCISPTR (0x2A/2) /* CR10 */ 869#define ATW_SR_HICISPTR (0x2C/2) /* CR10 */ 870#define ATW_SR_CSR18 (0x2E/2) 871#define ATW_SR_D0_D1_PWR (0x40/2) /* CR49 */ 872#define ATW_SR_D2_D3_PWR (0x42/2) /* CR49 */ 873#define ATW_SR_CIS_WORDS (0x52/2) 874/* CR17 of RFMD RF3000 BBP: returns TWO channels */ 875#define ATW_SR_TXPOWER(chnl) (0x54/2 + ((chnl) - 1)/2) 876/* CR20 of RFMD RF3000 BBP: returns TWO channels */ 877#define ATW_SR_LPF_CUTOFF(chnl) (0x62/2 + ((chnl) - 1)/2) 878/* CR21 of RFMD RF3000 BBP: returns TWO channels */ 879#define ATW_SR_LNA_GS_THRESH(chnl) (0x70/2 + ((chnl) - 1)/2) 880#define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */ 881#define ATW_SR_CIS (0x80/2) /* Cardbus CIS */ 882 883/* Tx descriptor */ 884struct atw_txdesc { 885 u_int32_t at_ctl; 886#define at_stat at_ctl 887 u_int32_t at_flags; 888 u_int32_t at_buf1; 889 u_int32_t at_buf2; 890}; 891 892#define ATW_TXCTL_OWN BIT(31) /* 1: ready to transmit */ 893#define ATW_TXCTL_DONE BIT(30) /* 0: not processed */ 894#define ATW_TXCTL_TXDR_MASK BITS(27,20) /* TX data rate (?) */ 895#define ATW_TXCTL_TL_MASK BITS(19,0) /* retry limit, 0 - 255 */ 896 897#define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */ 898#define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */ 899#define ATW_TXSTAT_ES BIT(29) /* 0: TX successful */ 900#define ATW_TXSTAT_TLT BIT(28) /* TX lifetime expired */ 901#define ATW_TXSTAT_TRT BIT(27) /* TX retry limit expired */ 902#define ATW_TXSTAT_TUF BIT(26) /* TX under-run error */ 903#define ATW_TXSTAT_TRO BIT(25) /* TX over-run error */ 904#define ATW_TXSTAT_SOFBR BIT(24) /* packet size != buffer size 905 * (?) 906 */ 907#define ATW_TXSTAT_ARC_MASK BITS(11,0) /* accumulated retry count */ 908 909#define ATW_TXFLAG_IC BIT(31) /* interrupt on completion */ 910#define ATW_TXFLAG_LS BIT(30) /* packet's last descriptor */ 911#define ATW_TXFLAG_FS BIT(29) /* packet's first descriptor */ 912#define ATW_TXFLAG_TER BIT(25) /* end of ring */ 913#define ATW_TXFLAG_TCH BIT(24) /* at_buf2 is 2nd chain */ 914#define ATW_TXFLAG_TBS2_MASK BITS(23,12) /* at_buf2 byte count */ 915#define ATW_TXFLAG_TBS1_MASK BITS(11,0) /* at_buf1 byte count */ 916 917/* Rx descriptor */ 918struct atw_rxdesc { 919 u_int32_t ar_stat; 920 u_int32_t ar_ctl; 921 u_int32_t ar_buf1; 922 u_int32_t ar_buf2; 923}; 924 925#define ar_rssi ar_ctl 926 927#define ATW_RXCTL_RER BIT(25) /* end of ring */ 928#define ATW_RXCTL_RCH BIT(24) /* ar_buf2 is 2nd chain */ 929#define ATW_RXCTL_RBS2_MASK BITS(23,12) /* ar_buf2 byte count */ 930#define ATW_RXCTL_RBS1_MASK BITS(11,0) /* ar_buf1 byte count */ 931 932#define ATW_RXSTAT_OWN BIT(31) /* 1: NIC may fill descriptor */ 933#define ATW_RXSTAT_ES BIT(30) /* error summary, 0 on 934 * success 935 */ 936#define ATW_RXSTAT_SQL BIT(29) /* has signal quality (?) */ 937#define ATW_RXSTAT_DE BIT(28) /* descriptor error---packet is 938 * truncated. last descriptor 939 * only 940 */ 941#define ATW_RXSTAT_FS BIT(27) /* packet's first descriptor */ 942#define ATW_RXSTAT_LS BIT(26) /* packet's last descriptor */ 943#define ATW_RXSTAT_PCF BIT(25) /* received during CFP */ 944#define ATW_RXSTAT_SFDE BIT(24) /* PLCP SFD error */ 945#define ATW_RXSTAT_SIGE BIT(23) /* PLCP signal error */ 946#define ATW_RXSTAT_CRC16E BIT(22) /* PLCP CRC16 error */ 947#define ATW_RXSTAT_RXTOE BIT(21) /* RX time-out, last descriptor 948 * only. 949 */ 950#define ATW_RXSTAT_CRC32E BIT(20) /* CRC32 error */ 951#define ATW_RXSTAT_ICVE BIT(19) /* WEP ICV error */ 952#define ATW_RXSTAT_DA1 BIT(17) /* DA bit 1, admin'd address */ 953#define ATW_RXSTAT_DA0 BIT(16) /* DA bit 0, group address */ 954#define ATW_RXSTAT_RXDR_MASK BITS(15,12) /* RX data rate */ 955#define ATW_RXSTAT_FL_MASK BITS(11,0) /* RX frame length, last 956 * descriptor only 957 */ 958 959/* Static RAM (contains WEP keys, beacon content). Addresses and size 960 * are in 16-bit words. 961 */ 962#define ATW_SRAM_ADDR_INDIVL_KEY 0x0 963#define ATW_SRAM_ADDR_SHARED_KEY (0x160 * 2) 964#define ATW_SRAM_ADDR_SSID (0x180 * 2) 965#define ATW_SRAM_ADDR_SUPRATES (0x191 * 2) 966#define ATW_SRAM_SIZE (0x200 * 2) 967 968