ar5211var.h revision 1.1 
1/*	$OpenBSD: ar5211var.h,v 1.1 2005/02/25 22:25:30 reyk Exp $	*/
2
3/*
4 * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/*
20 * Specific definitions for the Atheros AR5001 Wireless LAN chipset
21 * (AR5211/AR5311).
22 */
23
24#ifndef _AR5K_AR5211_VAR_H
25#define _AR5K_AR5211_VAR_H
26
27#include <dev/ic/ar5xxx.h>
28
29/*
30 * Define a "magic" code for the AR5211 (the HAL layer wants it)
31 */
32
33#define AR5K_AR5211_MAGIC		0x0000145b /* 5211 */
34#define AR5K_AR5211_TX_NUM_QUEUES	10
35
36#if BYTE_ORDER == BIG_ENDIAN
37#define AR5K_AR5211_INIT_CFG	(					\
38	AR5K_AR5211_CFG_SWTD | AR5K_AR5211_CFG_SWTB |			\
39        AR5K_AR5211_CFG_SWRD | AR5K_AR5211_CFG_SWRB |			\
40        AR5K_AR5211_CFG_SWRG						\
41)
42#else
43#define AR5K_AR5211_INIT_CFG	0x00000000
44#endif
45
46/*
47 * Internal RX/TX descriptor structures
48 * (rX: reserved fields possibily used by future versions of the ar5k chipset)
49 */
50
51struct ar5k_ar5211_rx_desc {
52	/*
53	 * First word
54	 */
55	u_int32_t	r1;
56
57	/*
58	 * Second word
59	 */
60	u_int32_t	buf_len:12;
61	u_int32_t	r2:1;
62	u_int32_t	inter_req:1;
63	u_int32_t	r3:18;
64} __packed;
65
66struct ar5k_ar5211_rx_status {
67	/*
68	 * First word
69	 */
70	u_int32_t	data_len:12;
71	u_int32_t	more:1;
72	u_int32_t	r1:1;
73	u_int32_t	receive_antenna:1;
74	u_int32_t	receive_rate:4;
75	u_int32_t	receive_sig_strength:8;
76	u_int32_t	r2:5;
77
78	/*
79	 * Second word
80	 */
81	u_int32_t	done:1;
82	u_int32_t	frame_receive_ok:1;
83	u_int32_t	crc_error:1;
84	u_int32_t	fifo_overrun:1;
85	u_int32_t	decrypt_crc_error:1;
86	u_int32_t	phy_error:3;
87	u_int32_t	key_index_valid:1;
88	u_int32_t	key_index:6;
89	u_int32_t	receive_timestamp:13;
90	u_int32_t	key_cache_miss:1;
91	u_int32_t	r3:3;
92} __packed;
93
94#define AR5K_AR5211_DESC_RX_PHY_ERROR_NONE		0x00
95#define AR5K_AR5211_DESC_RX_PHY_ERROR_TIMING		0x20
96#define AR5K_AR5211_DESC_RX_PHY_ERROR_PARITY		0x40
97#define AR5K_AR5211_DESC_RX_PHY_ERROR_RATE		0x60
98#define AR5K_AR5211_DESC_RX_PHY_ERROR_LENGTH		0x80
99#define AR5K_AR5211_DESC_RX_PHY_ERROR_64QAM		0xa0
100#define AR5K_AR5211_DESC_RX_PHY_ERROR_SERVICE		0xc0
101#define AR5K_AR5211_DESC_RX_PHY_ERROR_TRANSMITOVR	0xe0
102
103struct ar5k_ar5211_tx_desc {
104	/*
105	 * First word
106	 */
107	u_int32_t	frame_len:12;
108	u_int32_t	reserved_12_17:6;
109	u_int32_t	xmit_rate:4;
110	u_int32_t	rts_cts_enable:1;
111	u_int32_t	veol:1;
112	u_int32_t	clear_dest_mask:1;
113	u_int32_t	ant_mode_xmit:4;
114	u_int32_t	inter_req:1;
115	u_int32_t	encrypt_key_valid:1;
116	u_int32_t	reserved_31:1;
117
118	/*
119	 * Second word
120	 */
121	u_int32_t	buf_len:12;
122	u_int32_t	more:1;
123	u_int32_t	encrypt_key_index:7;
124	u_int32_t	frame_type:4;
125	u_int32_t	no_ack:1;
126	u_int32_t	reserved_24_31:1;
127} __packed;
128
129#define AR5K_AR5211_DESC_TX_XMIT_RATE_6		0xb
130#define AR5K_AR5211_DESC_TX_XMIT_RATE_9		0xf
131#define AR5K_AR5211_DESC_TX_XMIT_RATE_12	0xa
132#define AR5K_AR5211_DESC_TX_XMIT_RATE_18	0xe
133#define AR5K_AR5211_DESC_TX_XMIT_RATE_24	0x9
134#define AR5K_AR5211_DESC_TX_XMIT_RATE_36	0xd
135#define AR5K_AR5211_DESC_TX_XMIT_RATE_48	0x8
136#define AR5K_AR5211_DESC_TX_XMIT_RATE_54	0xc
137
138#define AR5K_AR5211_DESC_TX_FRAME_TYPE_NORMAL	0x00
139#define AR5K_AR5211_DESC_TX_FRAME_TYPE_ATIM	0x04
140#define AR5K_AR5211_DESC_TX_FRAME_TYPE_PSPOLL	0x08
141#define AR5K_AR5211_DESC_TX_FRAME_TYPE_NO_DELAY 0x0c
142#define AR5K_AR5211_DESC_TX_FRAME_TYPE_PIFS	0x10
143
144struct ar5k_ar5211_tx_status {
145	/*
146	 * First word
147	 */
148	u_int32_t	frame_xmit_ok:1;
149	u_int32_t	excessive_retries:1;
150	u_int32_t	fifo_underrun:1;
151	u_int32_t	filtered:1;
152	u_int32_t	rts_fail_count:4;
153	u_int32_t	data_fail_count:4;
154	u_int32_t	virt_coll_count:4;
155	u_int32_t	send_timestamp:16;
156
157	/*
158	 * Second word
159	 */
160	u_int32_t	done:1;
161	u_int32_t	seq_num:12;
162	u_int32_t	ack_sig_strength:8;
163	u_int32_t	reserved_21_31:11;
164} __packed;
165
166/*
167 * Public function prototypes
168 */
169extern ar5k_attach_t ar5k_ar5211_attach;
170
171/*
172 * Initial register values which have to be loaded into the
173 * card at boot time and after each reset.
174 */
175
176#define AR5K_AR5211_INI {						\
177	{ 0x000c, 0x00000000 },						\
178	{ 0x0028, 0x84849c9c },						\
179	{ 0x002c, 0x7c7c7c7c },						\
180	{ 0x0034, 0x00000005 },						\
181	{ 0x0040, 0x00000000 },						\
182	{ 0x0044, 0x00000008 },						\
183	{ 0x0048, 0x00000008 },						\
184	{ 0x004c, 0x00000010 },						\
185	{ 0x0050, 0x00000000 },						\
186	{ 0x0054, 0x0000001f },						\
187	{ 0x0800, 0x00000000 },						\
188	{ 0x0804, 0x00000000 },						\
189	{ 0x0808, 0x00000000 },						\
190	{ 0x080c, 0x00000000 },						\
191	{ 0x0810, 0x00000000 },						\
192	{ 0x0814, 0x00000000 },						\
193	{ 0x0818, 0x00000000 },						\
194	{ 0x081c, 0x00000000 },						\
195	{ 0x0820, 0x00000000 },						\
196	{ 0x0824, 0x00000000 },						\
197	{ 0x1230, 0x00000000 },						\
198	{ 0x8004, 0x00000000 },						\
199	{ 0x8008, 0x00000000 },						\
200	{ 0x800c, 0x00000000 },						\
201	{ 0x8018, 0x00000000 },						\
202	{ 0x8024, 0x00000000 },						\
203	{ 0x8028, 0x00000030 },						\
204	{ 0x802c, 0x0007ffff },						\
205	{ 0x8030, 0x01ffffff },						\
206	{ 0x8034, 0x00000031 },						\
207	{ 0x8038, 0x00000000 },						\
208	{ 0x803c, 0x00000000 },						\
209	{ 0x8040, 0x00000000 },						\
210	{ 0x8044, 0x00000002 },						\
211	{ 0x8048, 0x00000000 },						\
212	{ 0x8054, 0x00000000 },						\
213	{ 0x8058, 0x00000000 },						\
214        /* PHY registers */						\
215	{ 0x9808, 0x00000000 },						\
216	{ 0x980c, 0x2d849093 },						\
217	{ 0x9810, 0x7d32e000 },						\
218	{ 0x9814, 0x00000f6b },						\
219	{ 0x981c, 0x00000000 },						\
220	{ 0x982c, 0x00026ffe },						\
221	{ 0x9830, 0x00000000 },						\
222	{ 0x983c, 0x00020100 },						\
223	{ 0x9840, 0x206a017a },						\
224	{ 0x984c, 0x1284613c },						\
225	{ 0x9854, 0x00000859 },						\
226	{ 0x9868, 0x409a4190 },						\
227	{ 0x986c, 0x050cb081 },						\
228	{ 0x9870, 0x0000000f },						\
229	{ 0x9874, 0x00000080 },						\
230	{ 0x9878, 0x0000000c },						\
231	{ 0x9900, 0x00000000 },						\
232	{ 0x9904, 0x00000000 },						\
233	{ 0x9908, 0x00000000 },						\
234	{ 0x990c, 0x00800000 },						\
235	{ 0x9910, 0x00000001 },						\
236	{ 0x991c, 0x0000092a },						\
237	{ 0x9920, 0x00000000 },						\
238	{ 0x9924, 0x00058a05 },						\
239	{ 0x9928, 0x00000001 },						\
240	{ 0x992c, 0x00000000 },						\
241	{ 0x9930, 0x00000000 },						\
242	{ 0x9934, 0x00000000 },						\
243	{ 0x9938, 0x00000000 },						\
244	{ 0x993c, 0x0000003f },						\
245	{ 0x9940, 0x00000004 },						\
246	{ 0x9948, 0x00000000 },						\
247	{ 0x994c, 0x00000000 },						\
248	{ 0x9950, 0x00000000 },						\
249	{ 0x9954, 0x5d50f14c },						\
250	{ 0x9958, 0x00000018 },						\
251	{ 0x995c, 0x004b6a8e },						\
252	{ 0xa184, 0x06ff05ff },						\
253	{ 0xa188, 0x07ff07ff },						\
254	{ 0xa18c, 0x08ff08ff },						\
255	{ 0xa190, 0x09ff09ff },						\
256	{ 0xa194, 0x0aff0aff },						\
257	{ 0xa198, 0x0bff0bff },						\
258	{ 0xa19c, 0x0cff0cff },						\
259	{ 0xa1a0, 0x0dff0dff },						\
260	{ 0xa1a4, 0x0fff0eff },						\
261	{ 0xa1a8, 0x12ff12ff },						\
262	{ 0xa1ac, 0x14ff13ff },						\
263	{ 0xa1b0, 0x16ff15ff },						\
264	{ 0xa1b4, 0x19ff17ff },						\
265	{ 0xa1b8, 0x1bff1aff },						\
266	{ 0xa1bc, 0x1eff1dff },						\
267	{ 0xa1c0, 0x23ff20ff },						\
268	{ 0xa1c4, 0x27ff25ff },						\
269	{ 0xa1c8, 0x2cff29ff },						\
270	{ 0xa1cc, 0x31ff2fff },						\
271	{ 0xa1d0, 0x37ff34ff },						\
272	{ 0xa1d4, 0x3aff3aff },						\
273	{ 0xa1d8, 0x3aff3aff },						\
274	{ 0xa1dc, 0x3aff3aff },						\
275	{ 0xa1e0, 0x3aff3aff },						\
276	{ 0xa1e4, 0x3aff3aff },						\
277	{ 0xa1e8, 0x3aff3aff },						\
278	{ 0xa1ec, 0x3aff3aff },						\
279	{ 0xa1f0, 0x3aff3aff },						\
280	{ 0xa1f4, 0x3aff3aff },						\
281	{ 0xa1f8, 0x3aff3aff },						\
282	{ 0xa1fc, 0x3aff3aff },						\
283        /* BB gain table (64bytes) */					\
284	{ 0x9b00, 0x00000000 },						\
285	{ 0x9b04, 0x00000020 },						\
286	{ 0x9b08, 0x00000010 },						\
287	{ 0x9b0c, 0x00000030 },						\
288	{ 0x9b10, 0x00000008 },						\
289	{ 0x9b14, 0x00000028 },						\
290	{ 0x9b18, 0x00000004 },						\
291	{ 0x9b1c, 0x00000024 },						\
292	{ 0x9b20, 0x00000014 },						\
293	{ 0x9b24, 0x00000034 },						\
294	{ 0x9b28, 0x0000000c },						\
295	{ 0x9b2c, 0x0000002c },						\
296	{ 0x9b30, 0x00000002 },						\
297	{ 0x9b34, 0x00000022 },						\
298	{ 0x9b38, 0x00000012 },						\
299	{ 0x9b3c, 0x00000032 },						\
300	{ 0x9b40, 0x0000000a },						\
301	{ 0x9b44, 0x0000002a },						\
302	{ 0x9b48, 0x00000006 },						\
303	{ 0x9b4c, 0x00000026 },						\
304	{ 0x9b50, 0x00000016 },						\
305	{ 0x9b54, 0x00000036 },						\
306	{ 0x9b58, 0x0000000e },						\
307	{ 0x9b5c, 0x0000002e },						\
308	{ 0x9b60, 0x00000001 },						\
309	{ 0x9b64, 0x00000021 },						\
310	{ 0x9b68, 0x00000011 },						\
311	{ 0x9b6c, 0x00000031 },						\
312	{ 0x9b70, 0x00000009 },						\
313	{ 0x9b74, 0x00000029 },						\
314	{ 0x9b78, 0x00000005 },						\
315	{ 0x9b7c, 0x00000025 },						\
316	{ 0x9b80, 0x00000015 },						\
317	{ 0x9b84, 0x00000035 },						\
318	{ 0x9b88, 0x0000000d },						\
319	{ 0x9b8c, 0x0000002d },						\
320	{ 0x9b90, 0x00000003 },						\
321	{ 0x9b94, 0x00000023 },						\
322	{ 0x9b98, 0x00000013 },						\
323	{ 0x9b9c, 0x00000033 },						\
324	{ 0x9ba0, 0x0000000b },						\
325	{ 0x9ba4, 0x0000002b },						\
326	{ 0x9ba8, 0x0000002b },						\
327	{ 0x9bac, 0x0000002b },						\
328	{ 0x9bb0, 0x0000002b },						\
329	{ 0x9bb4, 0x0000002b },						\
330	{ 0x9bb8, 0x0000002b },						\
331	{ 0x9bbc, 0x0000002b },						\
332	{ 0x9bc0, 0x0000002b },						\
333	{ 0x9bc4, 0x0000002b },						\
334	{ 0x9bc8, 0x0000002b },						\
335	{ 0x9bcc, 0x0000002b },						\
336	{ 0x9bd0, 0x0000002b },						\
337	{ 0x9bd4, 0x0000002b },						\
338	{ 0x9bd8, 0x0000002b },						\
339	{ 0x9bdc, 0x0000002b },						\
340	{ 0x9be0, 0x0000002b },						\
341	{ 0x9be4, 0x0000002b },						\
342	{ 0x9be8, 0x0000002b },						\
343	{ 0x9bec, 0x0000002b },						\
344	{ 0x9bf0, 0x0000002b },						\
345	{ 0x9bf4, 0x0000002b },						\
346	{ 0x9bf8, 0x00000002 },						\
347	{ 0x9bfc, 0x00000016 },						\
348        /* PHY activation */						\
349	{ 0x98d4, 0x00000020 },						\
350        { 0x98d8, 0x00601068 },						\
351}
352
353struct ar5k_ar5211_ini_mode {
354	u_int16_t	mode_register;
355	u_int32_t	mode_value[4];
356};
357
358#define AR5K_AR5211_INI_MODE {						\
359	{ 0x0030, { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } },	\
360	{ 0x1040, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },	\
361	{ 0x1044, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },	\
362	{ 0x1048, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },	\
363	{ 0x104c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },	\
364	{ 0x1050, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },	\
365	{ 0x1054, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },	\
366	{ 0x1058, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },	\
367	{ 0x105c, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },	\
368	{ 0x1060, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },	\
369	{ 0x1064, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },	\
370	{ 0x1070, { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } },	\
371	{ 0x1030, { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } },	\
372	{ 0x10b0, { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } },	\
373	{ 0x10f0, { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } },	\
374	{ 0x8014, { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } },	\
375	{ 0x801c, { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } },	\
376	{ 0x9804, { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } },	\
377	{ 0x9820, { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } },	\
378	{ 0x9824, { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } },	\
379	{ 0x9828, { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } },	\
380	{ 0x9834, { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },	\
381	{ 0x9838, { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } },	\
382	{ 0x9844, { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } },	\
383	{ 0x9848, { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } },	\
384	{ 0x9850, { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },	\
385	{ 0x9858, { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },	\
386	{ 0x985c, { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } },	\
387	{ 0x9860, { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } },	\
388	{ 0x9864, { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },	\
389	{ 0x9914, { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } },	\
390	{ 0x9918, { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } },	\
391	{ 0x9944, { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } },	\
392	{ 0xa180, { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },	\
393	{ 0x98d4, { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } },	\
394}
395
396#endif /* _AR5K_AR5211_VAR_H */
397