ar5211reg.h revision 1.2
1/* $OpenBSD: ar5211reg.h,v 1.2 2005/03/10 08:30:56 reyk Exp $ */ 2 3/* 4 * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19/* 20 * Known registers of the Atheros AR5001 Wireless LAN chipsets 21 * (AR5211/AR5311). 22 */ 23 24#ifndef _AR5K_AR5211_REG_H 25#define _AR5K_AR5211_REG_H 26 27/* 28 * Command register 29 */ 30#define AR5K_AR5211_CR 0x0008 31#define AR5K_AR5211_CR_RXE 0x00000004 32#define AR5K_AR5211_CR_RXD 0x00000020 33#define AR5K_AR5211_CR_SWI 0x00000040 34 35/* 36 * Receive queue descriptor pointer register 37 */ 38#define AR5K_AR5211_RXDP 0x000c 39 40/* 41 * Configuration and status register 42 */ 43#define AR5K_AR5211_CFG 0x0014 44#define AR5K_AR5211_CFG_SWTD 0x00000001 45#define AR5K_AR5211_CFG_SWTB 0x00000002 46#define AR5K_AR5211_CFG_SWRD 0x00000004 47#define AR5K_AR5211_CFG_SWRB 0x00000008 48#define AR5K_AR5211_CFG_SWRG 0x00000010 49#define AR5K_AR5211_CFG_ADHOC 0x00000020 50#define AR5K_AR5211_CFG_PHY_OK 0x00000100 51#define AR5K_AR5211_CFG_EEBS 0x00000200 52#define AR5K_AR5211_CFG_CLKGD 0x00000400 53#define AR5K_AR5211_CFG_PCI_THRES 0x00060000 54#define AR5K_AR5211_CFG_PCI_THRES_S 17 55 56/* 57 * Interrupt enable register 58 */ 59#define AR5K_AR5211_IER 0x0024 60#define AR5K_AR5211_IER_DISABLE 0x00000000 61#define AR5K_AR5211_IER_ENABLE 0x00000001 62 63/* 64 * First RTS duration register 65 */ 66#define AR5K_AR5211_RTSD0 0x0028 67#define AR5K_AR5211_RTSD0_6 0x000000ff 68#define AR5K_AR5211_RTSD0_6_S 0 69#define AR5K_AR5211_RTSD0_9 0x0000ff00 70#define AR5K_AR5211_RTSD0_9_S 8 71#define AR5K_AR5211_RTSD0_12 0x00ff0000 72#define AR5K_AR5211_RTSD0_12_S 16 73#define AR5K_AR5211_RTSD0_18 0xff000000 74#define AR5K_AR5211_RTSD0_18_S 24 75 76/* 77 * Second RTS duration register 78 */ 79#define AR5K_AR5211_RTSD1 0x002c 80#define AR5K_AR5211_RTSD1_24 0x000000ff 81#define AR5K_AR5211_RTSD1_24_S 0 82#define AR5K_AR5211_RTSD1_36 0x0000ff00 83#define AR5K_AR5211_RTSD1_36_S 8 84#define AR5K_AR5211_RTSD1_48 0x00ff0000 85#define AR5K_AR5211_RTSD1_48_S 16 86#define AR5K_AR5211_RTSD1_54 0xff000000 87#define AR5K_AR5211_RTSD1_54_S 24 88 89/* 90 * Transmit configuration register 91 */ 92#define AR5K_AR5211_TXCFG 0x0030 93#define AR5K_AR5211_TXCFG_SDMAMR 0x00000007 94#define AR5K_AR5211_TXCFG_B_MODE 0x00000008 95#define AR5K_AR5211_TXCFG_TXFULL 0x000003f0 96#define AR5K_AR5211_TXCFG_TXFULL_S 4 97#define AR5K_AR5211_TXCFG_TXFULL_0B 0x00000000 98#define AR5K_AR5211_TXCFG_TXFULL_64B 0x00000010 99#define AR5K_AR5211_TXCFG_TXFULL_128B 0x00000020 100#define AR5K_AR5211_TXCFG_TXFULL_192B 0x00000030 101#define AR5K_AR5211_TXCFG_TXFULL_256B 0x00000040 102#define AR5K_AR5211_TXCFG_TXCONT_ENABLE 0x00000080 103#define AR5K_AR5211_TXCFG_JUMBO_TXE 0x00000400 104#define AR5K_AR5211_TXCFG_RTSRND 0x00001000 105#define AR5K_AR5211_TXCFG_FRMPAD_DIS 0x00002000 106#define AR5K_AR5211_TXCFG_RDY_DIS 0x00004000 107 108/* 109 * Receive configuration register 110 */ 111#define AR5K_AR5211_RXCFG 0x0034 112#define AR5K_AR5211_RXCFG_SDMAMW 0x00000007 113#define AR5K_AR5311_RXCFG_DEFAULT_ANTENNA 0x00000008 114#define AR5K_AR5211_RXCFG_ZLFDMA 0x00000010 115#define AR5K_AR5211_RXCFG_JUMBO_RXE 0x00000020 116#define AR5K_AR5211_RXCFG_JUMBO_WRAP 0x00000040 117 118/* 119 * Receive jumbo descriptor last address register 120 */ 121#define AR5K_AR5211_RXJLA 0x0038 122 123/* 124 * MIB control register 125 */ 126#define AR5K_AR5211_MIBC 0x0040 127#define AR5K_AR5211_MIBC_COW 0x00000001 128#define AR5K_AR5211_MIBC_FMC 0x00000002 129#define AR5K_AR5211_MIBC_CMC 0x00000004 130#define AR5K_AR5211_MIBC_MCS 0x00000008 131 132/* 133 * Timeout prescale register 134 */ 135#define AR5K_AR5211_TOPS 0x0044 136#define AR5K_AR5211_TOPS_M 0x0000ffff 137 138/* 139 * Receive timeout register (no frame received) 140 */ 141#define AR5K_AR5211_RXNOFRM 0x0048 142#define AR5K_AR5211_RXNOFRM_M 0x000003ff 143 144/* 145 * Transmit timeout register (no frame sent) 146 */ 147#define AR5K_AR5211_TXNOFRM 0x004c 148#define AR5K_AR5211_TXNOFRM_M 0x000003ff 149#define AR5K_AR5211_TXNOFRM_QCU 0x000ffc00 150 151/* 152 * Receive frame gap timeout register 153 */ 154#define AR5K_AR5211_RPGTO 0x0050 155#define AR5K_AR5211_RPGTO_M 0x000003ff 156 157/* 158 * Receive frame count limit register 159 */ 160#define AR5K_AR5211_RFCNT 0x0054 161#define AR5K_AR5211_RFCNT_M 0x0000001f 162 163/* 164 * Misc settings register 165 */ 166#define AR5K_AR5211_MISC 0x0058 167#define AR5K_AR5211_MISC_DMA_OBS_M 0x000001e0 168#define AR5K_AR5211_MISC_DMA_OBS_S 5 169#define AR5K_AR5211_MISC_MISC_OBS_M 0x00000e00 170#define AR5K_AR5211_MISC_MISC_OBS_S 9 171#define AR5K_AR5211_MISC_MAC_OBS_LSB_M 0x00007000 172#define AR5K_AR5211_MISC_MAC_OBS_LSB_S 12 173#define AR5K_AR5211_MISC_MAC_OBS_MSB_M 0x00038000 174#define AR5K_AR5211_MISC_MAC_OBS_MSB_S 15 175 176/* 177 * QCU/DCU clock gating register 178 */ 179#define AR5K_AR5311_QCUDCU_CLKGT 180#define AR5K_AR5311_QCUDCU_CLKGT_QCU 0x0000ffff 181#define AR5K_AR5311_QCUDCU_CLKGT_DCU 0x07ff0000 182 183/* 184 * Primary interrupt status register 185 */ 186#define AR5K_AR5211_PISR 0x0080 187#define AR5K_AR5211_PISR_RXOK 0x00000001 188#define AR5K_AR5211_PISR_RXDESC 0x00000002 189#define AR5K_AR5211_PISR_RXERR 0x00000004 190#define AR5K_AR5211_PISR_RXNOFRM 0x00000008 191#define AR5K_AR5211_PISR_RXEOL 0x00000010 192#define AR5K_AR5211_PISR_RXORN 0x00000020 193#define AR5K_AR5211_PISR_TXOK 0x00000040 194#define AR5K_AR5211_PISR_TXDESC 0x00000080 195#define AR5K_AR5211_PISR_TXERR 0x00000100 196#define AR5K_AR5211_PISR_TXNOFRM 0x00000200 197#define AR5K_AR5211_PISR_TXEOL 0x00000400 198#define AR5K_AR5211_PISR_TXURN 0x00000800 199#define AR5K_AR5211_PISR_MIB 0x00001000 200#define AR5K_AR5211_PISR_SWI 0x00002000 201#define AR5K_AR5211_PISR_RXPHY 0x00004000 202#define AR5K_AR5211_PISR_RXKCM 0x00008000 203#define AR5K_AR5211_PISR_SWBA 0x00010000 204#define AR5K_AR5211_PISR_BRSSI 0x00020000 205#define AR5K_AR5211_PISR_BMISS 0x00040000 206#define AR5K_AR5211_PISR_HIUERR 0x00080000 207#define AR5K_AR5211_PISR_BNR 0x00100000 208#define AR5K_AR5211_PISR_TIM 0x00800000 209#define AR5K_AR5211_PISR_GPIO 0x01000000 210#define AR5K_AR5211_PISR_QCBRORN 0x02000000 211#define AR5K_AR5211_PISR_QCBRURN 0x04000000 212#define AR5K_AR5211_PISR_QTRIG 0x08000000 213 214/* 215 * Secondary interrupt status registers (0 - 4) 216 */ 217#define AR5K_AR5211_SISR0 0x0084 218#define AR5K_AR5211_SISR0_QCU_TXOK 0x000003ff 219#define AR5K_AR5211_SISR0_QCU_TXDESC 0x03ff0000 220 221#define AR5K_AR5211_SISR1 0x0088 222#define AR5K_AR5211_SISR1_QCU_TXERR 0x000003ff 223#define AR5K_AR5211_SISR1_QCU_TXEOL 0x03ff0000 224 225#define AR5K_AR5211_SISR2 0x008c 226#define AR5K_AR5211_SISR2_QCU_TXURN 0x000003ff 227#define AR5K_AR5211_SISR2_MCABT 0x00100000 228#define AR5K_AR5211_SISR2_SSERR 0x00200000 229#define AR5K_AR5211_SISR2_DPERR 0x00400000 230 231#define AR5K_AR5211_SISR3 0x0090 232#define AR5K_AR5211_SISR3_QCBRORN 0x000003ff 233#define AR5K_AR5211_SISR3_QCBRURN 0x03ff0000 234 235#define AR5K_AR5211_SISR4 0x0094 236#define AR5K_AR5211_SISR4_QTRIG 0x000003ff 237 238/* 239 * Shadow read-and-clear interrupt status registers 240 */ 241#define AR5K_AR5211_RAC_PISR 0x00c0 242#define AR5K_AR5211_RAC_SISR0 0x00c4 243#define AR5K_AR5211_RAC_SISR1 0x00c8 244#define AR5K_AR5211_RAC_SISR2 0x00cc 245#define AR5K_AR5211_RAC_SISR3 0c00d0 246#define AR5K_AR5211_RAC_SISR4 0c00d4 247 248/* 249 * Primary interrupt mask register 250 */ 251#define AR5K_AR5211_PIMR 0x00a0 252#define AR5K_AR5211_PIMR_RXOK 0x00000001 253#define AR5K_AR5211_PIMR_RXDESC 0x00000002 254#define AR5K_AR5211_PIMR_RXERR 0x00000004 255#define AR5K_AR5211_PIMR_RXNOFRM 0x00000008 256#define AR5K_AR5211_PIMR_RXEOL 0x00000010 257#define AR5K_AR5211_PIMR_RXORN 0x00000020 258#define AR5K_AR5211_PIMR_TXOK 0x00000040 259#define AR5K_AR5211_PIMR_TXDESC 0x00000080 260#define AR5K_AR5211_PIMR_TXERR 0x00000100 261#define AR5K_AR5211_PIMR_TXNOFRM 0x00000200 262#define AR5K_AR5211_PIMR_TXEOL 0x00000400 263#define AR5K_AR5211_PIMR_TXURN 0x00000800 264#define AR5K_AR5211_PIMR_MIB 0x00001000 265#define AR5K_AR5211_PIMR_SWI 0x00002000 266#define AR5K_AR5211_PIMR_RXPHY 0x00004000 267#define AR5K_AR5211_PIMR_RXKCM 0x00008000 268#define AR5K_AR5211_PIMR_SWBA 0x00010000 269#define AR5K_AR5211_PIMR_BRSSI 0x00020000 270#define AR5K_AR5211_PIMR_BMISS 0x00040000 271#define AR5K_AR5211_PIMR_HIUERR 0x00080000 272#define AR5K_AR5211_PIMR_BNR 0x00100000 273#define AR5K_AR5211_PIMR_TIM 0x00800000 274#define AR5K_AR5211_PIMR_GPIO 0x01000000 275#define AR5K_AR5211_PIMR_QCBRORN 0x02000000 276#define AR5K_AR5211_PIMR_QCBRURN 0x04000000 277#define AR5K_AR5211_PIMR_QTRIG 0x08000000 278 279/* 280 * Secondary interrupt mask registers (0 - 4) 281 */ 282#define AR5K_AR5211_SIMR0 0x00a4 283#define AR5K_AR5211_SIMR0_QCU_TXOK 0x000003ff 284#define AR5K_AR5211_SIMR0_QCU_TXOK_S 0 285#define AR5K_AR5211_SIMR0_QCU_TXDESC 0x03ff0000 286#define AR5K_AR5211_SIMR0_QCU_TXDESC_S 16 287 288#define AR5K_AR5211_SIMR1 0x00a8 289#define AR5K_AR5211_SIMR1_QCU_TXERR 0x000003ff 290#define AR5K_AR5211_SIMR1_QCU_TXERR_S 0 291#define AR5K_AR5211_SIMR1_QCU_TXEOL 0x03ff0000 292#define AR5K_AR5211_SIMR1_QCU_TXEOL_S 16 293 294#define AR5K_AR5211_SIMR2 0x00ac 295#define AR5K_AR5211_SIMR2_QCU_TXURN 0x000003ff 296#define AR5K_AR5211_SIMR2_QCU_TXURN_S 0 297#define AR5K_AR5211_SIMR2_MCABT 0x00100000 298#define AR5K_AR5211_SIMR2_SSERR 0x00200000 299#define AR5K_AR5211_SIMR2_DPERR 0x00400000 300 301#define AR5K_AR5211_SIMR3 0x00b0 302#define AR5K_AR5211_SIMR3_QCBRORN 0x000003ff 303#define AR5K_AR5211_SIMR3_QCBRORN_S 0 304#define AR5K_AR5211_SIMR3_QCBRURN 0x03ff0000 305#define AR5K_AR5211_SIMR3_QCBRURN_S 16 306 307#define AR5K_AR5211_SIMR4 0x00b4 308#define AR5K_AR5211_SIMR4_QTRIG 0x000003ff 309#define AR5K_AR5211_SIMR4_QTRIG_S 0 310 311/* 312 * Queue control unit (QCU) registers (0 - 9) 313 */ 314#define AR5K_AR5211_QCU(_n, _a) (((_n) << 2) + _a) 315 316/* 317 * QCU Transmit descriptor pointer registers 318 */ 319#define AR5K_AR5211_QCU_TXDP(_n) AR5K_AR5211_QCU(_n, 0x0800) 320 321/* 322 * QCU Transmit enable register 323 */ 324#define AR5K_AR5211_QCU_TXE 0x0840 325 326/* 327 * QCU Transmit disable register 328 */ 329#define AR5K_AR5211_QCU_TXD 0x0880 330 331/* 332 * QCU CBR configuration registers 333 */ 334#define AR5K_AR5211_QCU_CBRCFG(_n) AR5K_AR5211_QCU(_n, 0x08c0) 335#define AR5K_AR5211_QCU_CBRCFG_INTVAL 0x00ffffff 336#define AR5K_AR5211_QCU_CBRCFG_INTVAL_S 0 337#define AR5K_AR5211_QCU_CBRCFG_ORN_THRES 0xff000000 338#define AR5K_AR5211_QCU_CBRCFG_ORN_THRES_S 24 339 340/* 341 * QCU Ready time configuration registers 342 */ 343#define AR5K_AR5211_QCU_RDYTIMECFG(_n) AR5K_AR5211_QCU(_n, 0x0900) 344#define AR5K_AR5211_QCU_RDYTIMECFG_INTVAL 0x00ffffff 345#define AR5K_AR5211_QCU_RDYTIMECFG_INTVAL_S 0 346#define AR5K_AR5211_QCU_RDYTIMECFG_DURATION 0x00ffffff 347#define AR5K_AR5211_QCU_RDYTIMECFG_ENABLE 0x01000000 348 349/* 350 * QCU one shot arm set registers 351 */ 352#define AR5K_AR5211_QCU_ONESHOTARMS(_n) AR5K_AR5211_QCU(_n, 0x0940) 353#define AR5K_AR5211_QCU_ONESHOTARMS_M 0x0000ffff 354 355/* 356 * QCU one shot arm clear registers 357 */ 358#define AR5K_AR5211_QCU_ONESHOTARMC(_n) AR5K_AR5211_QCU(_n, 0x0980) 359#define AR5K_AR5211_QCU_ONESHOTARMC_M 0x0000ffff 360 361/* 362 * QCU misc registers 363 */ 364#define AR5K_AR5211_QCU_MISC(_n) AR5K_AR5211_QCU(_n, 0x09c0) 365#define AR5K_AR5211_QCU_MISC_FRSHED_M 0x0000000f 366#define AR5K_AR5211_QCU_MISC_FRSHED_ASAP 0 367#define AR5K_AR5211_QCU_MISC_FRSHED_CBR 1 368#define AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT 2 369#define AR5K_AR5211_QCU_MISC_FRSHED_TIM_GT 3 370#define AR5K_AR5211_QCU_MISC_FRSHED_BCN_SENT_GT 4 371#define AR5K_AR5211_QCU_MISC_ONESHOT_ENABLE 0x00000010 372#define AR5K_AR5211_QCU_MISC_CBREXP 0x00000020 373#define AR5K_AR5211_QCU_MISC_CBREXP_BCN 0x00000040 374#define AR5K_AR5211_QCU_MISC_BCN_ENABLE 0x00000080 375#define AR5K_AR5211_QCU_MISC_CBR_THRES_ENABLE 0x00000100 376#define AR5K_AR5211_QCU_MISC_TXE 0x00000200 377#define AR5K_AR5211_QCU_MISC_CBR 0x00000400 378#define AR5K_AR5211_QCU_MISC_DCU_EARLY 0x00000800 379 380/* 381 * QCU status registers 382 */ 383#define AR5K_AR5211_QCU_STS(_n) AR5K_AR5211_QCU(_n, 0x0a00) 384#define AR5K_AR5211_QCU_STS_FRMPENDCNT 0x00000003 385#define AR5K_AR5211_QCU_STS_CBREXPCNT 0x0000ff00 386 387/* 388 * QCU ready time shutdown register 389 */ 390#define AR5K_AR5211_QCU_RDYTIMESHDN 0x0a40 391#define AR5K_AR5211_QCU_RDYTIMESHDN_M 0x000003ff 392 393/* 394 * DCF control unit (DCU) registers (0 - 9) 395 */ 396#define AR5K_AR5211_DCU(_n, _a) AR5K_AR5211_QCU(_n, _a) 397 398/* 399 * DCU QCU mask registers 400 */ 401#define AR5K_AR5211_DCU_QCUMASK(_n) AR5K_AR5211_DCU(_n, 0x1000) 402#define AR5K_AR5211_DCU_QCUMASK_M 0x000003ff 403 404/* 405 * DCU local IFS settings register 406 */ 407#define AR5K_AR5211_DCU_LCL_IFS(_n) AR5K_AR5211_DCU(_n, 0x1040) 408#define AR5K_AR5211_DCU_LCL_IFS_CW_MIN 0x000003ff 409#define AR5K_AR5211_DCU_LCL_IFS_CW_MIN_S 0 410#define AR5K_AR5211_DCU_LCL_IFS_CW_MAX 0x000ffc00 411#define AR5K_AR5211_DCU_LCL_IFS_CW_MAX_S 10 412#define AR5K_AR5211_DCU_LCL_IFS_AIFS 0x0ff00000 413#define AR5K_AR5211_DCU_LCL_IFS_AIFS_S 20 414 415/* 416 * DCU retry limit registers 417 */ 418#define AR5K_AR5211_DCU_RETRY_LMT(_n) AR5K_AR5211_DCU(_n, 0x1080) 419#define AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY 0x0000000f 420#define AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY_S 0 421#define AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY 0x000000f0 422#define AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY_S 4 423#define AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 424#define AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY_S 8 425#define AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 426#define AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY_S 14 427 428/* 429 * DCU channel time registers 430 */ 431#define AR5K_AR5211_DCU_CHAN_TIME(_n) AR5K_AR5211_DCU(_n, 0x10c0) 432#define AR5K_AR5211_DCU_CHAN_TIME_ENABLE 0x00100000 433#define AR5K_AR5211_DCU_CHAN_TIME_DUR 0x000fffff 434#define AR5K_AR5211_DCU_CHAN_TIME_DUR_S 0 435 436/* 437 * DCU misc registers 438 */ 439#define AR5K_AR5211_DCU_MISC(_n) AR5K_AR5211_DCU(_n, 0x1100) 440#define AR5K_AR5211_DCU_MISC_BACKOFF 0x000007ff 441#define AR5K_AR5211_DCU_MISC_BACKOFF_FRAG 0x00000200 442#define AR5K_AR5211_DCU_MISC_HCFPOLL_ENABLE 0x00000800 443#define AR5K_AR5211_DCU_MISC_BACKOFF_PERSIST 0x00001000 444#define AR5K_AR5211_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 445#define AR5K_AR5211_DCU_MISC_VIRTCOL 0x0000c000 446#define AR5K_AR5211_DCU_MISC_VIRTCOL_NORMAL 0 447#define AR5K_AR5211_DCU_MISC_VIRTCOL_MODIFIED 1 448#define AR5K_AR5211_DCU_MISC_VIRTCOL_IGNORE 2 449#define AR5K_AR5211_DCU_MISC_BCN_ENABLE 0x00010000 450#define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL 0x00060000 451#define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_S 17 452#define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_NONE 0 453#define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_INTFRM 1 454#define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 455#define AR5K_AR5211_DCU_MISC_ARBLOCK_IGNORE 0x00080000 456#define AR5K_AR5211_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 457#define AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 458#define AR5K_AR5211_DCU_MISC_VIRT_COLL_POLICY 0x00400000 459#define AR5K_AR5211_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 460#define AR5K_AR5211_DCU_MISC_SEQNUM_CTL 0x01000000 461 462/* 463 * DCU frame sequence number registers 464 */ 465#define AR5K_AR5211_DCU_SEQNUM(_n) AR5K_AR5211_DCU(_n, 0x1140) 466#define AR5K_AR5211_DCU_SEQNUM_M 0x00000fff 467/* 468 * DCU global IFS SIFS registers 469 */ 470#define AR5K_AR5211_DCU_GBL_IFS_SIFS 0x1030 471#define AR5K_AR5211_DCU_GBL_IFS_SIFS_M 0x0000ffff 472 473/* 474 * DCU global IFS slot interval registers 475 */ 476#define AR5K_AR5211_DCU_GBL_IFS_SLOT 0x1070 477#define AR5K_AR5211_DCU_GBL_IFS_SLOT_M 0x0000ffff 478 479/* 480 * DCU global IFS EIFS registers 481 */ 482#define AR5K_AR5211_DCU_GBL_IFS_EIFS 0x10b0 483#define AR5K_AR5211_DCU_GBL_IFS_EIFS_M 0x0000ffff 484 485/* 486 * DCU global IFS misc registers 487 */ 488#define AR5K_AR5211_DCU_GBL_IFS_MISC 0x10f0 489#define AR5K_AR5211_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 490#define AR5K_AR5211_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 491#define AR5K_AR5211_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 492#define AR5K_AR5211_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 493#define AR5K_AR5211_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 494 495/* 496 * DCU frame prefetch control register 497 */ 498#define AR5K_AR5211_DCU_FP 0x1230 499 500/* 501 * DCU transmit pause control/status register 502 */ 503#define AR5K_AR5211_DCU_TXP 0x1270 504#define AR5K_AR5211_DCU_TXP_M 0x000003ff 505#define AR5K_AR5211_DCU_TXP_STATUS 0x00010000 506 507/* 508 * DCU transmit filter register 509 */ 510#define AR5K_AR5211_DCU_TX_FILTER 0x1038 511 512/* 513 * DCU clear transmit filter register 514 */ 515#define AR5K_AR5211_DCU_TX_FILTER_CLR 0x143c 516 517/* 518 * DCU set transmit filter register 519 */ 520#define AR5K_AR5211_DCU_TX_FILTER_SET 0x147c 521 522/* 523 * DMA size definitions 524 */ 525typedef enum { 526 AR5K_AR5211_DMASIZE_4B = 0, 527 AR5K_AR5211_DMASIZE_8B, 528 AR5K_AR5211_DMASIZE_16B, 529 AR5K_AR5211_DMASIZE_32B, 530 AR5K_AR5211_DMASIZE_64B, 531 AR5K_AR5211_DMASIZE_128B, 532 AR5K_AR5211_DMASIZE_256B, 533 AR5K_AR5211_DMASIZE_512B 534} ar5k_ar5211_dmasize_t; 535 536/* 537 * Reset control register 538 */ 539#define AR5K_AR5211_RC 0x4000 540#define AR5K_AR5211_RC_PCU 0x00000001 541#define AR5K_AR5211_RC_BB 0x00000002 542#define AR5K_AR5211_RC_PCI 0x00000010 543#define AR5K_AR5211_RC_CHIP ( \ 544 AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB | AR5K_AR5211_RC_PCI \ 545) 546 547/* 548 * Sleep control register 549 */ 550#define AR5K_AR5211_SCR 0x4004 551#define AR5K_AR5211_SCR_SLDUR 0x0000ffff 552#define AR5K_AR5211_SCR_SLDUR_S 0 553#define AR5K_AR5211_SCR_SLE 0x00030000 554#define AR5K_AR5211_SCR_SLE_S 16 555#define AR5K_AR5211_SCR_SLE_WAKE 0x00000000 556#define AR5K_AR5211_SCR_SLE_SLP 0x00010000 557#define AR5K_AR5211_SCR_SLE_ALLOW 0x00020000 558#define AR5K_AR5211_SCR_SLE_UNITS 0x00000008 559 560/* 561 * Interrupt pending register 562 */ 563#define AR5K_AR5211_INTPEND 0x4008 564#define AR5K_AR5211_INTPEND_M 0x00000001 565 566/* 567 * Sleep force register 568 */ 569#define AR5K_AR5211_SFR 0x400c 570#define AR5K_AR5211_SFR_M 0x00000001 571 572/* 573 * PCI configuration register 574 */ 575#define AR5K_AR5211_PCICFG 0x4010 576#define AR5K_AR5211_PCICFG_CLKRUNEN 0x00000004 577#define AR5K_AR5211_PCICFG_EESIZE 0x00000018 578#define AR5K_AR5211_PCICFG_EESIZE_S 3 579#define AR5K_AR5211_PCICFG_EESIZE_4K 0 580#define AR5K_AR5211_PCICFG_EESIZE_8K 1 581#define AR5K_AR5211_PCICFG_EESIZE_16K 2 582#define AR5K_AR5211_PCICFG_EESIZE_FAIL 3 583#define AR5K_AR5211_PCICFG_LED 0x00000060 584#define AR5K_AR5211_PCICFG_LED_NONE 0x00000000 585#define AR5K_AR5211_PCICFG_LED_PEND 0x00000020 586#define AR5K_AR5211_PCICFG_LED_ASSOC 0x00000040 587#define AR5K_AR5211_PCICFG_BUS_SEL 0x00000380 588#define AR5K_AR5211_PCICFG_CBEFIX_DIS 0x00000400 589#define AR5K_AR5211_PCICFG_SL_INTEN 0x00000800 590#define AR5K_AR5211_PCICFG_SL_INPEN 0x00002800 591#define AR5K_AR5211_PCICFG_SPWR_DN 0x00010000 592#define AR5K_AR5211_PCICFG_LEDMODE 0x000e0000 593#define AR5K_AR5211_PCICFG_LEDMODE_PROP 0x00000000 594#define AR5K_AR5211_PCICFG_LEDMODE_PROM 0x00020000 595#define AR5K_AR5211_PCICFG_LEDMODE_PWR 0x00040000 596#define AR5K_AR5211_PCICFG_LEDMODE_RAND 0x00060000 597#define AR5K_AR5211_PCICFG_LEDBLINK 0x00700000 598#define AR5K_AR5211_PCICFG_LEDBLINK_S 20 599#define AR5K_AR5211_PCICFG_LEDSLOW 0x00800000 600 601/* 602 * "General Purpose Input/Output" (GPIO) control register 603 */ 604#define AR5K_AR5211_GPIOCR 0x4014 605#define AR5K_AR5211_GPIOCR_INT_ENA 0x00008000 606#define AR5K_AR5211_GPIOCR_INT_SELL 0x00000000 607#define AR5K_AR5211_GPIOCR_INT_SELH 0x00010000 608#define AR5K_AR5211_GPIOCR_NONE(n) (0 << ((n) * 2)) 609#define AR5K_AR5211_GPIOCR_OUT0(n) (1 << ((n) * 2)) 610#define AR5K_AR5211_GPIOCR_OUT1(n) (2 << ((n) * 2)) 611#define AR5K_AR5211_GPIOCR_ALL(n) (3 << ((n) * 2)) 612#define AR5K_AR5211_GPIOCR_INT_SEL(n) ((n) << 12) 613 614#define AR5K_AR5211_NUM_GPIO 6 615 616/* 617 * "General Purpose Input/Output" (GPIO) data output register 618 */ 619#define AR5K_AR5211_GPIODO 0x4018 620 621/* 622 * "General Purpose Input/Output" (GPIO) data input register 623 */ 624#define AR5K_AR5211_GPIODI 0x401c 625#define AR5K_AR5211_GPIODI_M 0x0000002f 626 627/* 628 * Silicon revision register 629 */ 630#define AR5K_AR5211_SREV 0x4020 631#define AR5K_AR5211_SREV_M 0x000000ff 632#define AR5K_AR5211_SREV_REVISION 0x0000000f 633#define AR5K_AR5211_SREV_VERSION 0x000000f0 634 635/* 636 * EEPROM access registers 637 */ 638#define AR5K_AR5211_EEPROM_BASE 0x6000 639#define AR5K_AR5211_EEPROM_DATA 0x6004 640#define AR5K_AR5211_EEPROM_CMD 0x6008 641#define AR5K_AR5211_EEPROM_CMD_READ 0x00000001 642#define AR5K_AR5211_EEPROM_CMD_WRITE 0x00000002 643#define AR5K_AR5211_EEPROM_CMD_RESET 0x00000004 644#define AR5K_AR5211_EEPROM_STATUS 0x600c 645#define AR5K_AR5211_EEPROM_STAT_RDERR 0x00000001 646#define AR5K_AR5211_EEPROM_STAT_RDDONE 0x00000002 647#define AR5K_AR5211_EEPROM_STAT_WRERR 0x00000004 648#define AR5K_AR5211_EEPROM_STAT_WRDONE 0x00000008 649#define AR5K_AR5211_EEPROM_CFG 0x6010 650 651/* 652 * AR5211 EEPROM data registers 653 */ 654#define AR5K_AR5211_EEPROM_MAGIC 0x3d 655#define AR5K_AR5211_EEPROM_MAGIC_VALUE 0x5aa5 656#define AR5K_AR5211_EEPROM_PROTECT 0x3f 657#define AR5K_AR5211_EEPROM_PROTECT_128_191 0x80 658#define AR5K_AR5211_EEPROM_REG_DOMAIN 0xbf 659#define AR5K_AR5211_EEPROM_INFO_BASE 0xc0 660#define AR5K_AR5211_EEPROM_INFO_VERSION \ 661 (AR5K_AR5211_EEPROM_INFO_BASE + 1) 662#define AR5K_AR5211_EEPROM_INFO_MAX \ 663 (0x400 - AR5K_AR5211_EEPROM_INFO_BASE) 664 665/* 666 * PCU registers 667 */ 668 669#define AR5K_AR5211_PCU_MIN 0x8000 670#define AR5K_AR5211_PCU_MAX 0x8fff 671 672/* 673 * First station id register (MAC address in lower 32 bits) 674 */ 675#define AR5K_AR5211_STA_ID0 0x8000 676 677/* 678 * Second station id register (MAC address in upper 16 bits) 679 */ 680#define AR5K_AR5211_STA_ID1 0x8004 681#define AR5K_AR5211_STA_ID1_AP 0x00010000 682#define AR5K_AR5211_STA_ID1_ADHOC 0x00020000 683#define AR5K_AR5211_STA_ID1_PWR_SV 0x00040000 684#define AR5K_AR5211_STA_ID1_NO_KEYSRCH 0x00080000 685#define AR5K_AR5211_STA_ID1_PCF 0x00100000 686#define AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA 0x00200000 687#define AR5K_AR5211_STA_ID1_DESC_ANTENNA 0x00400000 688#define AR5K_AR5211_STA_ID1_RTS_DEFAULT_ANTENNA 0x00800000 689#define AR5K_AR5211_STA_ID1_ACKCTS_6MB 0x01000000 690#define AR5K_AR5211_STA_ID1_BASE_RATE_11B 0x02000000 691 692/* 693 * First BSSID register (MAC address, lower 32bits) 694 */ 695#define AR5K_AR5211_BSS_ID0 0x8008 696 697/* 698 * Second BSSID register (MAC address in upper 16 bits) 699 * 700 * AID: Association ID 701 */ 702#define AR5K_AR5211_BSS_ID1 0x800c 703#define AR5K_AR5211_BSS_ID1_AID 0xffff0000 704#define AR5K_AR5211_BSS_ID1_AID_S 16 705 706/* 707 * Backoff slot time register 708 */ 709#define AR5K_AR5211_SLOT_TIME 0x8010 710 711/* 712 * ACK/CTS timeout register 713 */ 714#define AR5K_AR5211_TIME_OUT 0x8014 715#define AR5K_AR5211_TIME_OUT_ACK 0x00001fff 716#define AR5K_AR5211_TIME_OUT_ACK_S 0 717#define AR5K_AR5211_TIME_OUT_CTS 0x1fff0000 718#define AR5K_AR5211_TIME_OUT_CTS_S 16 719 720/* 721 * RSSI threshold register 722 */ 723#define AR5K_AR5211_RSSI_THR 0x8018 724#define AR5K_AR5211_RSSI_THR_M 0x000000ff 725#define AR5K_AR5211_RSSI_THR_BMISS 0x0000ff00 726#define AR5K_AR5211_RSSI_THR_BMISS_S 8 727 728/* 729 * Transmit latency register 730 */ 731#define AR5K_AR5211_USEC 0x801c 732#define AR5K_AR5211_USEC_1 0x0000007f 733#define AR5K_AR5211_USEC_1_S 0 734#define AR5K_AR5211_USEC_32 0x00003f80 735#define AR5K_AR5211_USEC_32_S 7 736#define AR5K_AR5211_USEC_TX_LATENCY 0x007fc000 737#define AR5K_AR5211_USEC_TX_LATENCY_S 14 738#define AR5K_AR5211_USEC_RX_LATENCY 0x1f800000 739#define AR5K_AR5211_USEC_RX_LATENCY_S 23 740#define AR5K_AR5311_USEC_TX_LATENCY 0x000fc000 741#define AR5K_AR5311_USEC_TX_LATENCY_S 14 742#define AR5K_AR5311_USEC_RX_LATENCY 0x03f00000 743#define AR5K_AR5311_USEC_RX_LATENCY_S 20 744 745/* 746 * PCU beacon control register 747 */ 748#define AR5K_AR5211_BEACON 0x8020 749#define AR5K_AR5211_BEACON_PERIOD 0x0000ffff 750#define AR5K_AR5211_BEACON_PERIOD_S 0 751#define AR5K_AR5211_BEACON_TIM 0x007f0000 752#define AR5K_AR5211_BEACON_TIM_S 16 753#define AR5K_AR5211_BEACON_ENABLE 0x00800000 754#define AR5K_AR5211_BEACON_RESET_TSF 0x01000000 755 756/* 757 * CFP period register 758 */ 759#define AR5K_AR5211_CFP_PERIOD 0x8024 760 761/* 762 * Next beacon time register 763 */ 764#define AR5K_AR5211_TIMER0 0x8028 765 766/* 767 * Next DMA beacon alert register 768 */ 769#define AR5K_AR5211_TIMER1 0x802c 770 771/* 772 * Next software beacon alert register 773 */ 774#define AR5K_AR5211_TIMER2 0x8030 775 776/* 777 * Next ATIM window time register 778 */ 779#define AR5K_AR5211_TIMER3 0x8034 780 781/* 782 * CFP duration register 783 */ 784#define AR5K_AR5211_CFP_DUR 0x8038 785 786/* 787 * Receive filter register 788 */ 789#define AR5K_AR5211_RX_FILTER 0x803c 790#define AR5K_AR5211_RX_FILTER_UNICAST 0x00000001 791#define AR5K_AR5211_RX_FILTER_MULTICAST 0x00000002 792#define AR5K_AR5211_RX_FILTER_BROADCAST 0x00000004 793#define AR5K_AR5211_RX_FILTER_CONTROL 0x00000008 794#define AR5K_AR5211_RX_FILTER_BEACON 0x00000010 795#define AR5K_AR5211_RX_FILTER_PROMISC 0x00000020 796#define AR5K_AR5211_RX_FILTER_PHYERR 0x00000040 797#define AR5K_AR5211_RX_FILTER_RADARERR 0x00000080 798 799/* 800 * Multicast filter register (lower 32 bits) 801 */ 802#define AR5K_AR5211_MCAST_FIL0 0x8040 803 804/* 805 * Multicast filter register (higher 16 bits) 806 */ 807#define AR5K_AR5211_MCAST_FIL1 0x8044 808 809/* 810 * PCU control register 811 */ 812#define AR5K_AR5211_DIAG_SW 0x8048 813#define AR5K_AR5211_DIAG_SW_DIS_WEP_ACK 0x00000001 814#define AR5K_AR5211_DIAG_SW_DIS_ACK 0x00000002 815#define AR5K_AR5211_DIAG_SW_DIS_CTS 0x00000004 816#define AR5K_AR5211_DIAG_SW_DIS_ENC 0x00000008 817#define AR5K_AR5211_DIAG_SW_DIS_DEC 0x00000010 818#define AR5K_AR5211_DIAG_SW_DIS_RX 0x00000020 819#define AR5K_AR5211_DIAG_SW_LOOP_BACK 0x00000040 820#define AR5K_AR5211_DIAG_SW_CORR_FCS 0x00000080 821#define AR5K_AR5211_DIAG_SW_CHAN_INFO 0x00000100 822#define AR5K_AR5211_DIAG_SW_EN_SCRAM_SEED 0x00000200 823#define AR5K_AR5211_DIAG_SW_ECO_ENABLE 0x00000400 824#define AR5K_AR5211_DIAG_SW_SCRAM_SEED_M 0x0001fc00 825#define AR5K_AR5211_DIAG_SW_SCRAM_SEED_S 10 826#define AR5K_AR5211_DIAG_SW_FRAME_NV0 0x00020000 827#define AR5K_AR5211_DIAG_SW_OBSPT_M 0x000c0000 828#define AR5K_AR5211_DIAG_SW_OBSPT_S 18 829 830/* 831 * TSF (clock) register (lower 32 bits) 832 */ 833#define AR5K_AR5211_TSF_L32 0x804c 834 835/* 836 * TSF (clock) register (higher 32 bits) 837 */ 838#define AR5K_AR5211_TSF_U32 0x8050 839 840/* 841 * ADDAC test register 842 */ 843#define AR5K_AR5211_ADDAC_TEST 0x8054 844 845/* 846 * Default antenna register 847 */ 848#define AR5K_AR5211_DEFAULT_ANTENNA 0x8058 849 850/* 851 * Last beacon timestamp register 852 */ 853#define AR5K_AR5211_LAST_TSTP 0x8080 854 855/* 856 * NAV register (current) 857 */ 858#define AR5K_AR5211_NAV 0x8084 859 860/* 861 * RTS success register 862 */ 863#define AR5K_AR5211_RTS_OK 0x8088 864 865/* 866 * RTS failure register 867 */ 868#define AR5K_AR5211_RTS_FAIL 0x808c 869 870/* 871 * ACK failure register 872 */ 873#define AR5K_AR5211_ACK_FAIL 0x8090 874 875/* 876 * FCS failure register 877 */ 878#define AR5K_AR5211_FCS_FAIL 0x8094 879 880/* 881 * Beacon count register 882 */ 883#define AR5K_AR5211_BEACON_CNT 0x8098 884 885/* 886 * Key table (WEP) register 887 */ 888#define AR5K_AR5211_KEYTABLE_0 0x8800 889#define AR5K_AR5211_KEYTABLE(n) (AR5K_AR5211_KEYTABLE_0 + ((n) * 32)) 890#define AR5K_AR5211_KEYTABLE_TYPE_40 0x00000000 891#define AR5K_AR5211_KEYTABLE_TYPE_104 0x00000001 892#define AR5K_AR5211_KEYTABLE_TYPE_128 0x00000003 893#define AR5K_AR5211_KEYTABLE_TYPE_AES 0x00000005 894#define AR5K_AR5211_KEYTABLE_TYPE_NULL 0x00000007 895#define AR5K_AR5211_KEYTABLE_VALID 0x00008000 896 897#define AR5K_AR5211_KEYTABLE_SIZE 64 898#define AR5K_AR5211_KEYCACHE_SIZE 8 899 900/* 901 * PHY register 902 */ 903#define AR5K_AR5211_PHY(_n) (0x9800 + ((_n) << 2)) 904#define AR5K_AR5211_PHY_SHIFT_2GHZ 0x00004007 905#define AR5K_AR5211_PHY_SHIFT_5GHZ 0x00000007 906 907/* 908 * PHY turbo mode register 909 */ 910#define AR5K_AR5211_PHY_TURBO 0x9804 911#define AR5K_AR5211_PHY_TURBO_MODE 0x00000001 912#define AR5K_AR5211_PHY_TURBO_SHORT 0x00000002 913 914/* 915 * PHY agility command register 916 */ 917#define AR5K_AR5211_PHY_AGC 0x9808 918#define AR5K_AR5211_PHY_AGC_DISABLE 0x08000000 919 920/* 921 * PHY chip revision register 922 */ 923#define AR5K_AR5211_PHY_CHIP_ID 0x9818 924 925/* 926 * PHY activation register 927 */ 928#define AR5K_AR5211_PHY_ACTIVE 0x981c 929#define AR5K_AR5211_PHY_ENABLE 0x00000001 930#define AR5K_AR5211_PHY_DISABLE 0x00000002 931 932/* 933 * PHY agility control register 934 */ 935#define AR5K_AR5211_PHY_AGCCTL 0x9860 936#define AR5K_AR5211_PHY_AGCCTL_CAL 0x00000001 937#define AR5K_AR5211_PHY_AGCCTL_NF 0x00000002 938 939/* 940 * PHY noise floor status register 941 */ 942#define AR5K_AR5211_PHY_NF 0x9864 943#define AR5K_AR5211_PHY_NF_M 0x000001ff 944#define AR5K_AR5211_PHY_NF_ACTIVE 0x00000100 945#define AR5K_AR5211_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_AR5211_PHY_NF_M) 946#define AR5K_AR5211_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_AR5211_PHY_NF_M) + 1) 947#define AR5K_AR5211_PHY_NF_SVAL(_n) (((_n) & AR5K_AR5211_PHY_NF_M) | (1 << 9)) 948 949/* 950 * PHY PLL control register 951 */ 952#define AR5K_AR5211_PHY_PLL 0x987c 953#define AR5K_AR5211_PHY_PLL_20MHZ 0x13 954#define AR5K_AR5211_PHY_PLL_40MHZ 0x18 955#define AR5K_AR5211_PHY_PLL_44MHZ 0x19 956 957/* 958 * PHY receiver delay register 959 */ 960#define AR5K_AR5211_PHY_RX_DELAY 0x9914 961#define AR5K_AR5211_PHY_RX_DELAY_M 0x00003fff 962 963/* 964 * PHY timing IQ control register 965 */ 966#define AR5K_AR5211_PHY_IQ 0x9920 967#define AR5K_AR5211_PHY_IQ_CORR_Q_Q_COFF 0x0000001f 968#define AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF 0x000007e0 969#define AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S 5 970#define AR5K_AR5211_PHY_IQ_CORR_ENABLE 0x00000800 971#define AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 972#define AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX_S 12 973#define AR5K_AR5211_PHY_IQ_RUN 0x00010000 974 975/* 976 * PHY PAPD probe register 977 */ 978#define AR5K_AR5211_PHY_PAPD_PROBE 0x9930 979#define AR5K_AR5211_PHY_PAPD_PROBE_TX_PWR 0x00007e00 980#define AR5K_AR5211_PHY_PAPD_PROBE_TX_PWR_S 9 981#define AR5K_AR5211_PHY_PAPD_PROBE_TX_NEXT 0x00008000 982#define AR5K_AR5211_PHY_PAPD_PROBE_GAINF 0xfe000000 983#define AR5K_AR5211_PHY_PAPD_PROBE_GAINF_S 25 984 985/* 986 * PHY frame control register 987 */ 988#define AR5K_AR5211_PHY_FC 0x9944 989#define AR5K_AR5211_PHY_FC_TX_CLIP 0x00000038 990#define AR5K_AR5211_PHY_FC_TX_CLIP_S 3 991 992/* 993 * PHY radar detection enable register 994 */ 995#define AR5K_AR5211_PHY_RADAR 0x9954 996#define AR5K_AR5211_PHY_RADAR_DISABLE 0x00000000 997#define AR5K_AR5211_PHY_RADAR_ENABLE 0x00000001 998 999/* 1000 * PHY antenna switch table registers 1001 */ 1002#define AR5K_AR5211_PHY_ANT_SWITCH_TABLE_0 0x9960 1003#define AR5K_AR5211_PHY_ANT_SWITCH_TABLE_1 0x9964 1004 1005/* 1006 * PHY timing IQ calibration result register 1007 */ 1008#define AR5K_AR5211_PHY_IQRES_CAL_PWR_I 0x9c10 1009#define AR5K_AR5211_PHY_IQRES_CAL_PWR_Q 0x9c14 1010#define AR5K_AR5211_PHY_IQRES_CAL_CORR 0x9c18 1011 1012/* 1013 * PHY current RSSI register 1014 */ 1015#define AR5K_AR5211_PHY_CURRENT_RSSI 0x9c1c 1016 1017/* 1018 * PHY mode register 1019 */ 1020#define AR5K_AR5211_PHY_MODE 0xa200 1021#define AR5K_AR5211_PHY_MODE_MOD 0x00000001 1022#define AR5K_AR5211_PHY_MODE_MOD_OFDM 0 1023#define AR5K_AR5211_PHY_MODE_MOD_CCK 1 1024#define AR5K_AR5211_PHY_MODE_FREQ 0x00000002 1025#define AR5K_AR5211_PHY_MODE_FREQ_5GHZ 0 1026#define AR5K_AR5211_PHY_MODE_FREQ_2GHZ 2 1027 1028/* 1029 * Misc PHY/radio registers 1030 */ 1031#define AR5K_AR5211_BB_GAIN(_n) (0x9b00 + ((_n) << 2)) 1032#define AR5K_AR5211_RF_GAIN(_n) (0x9a00 + ((_n) << 2)) 1033 1034#endif 1035