1/* $OpenBSD: ar5211.c,v 1.51 2022/01/09 05:42:38 jsg Exp $ */ 2 3/* 4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19/* 20 * HAL interface for the Atheros AR5001 Wireless LAN chipset 21 * (AR5211 + AR5111). 22 */ 23 24#include <dev/ic/ar5xxx.h> 25#include <dev/ic/ar5211reg.h> 26#include <dev/ic/ar5211var.h> 27 28HAL_BOOL ar5k_ar5211_nic_reset(struct ath_hal *, u_int32_t); 29HAL_BOOL ar5k_ar5211_nic_wakeup(struct ath_hal *, u_int16_t); 30u_int16_t ar5k_ar5211_radio_revision(struct ath_hal *, HAL_CHIP); 31void ar5k_ar5211_fill(struct ath_hal *); 32HAL_BOOL ar5k_ar5211_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int, 33 u_int); 34 35/* 36 * Initial register setting for the AR5211 37 */ 38static const struct ar5k_ini ar5211_ini[] = 39 AR5K_AR5211_INI; 40static const struct ar5k_ar5211_ini_mode ar5211_mode[] = 41 AR5K_AR5211_INI_MODE; 42static const struct ar5k_ar5211_ini_rf ar5211_rf[] = 43 AR5K_AR5211_INI_RF; 44 45AR5K_HAL_FUNCTIONS(extern, ar5k_ar5211,); 46 47void 48ar5k_ar5211_fill(struct ath_hal *hal) 49{ 50 hal->ah_magic = AR5K_AR5211_MAGIC; 51 52 /* 53 * Init/Exit functions 54 */ 55 AR5K_HAL_FUNCTION(hal, ar5211, get_rate_table); 56 AR5K_HAL_FUNCTION(hal, ar5211, detach); 57 58 /* 59 * Reset functions 60 */ 61 AR5K_HAL_FUNCTION(hal, ar5211, reset); 62 AR5K_HAL_FUNCTION(hal, ar5211, set_opmode); 63 AR5K_HAL_FUNCTION(hal, ar5211, calibrate); 64 65 /* 66 * TX functions 67 */ 68 AR5K_HAL_FUNCTION(hal, ar5211, update_tx_triglevel); 69 AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queue); 70 AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queueprops); 71 AR5K_HAL_FUNCTION(hal, ar5211, release_tx_queue); 72 AR5K_HAL_FUNCTION(hal, ar5211, reset_tx_queue); 73 AR5K_HAL_FUNCTION(hal, ar5211, get_tx_buf); 74 AR5K_HAL_FUNCTION(hal, ar5211, put_tx_buf); 75 AR5K_HAL_FUNCTION(hal, ar5211, tx_start); 76 AR5K_HAL_FUNCTION(hal, ar5211, stop_tx_dma); 77 AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_desc); 78 AR5K_HAL_FUNCTION(hal, ar5211, setup_xtx_desc); 79 AR5K_HAL_FUNCTION(hal, ar5211, fill_tx_desc); 80 AR5K_HAL_FUNCTION(hal, ar5211, proc_tx_desc); 81 AR5K_HAL_FUNCTION(hal, ar5211, has_veol); 82 83 /* 84 * RX functions 85 */ 86 AR5K_HAL_FUNCTION(hal, ar5211, get_rx_buf); 87 AR5K_HAL_FUNCTION(hal, ar5211, put_rx_buf); 88 AR5K_HAL_FUNCTION(hal, ar5211, start_rx); 89 AR5K_HAL_FUNCTION(hal, ar5211, stop_rx_dma); 90 AR5K_HAL_FUNCTION(hal, ar5211, start_rx_pcu); 91 AR5K_HAL_FUNCTION(hal, ar5211, stop_pcu_recv); 92 AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filter); 93 AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filterindex); 94 AR5K_HAL_FUNCTION(hal, ar5211, clear_mcast_filter_idx); 95 AR5K_HAL_FUNCTION(hal, ar5211, get_rx_filter); 96 AR5K_HAL_FUNCTION(hal, ar5211, set_rx_filter); 97 AR5K_HAL_FUNCTION(hal, ar5211, setup_rx_desc); 98 AR5K_HAL_FUNCTION(hal, ar5211, proc_rx_desc); 99 AR5K_HAL_FUNCTION(hal, ar5211, set_rx_signal); 100 101 /* 102 * Misc functions 103 */ 104 AR5K_HAL_FUNCTION(hal, ar5211, dump_state); 105 AR5K_HAL_FUNCTION(hal, ar5211, get_diag_state); 106 AR5K_HAL_FUNCTION(hal, ar5211, get_lladdr); 107 AR5K_HAL_FUNCTION(hal, ar5211, set_lladdr); 108 AR5K_HAL_FUNCTION(hal, ar5211, set_regdomain); 109 AR5K_HAL_FUNCTION(hal, ar5211, set_ledstate); 110 AR5K_HAL_FUNCTION(hal, ar5211, set_associd); 111 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_input); 112 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_output); 113 AR5K_HAL_FUNCTION(hal, ar5211, get_gpio); 114 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio); 115 AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_intr); 116 AR5K_HAL_FUNCTION(hal, ar5211, get_tsf32); 117 AR5K_HAL_FUNCTION(hal, ar5211, get_tsf64); 118 AR5K_HAL_FUNCTION(hal, ar5211, reset_tsf); 119 AR5K_HAL_FUNCTION(hal, ar5211, get_regdomain); 120 AR5K_HAL_FUNCTION(hal, ar5211, detect_card_present); 121 AR5K_HAL_FUNCTION(hal, ar5211, update_mib_counters); 122 AR5K_HAL_FUNCTION(hal, ar5211, get_rf_gain); 123 AR5K_HAL_FUNCTION(hal, ar5211, set_slot_time); 124 AR5K_HAL_FUNCTION(hal, ar5211, get_slot_time); 125 AR5K_HAL_FUNCTION(hal, ar5211, set_ack_timeout); 126 AR5K_HAL_FUNCTION(hal, ar5211, get_ack_timeout); 127 AR5K_HAL_FUNCTION(hal, ar5211, set_cts_timeout); 128 AR5K_HAL_FUNCTION(hal, ar5211, get_cts_timeout); 129 130 /* 131 * Key table (WEP) functions 132 */ 133 AR5K_HAL_FUNCTION(hal, ar5211, is_cipher_supported); 134 AR5K_HAL_FUNCTION(hal, ar5211, get_keycache_size); 135 AR5K_HAL_FUNCTION(hal, ar5211, reset_key); 136 AR5K_HAL_FUNCTION(hal, ar5211, is_key_valid); 137 AR5K_HAL_FUNCTION(hal, ar5211, set_key); 138 AR5K_HAL_FUNCTION(hal, ar5211, set_key_lladdr); 139 AR5K_HAL_FUNCTION(hal, ar5211, softcrypto); 140 141 /* 142 * Power management functions 143 */ 144 AR5K_HAL_FUNCTION(hal, ar5211, set_power); 145 AR5K_HAL_FUNCTION(hal, ar5211, get_power_mode); 146 AR5K_HAL_FUNCTION(hal, ar5211, query_pspoll_support); 147 AR5K_HAL_FUNCTION(hal, ar5211, init_pspoll); 148 AR5K_HAL_FUNCTION(hal, ar5211, enable_pspoll); 149 AR5K_HAL_FUNCTION(hal, ar5211, disable_pspoll); 150 151 /* 152 * Beacon functions 153 */ 154 AR5K_HAL_FUNCTION(hal, ar5211, init_beacon); 155 AR5K_HAL_FUNCTION(hal, ar5211, set_beacon_timers); 156 AR5K_HAL_FUNCTION(hal, ar5211, reset_beacon); 157 AR5K_HAL_FUNCTION(hal, ar5211, wait_for_beacon); 158 159 /* 160 * Interrupt functions 161 */ 162 AR5K_HAL_FUNCTION(hal, ar5211, is_intr_pending); 163 AR5K_HAL_FUNCTION(hal, ar5211, get_isr); 164 AR5K_HAL_FUNCTION(hal, ar5211, get_intr); 165 AR5K_HAL_FUNCTION(hal, ar5211, set_intr); 166 167 /* 168 * Chipset functions (ar5k-specific, non-HAL) 169 */ 170 AR5K_HAL_FUNCTION(hal, ar5211, get_capabilities); 171 AR5K_HAL_FUNCTION(hal, ar5211, radar_alert); 172 173 /* 174 * EEPROM access 175 */ 176 AR5K_HAL_FUNCTION(hal, ar5211, eeprom_is_busy); 177 AR5K_HAL_FUNCTION(hal, ar5211, eeprom_read); 178 AR5K_HAL_FUNCTION(hal, ar5211, eeprom_write); 179 180 /* 181 * Unused functions or functions not implemented 182 */ 183 AR5K_HAL_FUNCTION(hal, ar5211, get_tx_queueprops); 184 AR5K_HAL_FUNCTION(hal, ar5211, num_tx_pending); 185 AR5K_HAL_FUNCTION(hal, ar5211, phy_disable); 186 AR5K_HAL_FUNCTION(hal, ar5211, set_txpower_limit); 187 AR5K_HAL_FUNCTION(hal, ar5211, set_def_antenna); 188 AR5K_HAL_FUNCTION(hal, ar5211, get_def_antenna); 189 AR5K_HAL_FUNCTION(hal, ar5211, set_bssid_mask); 190#ifdef notyet 191 AR5K_HAL_FUNCTION(hal, ar5211, set_capability); 192 AR5K_HAL_FUNCTION(hal, ar5211, proc_mib_event); 193 AR5K_HAL_FUNCTION(hal, ar5211, get_tx_inter_queue); 194#endif 195} 196 197struct ath_hal * 198ar5k_ar5211_attach(u_int16_t device, void *sc, bus_space_tag_t st, 199 bus_space_handle_t sh, int *status) 200{ 201 struct ath_hal *hal = (struct ath_hal*) sc; 202 u_int8_t mac[IEEE80211_ADDR_LEN]; 203 u_int32_t srev; 204 205 ar5k_ar5211_fill(hal); 206 207 /* Bring device out of sleep and reset its units */ 208 if (ar5k_ar5211_nic_wakeup(hal, AR5K_INIT_MODE) != AH_TRUE) 209 return (NULL); 210 211 /* Get MAC, PHY and RADIO revisions */ 212 srev = AR5K_REG_READ(AR5K_AR5211_SREV); 213 hal->ah_mac_srev = srev; 214 hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5211_SREV_VER); 215 hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5211_SREV_REV); 216 hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5211_PHY_CHIP_ID) & 217 0x00ffffffff; 218 hal->ah_radio_5ghz_revision = 219 ar5k_ar5211_radio_revision(hal, HAL_CHIP_5GHZ); 220 hal->ah_radio_2ghz_revision = 0; 221 222 /* Identify the chipset (this has to be done in an early step) */ 223 hal->ah_version = AR5K_AR5211; 224 hal->ah_radio = AR5K_AR5111; 225 hal->ah_phy = AR5K_AR5211_PHY(0); 226 227 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); 228 ar5k_ar5211_set_associd(hal, mac, 0, 0); 229 ar5k_ar5211_get_lladdr(hal, mac); 230 ar5k_ar5211_set_opmode(hal); 231 232 return (hal); 233} 234 235HAL_BOOL 236ar5k_ar5211_nic_reset(struct ath_hal *hal, u_int32_t val) 237{ 238 HAL_BOOL ret = AH_FALSE; 239 u_int32_t mask = val ? val : ~0; 240 241 /* Read-and-clear */ 242 AR5K_REG_READ(AR5K_AR5211_RXDP); 243 244 /* 245 * Reset the device and wait until success 246 */ 247 AR5K_REG_WRITE(AR5K_AR5211_RC, val); 248 249 /* Wait at least 128 PCI clocks */ 250 AR5K_DELAY(15); 251 252 val &= 253 AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB; 254 255 mask &= 256 AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB; 257 258 ret = ar5k_register_timeout(hal, AR5K_AR5211_RC, mask, val, AH_FALSE); 259 260 /* 261 * Reset configuration register 262 */ 263 if ((val & AR5K_AR5211_RC_PCU) == 0) 264 AR5K_REG_WRITE(AR5K_AR5211_CFG, AR5K_AR5211_INIT_CFG); 265 266 return (ret); 267} 268 269HAL_BOOL 270ar5k_ar5211_nic_wakeup(struct ath_hal *hal, u_int16_t flags) 271{ 272 u_int32_t turbo, mode, clock; 273 274 turbo = 0; 275 mode = 0; 276 clock = 0; 277 278 /* 279 * Get channel mode flags 280 */ 281 282 if (flags & IEEE80211_CHAN_2GHZ) { 283 mode |= AR5K_AR5211_PHY_MODE_FREQ_2GHZ; 284 clock |= AR5K_AR5211_PHY_PLL_44MHZ; 285 } else if (flags & IEEE80211_CHAN_5GHZ) { 286 mode |= AR5K_AR5211_PHY_MODE_FREQ_5GHZ; 287 clock |= AR5K_AR5211_PHY_PLL_40MHZ; 288 } else { 289 AR5K_PRINT("invalid radio frequency mode\n"); 290 return (AH_FALSE); 291 } 292 293 if ((flags & IEEE80211_CHAN_CCK) || 294 (flags & IEEE80211_CHAN_DYN)) { 295 /* Dynamic OFDM/CCK is not supported by the AR5211 */ 296 mode |= AR5K_AR5211_PHY_MODE_MOD_CCK; 297 } else if (flags & IEEE80211_CHAN_OFDM) { 298 mode |= AR5K_AR5211_PHY_MODE_MOD_OFDM; 299 } else { 300 AR5K_PRINT("invalid radio frequency mode\n"); 301 return (AH_FALSE); 302 } 303 304 /* 305 * Reset and wakeup the device 306 */ 307 308 /* ...reset chipset and PCI device */ 309 if (ar5k_ar5211_nic_reset(hal, 310 AR5K_AR5211_RC_CHIP | AR5K_AR5211_RC_PCI) == AH_FALSE) { 311 AR5K_PRINT("failed to reset the AR5211 + PCI chipset\n"); 312 return (AH_FALSE); 313 } 314 315 /* ...wakeup */ 316 if (ar5k_ar5211_set_power(hal, 317 HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) { 318 AR5K_PRINT("failed to resume the AR5211 (again)\n"); 319 return (AH_FALSE); 320 } 321 322 /* ...final warm reset */ 323 if (ar5k_ar5211_nic_reset(hal, 0) == AH_FALSE) { 324 AR5K_PRINT("failed to warm reset the AR5211\n"); 325 return (AH_FALSE); 326 } 327 328 /* ...set the PHY operating mode */ 329 AR5K_REG_WRITE(AR5K_AR5211_PHY_PLL, clock); 330 AR5K_DELAY(300); 331 332 AR5K_REG_WRITE(AR5K_AR5211_PHY_MODE, mode); 333 AR5K_REG_WRITE(AR5K_AR5211_PHY_TURBO, turbo); 334 335 return (AH_TRUE); 336} 337 338u_int16_t 339ar5k_ar5211_radio_revision(struct ath_hal *hal, HAL_CHIP chip) 340{ 341 int i; 342 u_int32_t srev; 343 u_int16_t ret; 344 345 /* 346 * Set the radio chip access register 347 */ 348 switch (chip) { 349 case HAL_CHIP_2GHZ: 350 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_2GHZ); 351 break; 352 case HAL_CHIP_5GHZ: 353 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); 354 break; 355 default: 356 return (0); 357 } 358 359 AR5K_DELAY(2000); 360 361 /* ...wait until PHY is ready and read the selected radio revision */ 362 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x34), 0x00001c16); 363 364 for (i = 0; i < 8; i++) 365 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x20), 0x00010000); 366 srev = (AR5K_REG_READ(AR5K_AR5211_PHY(0x100)) >> 24) & 0xff; 367 368 ret = ar5k_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8); 369 370 /* Reset to the 5GHz mode */ 371 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); 372 373 return (ret); 374} 375 376const HAL_RATE_TABLE * 377ar5k_ar5211_get_rate_table(struct ath_hal *hal, u_int mode) 378{ 379 switch (mode) { 380 case HAL_MODE_11A: 381 return (&hal->ah_rt_11a); 382 case HAL_MODE_11B: 383 return (&hal->ah_rt_11b); 384 case HAL_MODE_11G: 385 case HAL_MODE_PUREG: 386 return (&hal->ah_rt_11g); 387 default: 388 return (NULL); 389 } 390 391 return (NULL); 392} 393 394void 395ar5k_ar5211_detach(struct ath_hal *hal) 396{ 397 /* 398 * Free HAL structure, assume interrupts are down 399 */ 400 free(hal, M_DEVBUF, 0); 401} 402 403HAL_BOOL 404ar5k_ar5211_phy_disable(struct ath_hal *hal) 405{ 406 AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_DISABLE); 407 return (AH_TRUE); 408} 409 410HAL_BOOL 411ar5k_ar5211_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel, 412 HAL_BOOL change_channel, HAL_STATUS *status) 413{ 414 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 415 u_int8_t mac[IEEE80211_ADDR_LEN]; 416 u_int32_t data, s_seq, s_ant, s_led[3]; 417 u_int i, mode, freq, ee_mode, ant[2]; 418 419 /* Not used, keep for HAL compatibility */ 420 *status = HAL_OK; 421 422 /* 423 * Save some registers before a reset 424 */ 425 if (change_channel == AH_TRUE) { 426 s_seq = AR5K_REG_READ(AR5K_AR5211_DCU_SEQNUM(0)); 427 s_ant = AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA); 428 } else { 429 s_seq = 0; 430 s_ant = 1; 431 } 432 433 s_led[0] = AR5K_REG_READ(AR5K_AR5211_PCICFG) & 434 AR5K_AR5211_PCICFG_LEDSTATE; 435 s_led[1] = AR5K_REG_READ(AR5K_AR5211_GPIOCR); 436 s_led[2] = AR5K_REG_READ(AR5K_AR5211_GPIODO); 437 438 if (ar5k_ar5211_nic_wakeup(hal, channel->c_channel_flags) == AH_FALSE) 439 return (AH_FALSE); 440 441 /* 442 * Initialize operating mode 443 */ 444 hal->ah_op_mode = op_mode; 445 446 if ((channel->c_channel_flags & CHANNEL_A) == CHANNEL_A) { 447 mode = AR5K_INI_VAL_11A; 448 freq = AR5K_INI_RFGAIN_5GHZ; 449 ee_mode = AR5K_EEPROM_MODE_11A; 450 } else if ((channel->c_channel_flags & CHANNEL_B) == CHANNEL_B) { 451 if (hal->ah_capabilities.cap_mode & HAL_MODE_11B) { 452 mode = AR5K_INI_VAL_11B; 453 ee_mode = AR5K_EEPROM_MODE_11B; 454 } else { 455 mode = AR5K_INI_VAL_11G; 456 ee_mode = AR5K_EEPROM_MODE_11G; 457 } 458 freq = AR5K_INI_RFGAIN_2GHZ; 459 } else if ((channel->c_channel_flags & (CHANNEL_G | CHANNEL_PUREG)) == 460 (CHANNEL_G | CHANNEL_PUREG)) { 461 mode = AR5K_INI_VAL_11G; 462 freq = AR5K_INI_RFGAIN_2GHZ; 463 ee_mode = AR5K_EEPROM_MODE_11G; 464 } else { 465 AR5K_PRINTF("invalid channel: %d\n", channel->c_channel); 466 return (AH_FALSE); 467 } 468 469 /* PHY access enable */ 470 AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ); 471 472 /* 473 * Write initial RF registers 474 */ 475 if (ar5k_ar5211_rfregs(hal, channel, freq, ee_mode) == AH_FALSE) 476 return (AH_FALSE); 477 478 /* 479 * Write initial mode settings 480 */ 481 for (i = 0; i < nitems(ar5211_mode); i++) { 482 AR5K_REG_WAIT(i); 483 AR5K_REG_WRITE((u_int32_t)ar5211_mode[i].mode_register, 484 ar5211_mode[i].mode_value[mode]); 485 } 486 487 /* 488 * Write initial register settings 489 */ 490 for (i = 0; i < nitems(ar5211_ini); i++) { 491 if (change_channel == AH_TRUE && 492 ar5211_ini[i].ini_register >= AR5K_AR5211_PCU_MIN && 493 ar5211_ini[i].ini_register <= AR5K_AR5211_PCU_MAX) 494 continue; 495 496 AR5K_REG_WAIT(i); 497 AR5K_REG_WRITE((u_int32_t)ar5211_ini[i].ini_register, 498 ar5211_ini[i].ini_value); 499 } 500 501 /* 502 * Write initial RF gain settings 503 */ 504 if (ar5k_rfgain(hal, freq) == AH_FALSE) 505 return (AH_FALSE); 506 507 AR5K_DELAY(1000); 508 509 /* 510 * Configure additional registers 511 */ 512 513 if (hal->ah_radio == AR5K_AR5111) { 514 if (channel->c_channel_flags & IEEE80211_CHAN_B) 515 AR5K_REG_ENABLE_BITS(AR5K_AR5211_TXCFG, 516 AR5K_AR5211_TXCFG_B_MODE); 517 else 518 AR5K_REG_DISABLE_BITS(AR5K_AR5211_TXCFG, 519 AR5K_AR5211_TXCFG_B_MODE); 520 } 521 522 /* Set antenna mode */ 523 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x44), 524 hal->ah_antenna[ee_mode][0], 0xfffffc06); 525 526 if (freq == AR5K_INI_RFGAIN_2GHZ) 527 ant[0] = ant[1] = HAL_ANT_FIXED_B; 528 else 529 ant[0] = ant[1] = HAL_ANT_FIXED_A; 530 531 AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_0, 532 hal->ah_antenna[ee_mode][ant[0]]); 533 AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_1, 534 hal->ah_antenna[ee_mode][ant[1]]); 535 536 /* Commit values from EEPROM */ 537 AR5K_REG_WRITE_BITS(AR5K_AR5211_PHY_FC, 538 AR5K_AR5211_PHY_FC_TX_CLIP, ee->ee_tx_clip); 539 540 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x5a), 541 AR5K_AR5211_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode])); 542 543 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x11), 544 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f); 545 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x12), 546 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff); 547 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x14), 548 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | 549 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000); 550 551 AR5K_REG_WRITE(AR5K_AR5211_PHY(0x0d), 552 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | 553 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | 554 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | 555 (ee->ee_tx_frm2xpa_enable[ee_mode])); 556 557 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x0a), 558 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); 559 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x19), 560 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); 561 AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x49), 4, 0xffffff01); 562 563 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, 564 AR5K_AR5211_PHY_IQ_CORR_ENABLE | 565 (ee->ee_i_cal[ee_mode] << AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S) | 566 ee->ee_q_cal[ee_mode]); 567 568 /* 569 * Restore saved values 570 */ 571 AR5K_REG_WRITE(AR5K_AR5211_DCU_SEQNUM(0), s_seq); 572 AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, s_ant); 573 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, s_led[0]); 574 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, s_led[1]); 575 AR5K_REG_WRITE(AR5K_AR5211_GPIODO, s_led[2]); 576 577 /* 578 * Misc 579 */ 580 bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN); 581 ar5k_ar5211_set_associd(hal, mac, 0, 0); 582 ar5k_ar5211_set_opmode(hal); 583 AR5K_REG_WRITE(AR5K_AR5211_PISR, 0xffffffff); 584 AR5K_REG_WRITE(AR5K_AR5211_RSSI_THR, AR5K_TUNE_RSSI_THRES); 585 586 /* 587 * Set Rx/Tx DMA Configuration 588 */ 589 AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG, AR5K_AR5211_TXCFG_SDMAMR, 590 AR5K_AR5211_DMASIZE_512B | AR5K_AR5211_TXCFG_DMASIZE); 591 AR5K_REG_WRITE_BITS(AR5K_AR5211_RXCFG, AR5K_AR5211_RXCFG_SDMAMW, 592 AR5K_AR5211_DMASIZE_512B); 593 594 /* 595 * Set channel and calibrate the PHY 596 */ 597 if (ar5k_channel(hal, channel) == AH_FALSE) 598 return (AH_FALSE); 599 600 /* 601 * Enable the PHY and wait until completion 602 */ 603 AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_ENABLE); 604 605 data = AR5K_REG_READ(AR5K_AR5211_PHY_RX_DELAY) & 606 AR5K_AR5211_PHY_RX_DELAY_M; 607 data = (channel->c_channel_flags & IEEE80211_CHAN_CCK) ? 608 ((data << 2) / 22) : (data / 10); 609 610 AR5K_DELAY(100 + data); 611 612 /* 613 * Start calibration 614 */ 615 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL, 616 AR5K_AR5211_PHY_AGCCTL_NF | 617 AR5K_AR5211_PHY_AGCCTL_CAL); 618 619 if (channel->c_channel_flags & IEEE80211_CHAN_B) { 620 hal->ah_calibration = AH_FALSE; 621 } else { 622 hal->ah_calibration = AH_TRUE; 623 AR5K_REG_WRITE_BITS(AR5K_AR5211_PHY_IQ, 624 AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX, 15); 625 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, 626 AR5K_AR5211_PHY_IQ_RUN); 627 } 628 629 /* 630 * Reset queues and start beacon timers at the end of the reset routine 631 */ 632 for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) { 633 AR5K_REG_WRITE_Q(AR5K_AR5211_DCU_QCUMASK(i), i); 634 if (ar5k_ar5211_reset_tx_queue(hal, i) == AH_FALSE) { 635 AR5K_PRINTF("failed to reset TX queue #%d\n", i); 636 return (AH_FALSE); 637 } 638 } 639 640 /* Pre-enable interrupts */ 641 ar5k_ar5211_set_intr(hal, HAL_INT_RX | HAL_INT_TX | HAL_INT_FATAL); 642 643 /* 644 * Set RF kill flags if supported by the device (read from the EEPROM) 645 */ 646 if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) { 647 ar5k_ar5211_set_gpio_input(hal, 0); 648 if ((hal->ah_gpio[0] = ar5k_ar5211_get_gpio(hal, 0)) == 0) 649 ar5k_ar5211_set_gpio_intr(hal, 0, 1); 650 else 651 ar5k_ar5211_set_gpio_intr(hal, 0, 0); 652 } 653 654 /* 655 * Disable beacons and reset the register 656 */ 657 AR5K_REG_DISABLE_BITS(AR5K_AR5211_BEACON, 658 AR5K_AR5211_BEACON_ENABLE | AR5K_AR5211_BEACON_RESET_TSF); 659 660 return (AH_TRUE); 661} 662 663void 664ar5k_ar5211_set_def_antenna(struct ath_hal *hal, u_int ant) 665{ 666 AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, ant); 667} 668 669u_int 670ar5k_ar5211_get_def_antenna(struct ath_hal *hal) 671{ 672 return AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA); 673} 674 675void 676ar5k_ar5211_set_opmode(struct ath_hal *hal) 677{ 678 u_int32_t pcu_reg, low_id, high_id; 679 680 pcu_reg = 0; 681 682 switch (hal->ah_op_mode) { 683#ifndef IEEE80211_STA_ONLY 684 case IEEE80211_M_IBSS: 685 pcu_reg |= AR5K_AR5211_STA_ID1_ADHOC | 686 AR5K_AR5211_STA_ID1_DESC_ANTENNA; 687 break; 688 689 case IEEE80211_M_HOSTAP: 690 pcu_reg |= AR5K_AR5211_STA_ID1_AP | 691 AR5K_AR5211_STA_ID1_RTS_DEFAULT_ANTENNA; 692 break; 693#endif 694 695 case IEEE80211_M_STA: 696 case IEEE80211_M_MONITOR: 697 pcu_reg |= AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA; 698 break; 699 700 default: 701 return; 702 } 703 704 /* 705 * Set PCU registers 706 */ 707 low_id = AR5K_LOW_ID(hal->ah_sta_id); 708 high_id = AR5K_HIGH_ID(hal->ah_sta_id); 709 AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id); 710 AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, pcu_reg | high_id); 711 712 return; 713} 714 715HAL_BOOL 716ar5k_ar5211_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel) 717{ 718 u_int32_t i_pwr, q_pwr; 719 int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd; 720 721 if (hal->ah_calibration == AH_FALSE || 722 AR5K_REG_READ(AR5K_AR5211_PHY_IQ) & AR5K_AR5211_PHY_IQ_RUN) 723 goto done; 724 725 hal->ah_calibration = AH_FALSE; 726 727 iq_corr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_CORR); 728 i_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_I); 729 q_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_Q); 730 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 731 q_coffd = q_pwr >> 6; 732 733 if (i_coffd == 0 || q_coffd == 0) 734 goto done; 735 736 i_coff = ((-iq_corr) / i_coffd) & 0x3f; 737 q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f; 738 739 /* Commit new IQ value */ 740 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ, 741 AR5K_AR5211_PHY_IQ_CORR_ENABLE | 742 ((u_int32_t)q_coff) | 743 ((u_int32_t)i_coff << AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S)); 744 745 done: 746 /* Start noise floor calibration */ 747 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL, 748 AR5K_AR5211_PHY_AGCCTL_NF); 749 750 return (AH_TRUE); 751} 752 753/* 754 * Transmit functions 755 */ 756 757HAL_BOOL 758ar5k_ar5211_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase) 759{ 760 u_int32_t trigger_level, imr; 761 HAL_BOOL status = AH_FALSE; 762 763 /* 764 * Disable interrupts by setting the mask 765 */ 766 imr = ar5k_ar5211_set_intr(hal, hal->ah_imr & ~HAL_INT_GLOBAL); 767 768 trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TXCFG), 769 AR5K_AR5211_TXCFG_TXFULL); 770 771 if (increase == AH_FALSE) { 772 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) 773 goto done; 774 } else 775 trigger_level += 776 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); 777 778 /* 779 * Update trigger level on success 780 */ 781 AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG, 782 AR5K_AR5211_TXCFG_TXFULL, trigger_level); 783 status = AH_TRUE; 784 785 done: 786 /* 787 * Restore interrupt mask 788 */ 789 ar5k_ar5211_set_intr(hal, imr); 790 791 return (status); 792} 793 794int 795ar5k_ar5211_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type, 796 const HAL_TXQ_INFO *queue_info) 797{ 798 u_int queue; 799 800 /* 801 * Get queue by type 802 */ 803 if (queue_type == HAL_TX_QUEUE_DATA) { 804 for (queue = HAL_TX_QUEUE_ID_DATA_MIN; 805 hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE; 806 queue++) 807 if (queue > HAL_TX_QUEUE_ID_DATA_MAX) 808 return (-1); 809 } else if (queue_type == HAL_TX_QUEUE_PSPOLL) { 810 queue = HAL_TX_QUEUE_ID_PSPOLL; 811 } else if (queue_type == HAL_TX_QUEUE_BEACON) { 812 queue = HAL_TX_QUEUE_ID_BEACON; 813 } else if (queue_type == HAL_TX_QUEUE_CAB) { 814 queue = HAL_TX_QUEUE_ID_CAB; 815 } else 816 return (-1); 817 818 /* 819 * Setup internal queue structure 820 */ 821 bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); 822 hal->ah_txq[queue].tqi_type = queue_type; 823 824 if (queue_info != NULL) { 825 if (ar5k_ar5211_setup_tx_queueprops(hal, queue, queue_info) 826 != AH_TRUE) 827 return (-1); 828 } 829 830 AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue); 831 832 return (queue); 833} 834 835HAL_BOOL 836ar5k_ar5211_setup_tx_queueprops(struct ath_hal *hal, int queue, 837 const HAL_TXQ_INFO *queue_info) 838{ 839 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 840 841 if (hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE) 842 return (AH_FALSE); 843 844 bcopy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO)); 845 846 if (queue_info->tqi_type == HAL_TX_QUEUE_DATA && 847 (queue_info->tqi_subtype >= HAL_WME_AC_VI) && 848 (queue_info->tqi_subtype <= HAL_WME_UPSD)) 849 hal->ah_txq[queue].tqi_flags |= 850 AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; 851 852 return (AH_TRUE); 853} 854 855HAL_BOOL 856ar5k_ar5211_get_tx_queueprops(struct ath_hal *hal, int queue, 857 HAL_TXQ_INFO *queue_info) 858{ 859 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 860 bcopy(&hal->ah_txq[queue], queue_info, sizeof(HAL_TXQ_INFO)); 861 return (AH_TRUE); 862} 863 864HAL_BOOL 865ar5k_ar5211_release_tx_queue(struct ath_hal *hal, u_int queue) 866{ 867 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 868 869 /* This queue will be skipped in further operations */ 870 hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE; 871 AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue); 872 873 return (AH_FALSE); 874} 875 876HAL_BOOL 877ar5k_ar5211_reset_tx_queue(struct ath_hal *hal, u_int queue) 878{ 879 u_int32_t cw_min, cw_max, retry_lg, retry_sh; 880 struct ieee80211_channel *channel = (struct ieee80211_channel*) 881 &hal->ah_current_channel; 882 HAL_TXQ_INFO *tq; 883 884 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 885 886 tq = &hal->ah_txq[queue]; 887 888 if (tq->tqi_type == HAL_TX_QUEUE_INACTIVE) 889 return (AH_TRUE); 890 891 /* 892 * Set registers by channel mode 893 */ 894 if (IEEE80211_IS_CHAN_B(channel)) { 895 hal->ah_cw_min = AR5K_TUNE_CWMIN_11B; 896 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B; 897 hal->ah_aifs = AR5K_TUNE_AIFS_11B; 898 } else { 899 hal->ah_cw_min = AR5K_TUNE_CWMIN; 900 cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX; 901 hal->ah_aifs = AR5K_TUNE_AIFS; 902 } 903 904 /* 905 * Set retry limits 906 */ 907 if (hal->ah_software_retry == AH_TRUE) { 908 /* XXX Need to test this */ 909 retry_lg = hal->ah_limit_tx_retries; 910 retry_sh = retry_lg = 911 retry_lg > AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY ? 912 AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY : retry_lg; 913 } else { 914 retry_lg = AR5K_INIT_LG_RETRY; 915 retry_sh = AR5K_INIT_SH_RETRY; 916 } 917 918 AR5K_REG_WRITE(AR5K_AR5211_DCU_RETRY_LMT(queue), 919 AR5K_REG_SM(AR5K_INIT_SLG_RETRY, 920 AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY) | 921 AR5K_REG_SM(AR5K_INIT_SSH_RETRY, 922 AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY) | 923 AR5K_REG_SM(retry_lg, AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY) | 924 AR5K_REG_SM(retry_sh, AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY)); 925 926 /* 927 * Set initial content window (cw_min/cw_max) 928 */ 929 cw_min = 1; 930 while (cw_min < hal->ah_cw_min) 931 cw_min = (cw_min << 1) | 1; 932 933 cw_min = tq->tqi_cw_min < 0 ? 934 (cw_min >> (-tq->tqi_cw_min)) : 935 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); 936 cw_max = tq->tqi_cw_max < 0 ? 937 (cw_max >> (-tq->tqi_cw_max)) : 938 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); 939 940 AR5K_REG_WRITE(AR5K_AR5211_DCU_LCL_IFS(queue), 941 AR5K_REG_SM(cw_min, AR5K_AR5211_DCU_LCL_IFS_CW_MIN) | 942 AR5K_REG_SM(cw_max, AR5K_AR5211_DCU_LCL_IFS_CW_MAX) | 943 AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs, 944 AR5K_AR5211_DCU_LCL_IFS_AIFS)); 945 946 /* 947 * Set misc registers 948 */ 949 AR5K_REG_WRITE(AR5K_AR5211_QCU_MISC(queue), 950 AR5K_AR5211_QCU_MISC_DCU_EARLY); 951 952 if (tq->tqi_cbr_period) { 953 AR5K_REG_WRITE(AR5K_AR5211_QCU_CBRCFG(queue), 954 AR5K_REG_SM(tq->tqi_cbr_period, 955 AR5K_AR5211_QCU_CBRCFG_INTVAL) | 956 AR5K_REG_SM(tq->tqi_cbr_overflow_limit, 957 AR5K_AR5211_QCU_CBRCFG_ORN_THRES)); 958 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 959 AR5K_AR5211_QCU_MISC_FRSHED_CBR); 960 if (tq->tqi_cbr_overflow_limit) 961 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 962 AR5K_AR5211_QCU_MISC_CBR_THRES_ENABLE); 963 } 964 965 if (tq->tqi_ready_time) { 966 AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue), 967 AR5K_REG_SM(tq->tqi_ready_time, 968 AR5K_AR5211_QCU_RDYTIMECFG_INTVAL) | 969 AR5K_AR5211_QCU_RDYTIMECFG_ENABLE); 970 } 971 972 if (tq->tqi_burst_time) { 973 AR5K_REG_WRITE(AR5K_AR5211_DCU_CHAN_TIME(queue), 974 AR5K_REG_SM(tq->tqi_burst_time, 975 AR5K_AR5211_DCU_CHAN_TIME_DUR) | 976 AR5K_AR5211_DCU_CHAN_TIME_ENABLE); 977 978 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) { 979 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 980 AR5K_AR5211_QCU_MISC_TXE); 981 } 982 } 983 984 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) { 985 AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue), 986 AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS); 987 } 988 989 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { 990 AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue), 991 AR5K_AR5211_DCU_MISC_BACKOFF_FRAG); 992 } 993 994 /* 995 * Set registers by queue type 996 */ 997 switch (tq->tqi_type) { 998 case HAL_TX_QUEUE_BEACON: 999 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 1000 AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT | 1001 AR5K_AR5211_QCU_MISC_CBREXP_BCN | 1002 AR5K_AR5211_QCU_MISC_BCN_ENABLE); 1003 1004 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue), 1005 (AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL << 1006 AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL) | 1007 AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS | 1008 AR5K_AR5211_DCU_MISC_BCN_ENABLE); 1009 1010 AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue), 1011 ((AR5K_TUNE_BEACON_INTERVAL - 1012 (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) - 1013 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) | 1014 AR5K_AR5211_QCU_RDYTIMECFG_ENABLE); 1015 break; 1016 1017 case HAL_TX_QUEUE_CAB: 1018 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 1019 AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT | 1020 AR5K_AR5211_QCU_MISC_CBREXP | 1021 AR5K_AR5211_QCU_MISC_CBREXP_BCN); 1022 1023 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue), 1024 (AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL << 1025 AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL)); 1026 break; 1027 1028 case HAL_TX_QUEUE_PSPOLL: 1029 AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue), 1030 AR5K_AR5211_QCU_MISC_CBREXP); 1031 break; 1032 1033 case HAL_TX_QUEUE_DATA: 1034 default: 1035 break; 1036 } 1037 1038 /* 1039 * Enable tx queue in the secondary interrupt mask registers 1040 */ 1041 AR5K_REG_WRITE(AR5K_AR5211_SIMR0, 1042 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXOK) | 1043 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXDESC)); 1044 AR5K_REG_WRITE(AR5K_AR5211_SIMR1, 1045 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR1_QCU_TXERR)); 1046 AR5K_REG_WRITE(AR5K_AR5211_SIMR2, 1047 AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR2_QCU_TXURN)); 1048 1049 return (AH_TRUE); 1050} 1051 1052u_int32_t 1053ar5k_ar5211_get_tx_buf(struct ath_hal *hal, u_int queue) 1054{ 1055 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1056 1057 /* 1058 * Get the transmit queue descriptor pointer from the selected queue 1059 */ 1060 return (AR5K_REG_READ(AR5K_AR5211_QCU_TXDP(queue))); 1061} 1062 1063HAL_BOOL 1064ar5k_ar5211_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr) 1065{ 1066 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1067 1068 /* 1069 * Set the transmit queue descriptor pointer for the selected queue 1070 * (this won't work if the queue is still active) 1071 */ 1072 if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, queue)) 1073 return (AH_FALSE); 1074 1075 AR5K_REG_WRITE(AR5K_AR5211_QCU_TXDP(queue), phys_addr); 1076 1077 return (AH_TRUE); 1078} 1079 1080u_int32_t 1081ar5k_ar5211_num_tx_pending(struct ath_hal *hal, u_int queue) 1082{ 1083 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1084 return (AR5K_AR5211_QCU_STS(queue) & AR5K_AR5211_QCU_STS_FRMPENDCNT); 1085} 1086 1087HAL_BOOL 1088ar5k_ar5211_tx_start(struct ath_hal *hal, u_int queue) 1089{ 1090 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1091 1092 /* Return if queue is disabled */ 1093 if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXD, queue)) 1094 return (AH_FALSE); 1095 1096 /* Start queue */ 1097 AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXE, queue); 1098 1099 return (AH_TRUE); 1100} 1101 1102HAL_BOOL 1103ar5k_ar5211_stop_tx_dma(struct ath_hal *hal, u_int queue) 1104{ 1105 int i = 100, pending; 1106 1107 AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num); 1108 1109 /* 1110 * Schedule TX disable and wait until queue is empty 1111 */ 1112 AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXD, queue); 1113 1114 do { 1115 pending = AR5K_REG_READ(AR5K_AR5211_QCU_STS(queue)) & 1116 AR5K_AR5211_QCU_STS_FRMPENDCNT; 1117 delay(100); 1118 } while (--i && pending); 1119 1120 /* Clear register */ 1121 AR5K_REG_WRITE(AR5K_AR5211_QCU_TXD, 0); 1122 1123 return (AH_TRUE); 1124} 1125 1126HAL_BOOL 1127ar5k_ar5211_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1128 u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power, 1129 u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode, 1130 u_int flags, u_int rtscts_rate, u_int rtscts_duration) 1131{ 1132 struct ar5k_ar5211_tx_desc *tx_desc; 1133 1134 tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; 1135 1136 /* 1137 * Validate input 1138 */ 1139 if (tx_tries0 == 0) 1140 return (AH_FALSE); 1141 1142 if ((tx_desc->tx_control_0 = (packet_length & 1143 AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN)) != packet_length) 1144 return (AH_FALSE); 1145 1146 tx_desc->tx_control_0 |= 1147 AR5K_REG_SM(tx_rate0, AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE) | 1148 AR5K_REG_SM(antenna_mode, AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT); 1149 tx_desc->tx_control_1 = 1150 AR5K_REG_SM(type, AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE); 1151 1152#define _TX_FLAGS(_c, _flag) \ 1153 if (flags & HAL_TXDESC_##_flag) \ 1154 tx_desc->tx_control_##_c |= \ 1155 AR5K_AR5211_DESC_TX_CTL##_c##_##_flag 1156 1157 _TX_FLAGS(0, CLRDMASK); 1158 _TX_FLAGS(0, VEOL); 1159 _TX_FLAGS(0, INTREQ); 1160 _TX_FLAGS(0, RTSENA); 1161 _TX_FLAGS(1, NOACK); 1162 1163#undef _TX_FLAGS 1164 1165 /* 1166 * WEP crap 1167 */ 1168 if (key_index != HAL_TXKEYIX_INVALID) { 1169 tx_desc->tx_control_0 |= 1170 AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID; 1171 tx_desc->tx_control_1 |= 1172 AR5K_REG_SM(key_index, 1173 AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX); 1174 } 1175 1176 return (AH_TRUE); 1177} 1178 1179HAL_BOOL 1180ar5k_ar5211_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc, 1181 u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment) 1182{ 1183 struct ar5k_ar5211_tx_desc *tx_desc; 1184 1185 tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; 1186 1187 /* Clear status descriptor */ 1188 bzero(desc->ds_hw, sizeof(desc->ds_hw)); 1189 1190 /* Validate segment length and initialize the descriptor */ 1191 if (segment_length & ~AR5K_AR5211_DESC_TX_CTL1_BUF_LEN) 1192 return (AH_FALSE); 1193 tx_desc->tx_control_1 = 1194#if 0 1195 (tx_desc->tx_control_1 & ~AR5K_AR5211_DESC_TX_CTL1_BUF_LEN) | 1196#endif 1197 segment_length; 1198 1199 if (first_segment != AH_TRUE) 1200 tx_desc->tx_control_0 &= ~AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN; 1201 1202 if (last_segment != AH_TRUE) 1203 tx_desc->tx_control_1 |= AR5K_AR5211_DESC_TX_CTL1_MORE; 1204 1205 return (AH_TRUE); 1206} 1207 1208HAL_BOOL 1209ar5k_ar5211_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc, 1210 u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, 1211 u_int tx_rate3, u_int tx_tries3) 1212{ 1213 return (AH_FALSE); 1214} 1215 1216HAL_STATUS 1217ar5k_ar5211_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc) 1218{ 1219 struct ar5k_ar5211_tx_status *tx_status; 1220 struct ar5k_ar5211_tx_desc *tx_desc; 1221 1222 tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0; 1223 tx_status = (struct ar5k_ar5211_tx_status*)&desc->ds_hw[0]; 1224 1225 /* No frame has been send or error */ 1226 if ((tx_status->tx_status_1 & AR5K_AR5211_DESC_TX_STATUS1_DONE) == 0) 1227 return (HAL_EINPROGRESS); 1228 1229 /* 1230 * Get descriptor status 1231 */ 1232 desc->ds_us.tx.ts_tstamp = 1233 AR5K_REG_MS(tx_status->tx_status_0, 1234 AR5K_AR5211_DESC_TX_STATUS0_SEND_TIMESTAMP); 1235 desc->ds_us.tx.ts_shortretry = 1236 AR5K_REG_MS(tx_status->tx_status_0, 1237 AR5K_AR5211_DESC_TX_STATUS0_RTS_FAIL_COUNT); 1238 desc->ds_us.tx.ts_longretry = 1239 AR5K_REG_MS(tx_status->tx_status_0, 1240 AR5K_AR5211_DESC_TX_STATUS0_DATA_FAIL_COUNT); 1241 desc->ds_us.tx.ts_seqnum = 1242 AR5K_REG_MS(tx_status->tx_status_1, 1243 AR5K_AR5211_DESC_TX_STATUS1_SEQ_NUM); 1244 desc->ds_us.tx.ts_rssi = 1245 AR5K_REG_MS(tx_status->tx_status_1, 1246 AR5K_AR5211_DESC_TX_STATUS1_ACK_SIG_STRENGTH); 1247 desc->ds_us.tx.ts_antenna = 1; 1248 desc->ds_us.tx.ts_status = 0; 1249 desc->ds_us.tx.ts_rate = 1250 AR5K_REG_MS(tx_desc->tx_control_0, 1251 AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE); 1252 1253 if ((tx_status->tx_status_0 & 1254 AR5K_AR5211_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) { 1255 if (tx_status->tx_status_0 & 1256 AR5K_AR5211_DESC_TX_STATUS0_EXCESSIVE_RETRIES) 1257 desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY; 1258 1259 if (tx_status->tx_status_0 & 1260 AR5K_AR5211_DESC_TX_STATUS0_FIFO_UNDERRUN) 1261 desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO; 1262 1263 if (tx_status->tx_status_0 & 1264 AR5K_AR5211_DESC_TX_STATUS0_FILTERED) 1265 desc->ds_us.tx.ts_status |= HAL_TXERR_FILT; 1266 } 1267 1268 return (HAL_OK); 1269} 1270 1271HAL_BOOL 1272ar5k_ar5211_has_veol(struct ath_hal *hal) 1273{ 1274 return (AH_TRUE); 1275} 1276 1277/* 1278 * Receive functions 1279 */ 1280 1281u_int32_t 1282ar5k_ar5211_get_rx_buf(struct ath_hal *hal) 1283{ 1284 return (AR5K_REG_READ(AR5K_AR5211_RXDP)); 1285} 1286 1287void 1288ar5k_ar5211_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr) 1289{ 1290 AR5K_REG_WRITE(AR5K_AR5211_RXDP, phys_addr); 1291} 1292 1293void 1294ar5k_ar5211_start_rx(struct ath_hal *hal) 1295{ 1296 AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXE); 1297} 1298 1299HAL_BOOL 1300ar5k_ar5211_stop_rx_dma(struct ath_hal *hal) 1301{ 1302 int i; 1303 1304 AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXD); 1305 1306 /* 1307 * It may take some time to disable the DMA receive unit 1308 */ 1309 for (i = 2000; 1310 i > 0 && (AR5K_REG_READ(AR5K_AR5211_CR) & AR5K_AR5211_CR_RXE) != 0; 1311 i--) 1312 AR5K_DELAY(10); 1313 1314 return (i > 0 ? AH_TRUE : AH_FALSE); 1315} 1316 1317void 1318ar5k_ar5211_start_rx_pcu(struct ath_hal *hal) 1319{ 1320 AR5K_REG_DISABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX); 1321} 1322 1323void 1324ar5k_ar5211_stop_pcu_recv(struct ath_hal *hal) 1325{ 1326 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX); 1327} 1328 1329void 1330ar5k_ar5211_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0, 1331 u_int32_t filter1) 1332{ 1333 /* Set the multicast filter */ 1334 AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL0, filter0); 1335 AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL1, filter1); 1336} 1337 1338HAL_BOOL 1339ar5k_ar5211_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index) 1340{ 1341 if (index >= 64) { 1342 return (AH_FALSE); 1343 } else if (index >= 32) { 1344 AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL1, 1345 (1 << (index - 32))); 1346 } else { 1347 AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL0, 1348 (1 << index)); 1349 } 1350 1351 return (AH_TRUE); 1352} 1353 1354HAL_BOOL 1355ar5k_ar5211_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index) 1356{ 1357 1358 if (index >= 64) { 1359 return (AH_FALSE); 1360 } else if (index >= 32) { 1361 AR5K_REG_DISABLE_BITS(AR5K_AR5211_MCAST_FIL1, 1362 (1 << (index - 32))); 1363 } else { 1364 AR5K_REG_DISABLE_BITS(AR5K_AR5211_MCAST_FIL0, 1365 (1 << index)); 1366 } 1367 1368 return (AH_TRUE); 1369} 1370 1371u_int32_t 1372ar5k_ar5211_get_rx_filter(struct ath_hal *hal) 1373{ 1374 return (AR5K_REG_READ(AR5K_AR5211_RX_FILTER)); 1375} 1376 1377void 1378ar5k_ar5211_set_rx_filter(struct ath_hal *hal, u_int32_t filter) 1379{ 1380 AR5K_REG_WRITE(AR5K_AR5211_RX_FILTER, filter); 1381} 1382 1383HAL_BOOL 1384ar5k_ar5211_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1385 u_int32_t size, u_int flags) 1386{ 1387 struct ar5k_ar5211_rx_desc *rx_desc; 1388 1389 rx_desc = (struct ar5k_ar5211_rx_desc*)&desc->ds_ctl0; 1390 1391 if ((rx_desc->rx_control_1 = (size & 1392 AR5K_AR5211_DESC_RX_CTL1_BUF_LEN)) != size) 1393 return (AH_FALSE); 1394 1395 if (flags & HAL_RXDESC_INTREQ) 1396 rx_desc->rx_control_1 |= AR5K_AR5211_DESC_RX_CTL1_INTREQ; 1397 1398 return (AH_TRUE); 1399} 1400 1401HAL_STATUS 1402ar5k_ar5211_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc, 1403 u_int32_t phys_addr, struct ath_desc *next) 1404{ 1405 struct ar5k_ar5211_rx_status *rx_status; 1406 1407 rx_status = (struct ar5k_ar5211_rx_status*)&desc->ds_hw[0]; 1408 1409 /* No frame received / not ready */ 1410 if ((rx_status->rx_status_1 & AR5K_AR5211_DESC_RX_STATUS1_DONE) == 0) 1411 return (HAL_EINPROGRESS); 1412 1413 /* 1414 * Frame receive status 1415 */ 1416 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 & 1417 AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN; 1418 desc->ds_us.rx.rs_rssi = 1419 AR5K_REG_MS(rx_status->rx_status_0, 1420 AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL); 1421 desc->ds_us.rx.rs_rate = 1422 AR5K_REG_MS(rx_status->rx_status_0, 1423 AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE); 1424 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 & 1425 AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA; 1426 desc->ds_us.rx.rs_more = rx_status->rx_status_0 & 1427 AR5K_AR5211_DESC_RX_STATUS0_MORE; 1428 desc->ds_us.rx.rs_tstamp = 1429 AR5K_REG_MS(rx_status->rx_status_1, 1430 AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP); 1431 desc->ds_us.rx.rs_status = 0; 1432 1433 /* 1434 * Key table status 1435 */ 1436 if (rx_status->rx_status_1 & 1437 AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID) { 1438 desc->ds_us.rx.rs_keyix = 1439 AR5K_REG_MS(rx_status->rx_status_1, 1440 AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX); 1441 } else { 1442 desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID; 1443 } 1444 1445 /* 1446 * Receive/descriptor errors 1447 */ 1448 if ((rx_status->rx_status_1 & 1449 AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) { 1450 if (rx_status->rx_status_1 & 1451 AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR) 1452 desc->ds_us.rx.rs_status |= HAL_RXERR_CRC; 1453 1454 if (rx_status->rx_status_1 & 1455 AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR) { 1456 desc->ds_us.rx.rs_status |= HAL_RXERR_PHY; 1457 desc->ds_us.rx.rs_phyerr = 1458 AR5K_REG_MS(rx_status->rx_status_1, 1459 AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR); 1460 } 1461 1462 if (rx_status->rx_status_1 & 1463 AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR) 1464 desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT; 1465 } 1466 1467 return (HAL_OK); 1468} 1469 1470void 1471ar5k_ar5211_set_rx_signal(struct ath_hal *hal) 1472{ 1473 /* Signal state monitoring is not yet supported */ 1474} 1475 1476/* 1477 * Misc functions 1478 */ 1479 1480void 1481ar5k_ar5211_dump_state(struct ath_hal *hal) 1482{ 1483#ifdef AR5K_DEBUG 1484#define AR5K_PRINT_REGISTER(_x) \ 1485 printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5211_##_x)); 1486 1487 printf("MAC registers:\n"); 1488 AR5K_PRINT_REGISTER(CR); 1489 AR5K_PRINT_REGISTER(CFG); 1490 AR5K_PRINT_REGISTER(IER); 1491 AR5K_PRINT_REGISTER(RTSD0); 1492 AR5K_PRINT_REGISTER(TXCFG); 1493 AR5K_PRINT_REGISTER(RXCFG); 1494 AR5K_PRINT_REGISTER(RXJLA); 1495 AR5K_PRINT_REGISTER(MIBC); 1496 AR5K_PRINT_REGISTER(TOPS); 1497 AR5K_PRINT_REGISTER(RXNOFRM); 1498 AR5K_PRINT_REGISTER(RPGTO); 1499 AR5K_PRINT_REGISTER(RFCNT); 1500 AR5K_PRINT_REGISTER(MISC); 1501 AR5K_PRINT_REGISTER(PISR); 1502 AR5K_PRINT_REGISTER(SISR0); 1503 AR5K_PRINT_REGISTER(SISR1); 1504 AR5K_PRINT_REGISTER(SISR3); 1505 AR5K_PRINT_REGISTER(SISR4); 1506 AR5K_PRINT_REGISTER(QCU_TXE); 1507 AR5K_PRINT_REGISTER(QCU_TXD); 1508 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS); 1509 AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT); 1510 AR5K_PRINT_REGISTER(DCU_FP); 1511 AR5K_PRINT_REGISTER(DCU_TXP); 1512 AR5K_PRINT_REGISTER(DCU_TX_FILTER); 1513 AR5K_PRINT_REGISTER(RC); 1514 AR5K_PRINT_REGISTER(SCR); 1515 AR5K_PRINT_REGISTER(INTPEND); 1516 AR5K_PRINT_REGISTER(PCICFG); 1517 AR5K_PRINT_REGISTER(GPIOCR); 1518 AR5K_PRINT_REGISTER(GPIODO); 1519 AR5K_PRINT_REGISTER(SREV); 1520 AR5K_PRINT_REGISTER(EEPROM_BASE); 1521 AR5K_PRINT_REGISTER(EEPROM_DATA); 1522 AR5K_PRINT_REGISTER(EEPROM_CMD); 1523 AR5K_PRINT_REGISTER(EEPROM_CFG); 1524 AR5K_PRINT_REGISTER(PCU_MIN); 1525 AR5K_PRINT_REGISTER(STA_ID0); 1526 AR5K_PRINT_REGISTER(STA_ID1); 1527 AR5K_PRINT_REGISTER(BSS_ID0); 1528 AR5K_PRINT_REGISTER(SLOT_TIME); 1529 AR5K_PRINT_REGISTER(TIME_OUT); 1530 AR5K_PRINT_REGISTER(RSSI_THR); 1531 AR5K_PRINT_REGISTER(BEACON); 1532 AR5K_PRINT_REGISTER(CFP_PERIOD); 1533 AR5K_PRINT_REGISTER(TIMER0); 1534 AR5K_PRINT_REGISTER(TIMER2); 1535 AR5K_PRINT_REGISTER(TIMER3); 1536 AR5K_PRINT_REGISTER(CFP_DUR); 1537 AR5K_PRINT_REGISTER(MCAST_FIL0); 1538 AR5K_PRINT_REGISTER(MCAST_FIL1); 1539 AR5K_PRINT_REGISTER(DIAG_SW); 1540 AR5K_PRINT_REGISTER(TSF_U32); 1541 AR5K_PRINT_REGISTER(ADDAC_TEST); 1542 AR5K_PRINT_REGISTER(DEFAULT_ANTENNA); 1543 AR5K_PRINT_REGISTER(LAST_TSTP); 1544 AR5K_PRINT_REGISTER(NAV); 1545 AR5K_PRINT_REGISTER(RTS_OK); 1546 AR5K_PRINT_REGISTER(ACK_FAIL); 1547 AR5K_PRINT_REGISTER(FCS_FAIL); 1548 AR5K_PRINT_REGISTER(BEACON_CNT); 1549 AR5K_PRINT_REGISTER(KEYTABLE_0); 1550 printf("\n"); 1551 1552 printf("PHY registers:\n"); 1553 AR5K_PRINT_REGISTER(PHY_TURBO); 1554 AR5K_PRINT_REGISTER(PHY_AGC); 1555 AR5K_PRINT_REGISTER(PHY_CHIP_ID); 1556 AR5K_PRINT_REGISTER(PHY_AGCCTL); 1557 AR5K_PRINT_REGISTER(PHY_NF); 1558 AR5K_PRINT_REGISTER(PHY_RX_DELAY); 1559 AR5K_PRINT_REGISTER(PHY_IQ); 1560 AR5K_PRINT_REGISTER(PHY_PAPD_PROBE); 1561 AR5K_PRINT_REGISTER(PHY_FC); 1562 AR5K_PRINT_REGISTER(PHY_RADAR); 1563 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0); 1564 AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1); 1565 printf("\n"); 1566#endif 1567} 1568 1569HAL_BOOL 1570ar5k_ar5211_get_diag_state(struct ath_hal *hal, int id, void **device, 1571 u_int *size) 1572{ 1573 /* 1574 * We'll ignore this right now. This seems to be some kind of an obscure 1575 * debugging interface for the binary-only HAL. 1576 */ 1577 return (AH_FALSE); 1578} 1579 1580void 1581ar5k_ar5211_get_lladdr(struct ath_hal *hal, u_int8_t *mac) 1582{ 1583 bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN); 1584} 1585 1586HAL_BOOL 1587ar5k_ar5211_set_lladdr(struct ath_hal *hal, const u_int8_t *mac) 1588{ 1589 u_int32_t low_id, high_id; 1590 1591 /* Set new station ID */ 1592 bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN); 1593 1594 low_id = AR5K_LOW_ID(mac); 1595 high_id = 0x0000ffff & AR5K_HIGH_ID(mac); 1596 1597 AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id); 1598 AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, high_id); 1599 1600 return (AH_TRUE); 1601} 1602 1603HAL_BOOL 1604ar5k_ar5211_set_regdomain(struct ath_hal *hal, u_int16_t regdomain, 1605 HAL_STATUS *status) 1606{ 1607 ieee80211_regdomain_t ieee_regdomain; 1608 1609 ieee_regdomain = ar5k_regdomain_to_ieee(regdomain); 1610 1611 if (ar5k_eeprom_regulation_domain(hal, AH_TRUE, 1612 &ieee_regdomain) == AH_TRUE) { 1613 *status = HAL_OK; 1614 return (AH_TRUE); 1615 } 1616 1617 *status = EIO; 1618 1619 return (AH_FALSE); 1620} 1621 1622void 1623ar5k_ar5211_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state) 1624{ 1625 u_int32_t led; 1626 1627 AR5K_REG_DISABLE_BITS(AR5K_AR5211_PCICFG, 1628 AR5K_AR5211_PCICFG_LEDMODE | AR5K_AR5211_PCICFG_LED); 1629 1630 /* 1631 * Some blinking values, define at your wish 1632 */ 1633 switch (state) { 1634 case IEEE80211_S_SCAN: 1635 case IEEE80211_S_AUTH: 1636 led = AR5K_AR5211_PCICFG_LEDMODE_PROP | 1637 AR5K_AR5211_PCICFG_LED_PEND; 1638 break; 1639 1640 case IEEE80211_S_INIT: 1641 led = AR5K_AR5211_PCICFG_LEDMODE_PROP | 1642 AR5K_AR5211_PCICFG_LED_NONE; 1643 break; 1644 1645 case IEEE80211_S_ASSOC: 1646 case IEEE80211_S_RUN: 1647 led = AR5K_AR5211_PCICFG_LEDMODE_PROP | 1648 AR5K_AR5211_PCICFG_LED_ASSOC; 1649 break; 1650 1651 default: 1652 led = AR5K_AR5211_PCICFG_LEDMODE_PROM | 1653 AR5K_AR5211_PCICFG_LED_NONE; 1654 break; 1655 } 1656 1657 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, led); 1658} 1659 1660void 1661ar5k_ar5211_set_associd(struct ath_hal *hal, const u_int8_t *bssid, 1662 u_int16_t assoc_id, u_int16_t tim_offset) 1663{ 1664 u_int32_t low_id, high_id; 1665 1666 /* 1667 * Set BSSID which triggers the "SME Join" operation 1668 */ 1669 low_id = AR5K_LOW_ID(bssid); 1670 high_id = AR5K_HIGH_ID(bssid); 1671 AR5K_REG_WRITE(AR5K_AR5211_BSS_ID0, low_id); 1672 AR5K_REG_WRITE(AR5K_AR5211_BSS_ID1, high_id | 1673 ((assoc_id & 0x3fff) << AR5K_AR5211_BSS_ID1_AID_S)); 1674 bcopy(bssid, hal->ah_bssid, IEEE80211_ADDR_LEN); 1675 1676 if (assoc_id == 0) { 1677 ar5k_ar5211_disable_pspoll(hal); 1678 return; 1679 } 1680 1681 AR5K_REG_WRITE(AR5K_AR5211_BEACON, 1682 (AR5K_REG_READ(AR5K_AR5211_BEACON) & 1683 ~AR5K_AR5211_BEACON_TIM) | 1684 (((tim_offset ? tim_offset + 4 : 0) << 1685 AR5K_AR5211_BEACON_TIM_S) & 1686 AR5K_AR5211_BEACON_TIM)); 1687 1688 ar5k_ar5211_enable_pspoll(hal, NULL, 0); 1689} 1690 1691HAL_BOOL 1692ar5k_ar5211_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask) 1693{ 1694 /* Not supported in 5211 */ 1695 return (AH_FALSE); 1696} 1697 1698HAL_BOOL 1699ar5k_ar5211_set_gpio_output(struct ath_hal *hal, u_int32_t gpio) 1700{ 1701 if (gpio > AR5K_AR5211_NUM_GPIO) 1702 return (AH_FALSE); 1703 1704 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, 1705 (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio)) 1706 | AR5K_AR5211_GPIOCR_ALL(gpio)); 1707 1708 return (AH_TRUE); 1709} 1710 1711HAL_BOOL 1712ar5k_ar5211_set_gpio_input(struct ath_hal *hal, u_int32_t gpio) 1713{ 1714 if (gpio > AR5K_AR5211_NUM_GPIO) 1715 return (AH_FALSE); 1716 1717 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, 1718 (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio)) 1719 | AR5K_AR5211_GPIOCR_NONE(gpio)); 1720 1721 return (AH_TRUE); 1722} 1723 1724u_int32_t 1725ar5k_ar5211_get_gpio(struct ath_hal *hal, u_int32_t gpio) 1726{ 1727 if (gpio > AR5K_AR5211_NUM_GPIO) 1728 return (0xffffffff); 1729 1730 /* GPIO input magic */ 1731 return (((AR5K_REG_READ(AR5K_AR5211_GPIODI) & 1732 AR5K_AR5211_GPIODI_M) >> gpio) & 0x1); 1733} 1734 1735HAL_BOOL 1736ar5k_ar5211_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val) 1737{ 1738 u_int32_t data; 1739 1740 if (gpio > AR5K_AR5211_NUM_GPIO) 1741 return (0xffffffff); 1742 1743 /* GPIO output magic */ 1744 data = AR5K_REG_READ(AR5K_AR5211_GPIODO); 1745 1746 data &= ~(1 << gpio); 1747 data |= (val&1) << gpio; 1748 1749 AR5K_REG_WRITE(AR5K_AR5211_GPIODO, data); 1750 1751 return (AH_TRUE); 1752} 1753 1754void 1755ar5k_ar5211_set_gpio_intr(struct ath_hal *hal, u_int gpio, 1756 u_int32_t interrupt_level) 1757{ 1758 u_int32_t data; 1759 1760 if (gpio > AR5K_AR5211_NUM_GPIO) 1761 return; 1762 1763 /* 1764 * Set the GPIO interrupt 1765 */ 1766 data = (AR5K_REG_READ(AR5K_AR5211_GPIOCR) & 1767 ~(AR5K_AR5211_GPIOCR_INT_SEL(gpio) | AR5K_AR5211_GPIOCR_INT_SELH | 1768 AR5K_AR5211_GPIOCR_INT_ENA | AR5K_AR5211_GPIOCR_ALL(gpio))) | 1769 (AR5K_AR5211_GPIOCR_INT_SEL(gpio) | AR5K_AR5211_GPIOCR_INT_ENA); 1770 1771 AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, 1772 interrupt_level ? data : (data | AR5K_AR5211_GPIOCR_INT_SELH)); 1773 1774 hal->ah_imr |= AR5K_AR5211_PIMR_GPIO; 1775 1776 /* Enable GPIO interrupts */ 1777 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, AR5K_AR5211_PIMR_GPIO); 1778} 1779 1780u_int32_t 1781ar5k_ar5211_get_tsf32(struct ath_hal *hal) 1782{ 1783 return (AR5K_REG_READ(AR5K_AR5211_TSF_L32)); 1784} 1785 1786u_int64_t 1787ar5k_ar5211_get_tsf64(struct ath_hal *hal) 1788{ 1789 u_int64_t tsf = AR5K_REG_READ(AR5K_AR5211_TSF_U32); 1790 1791 return (AR5K_REG_READ(AR5K_AR5211_TSF_L32) | (tsf << 32)); 1792} 1793 1794void 1795ar5k_ar5211_reset_tsf(struct ath_hal *hal) 1796{ 1797 AR5K_REG_ENABLE_BITS(AR5K_AR5211_BEACON, 1798 AR5K_AR5211_BEACON_RESET_TSF); 1799} 1800 1801u_int16_t 1802ar5k_ar5211_get_regdomain(struct ath_hal *hal) 1803{ 1804 return (ar5k_get_regdomain(hal)); 1805} 1806 1807HAL_BOOL 1808ar5k_ar5211_detect_card_present(struct ath_hal *hal) 1809{ 1810 u_int16_t magic; 1811 1812 /* 1813 * Checking the EEPROM's magic value could be an indication 1814 * if the card is still present. I didn't find another suitable 1815 * way to do this. 1816 */ 1817 if (ar5k_ar5211_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0) 1818 return (AH_FALSE); 1819 1820 return (magic == AR5K_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE); 1821} 1822 1823void 1824ar5k_ar5211_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics) 1825{ 1826 statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5211_ACK_FAIL); 1827 statistics->rts_bad += AR5K_REG_READ(AR5K_AR5211_RTS_FAIL); 1828 statistics->rts_good += AR5K_REG_READ(AR5K_AR5211_RTS_OK); 1829 statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5211_FCS_FAIL); 1830 statistics->beacons += AR5K_REG_READ(AR5K_AR5211_BEACON_CNT); 1831} 1832 1833HAL_RFGAIN 1834ar5k_ar5211_get_rf_gain(struct ath_hal *hal) 1835{ 1836 return (HAL_RFGAIN_INACTIVE); 1837} 1838 1839HAL_BOOL 1840ar5k_ar5211_set_slot_time(struct ath_hal *hal, u_int slot_time) 1841{ 1842 if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX) 1843 return (AH_FALSE); 1844 1845 AR5K_REG_WRITE(AR5K_AR5211_DCU_GBL_IFS_SLOT, slot_time); 1846 1847 return (AH_TRUE); 1848} 1849 1850u_int 1851ar5k_ar5211_get_slot_time(struct ath_hal *hal) 1852{ 1853 return (AR5K_REG_READ(AR5K_AR5211_DCU_GBL_IFS_SLOT) & 0xffff); 1854} 1855 1856HAL_BOOL 1857ar5k_ar5211_set_ack_timeout(struct ath_hal *hal, u_int timeout) 1858{ 1859 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_ACK)) 1860 <= timeout) 1861 return (AH_FALSE); 1862 1863 AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_ACK, 1864 ar5k_htoclock(timeout)); 1865 1866 return (AH_TRUE); 1867} 1868 1869u_int 1870ar5k_ar5211_get_ack_timeout(struct ath_hal *hal) 1871{ 1872 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT), 1873 AR5K_AR5211_TIME_OUT_ACK))); 1874} 1875 1876HAL_BOOL 1877ar5k_ar5211_set_cts_timeout(struct ath_hal *hal, u_int timeout) 1878{ 1879 if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_CTS)) 1880 <= timeout) 1881 return (AH_FALSE); 1882 1883 AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_CTS, 1884 ar5k_htoclock(timeout)); 1885 1886 return (AH_TRUE); 1887} 1888 1889u_int 1890ar5k_ar5211_get_cts_timeout(struct ath_hal *hal) 1891{ 1892 return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT), 1893 AR5K_AR5211_TIME_OUT_CTS))); 1894} 1895 1896/* 1897 * Key table (WEP) functions 1898 */ 1899 1900HAL_BOOL 1901ar5k_ar5211_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher) 1902{ 1903 /* 1904 * The AR5211 only supports WEP 1905 */ 1906 if (cipher == HAL_CIPHER_WEP) 1907 return (AH_TRUE); 1908 1909 return (AH_FALSE); 1910} 1911 1912u_int32_t 1913ar5k_ar5211_get_keycache_size(struct ath_hal *hal) 1914{ 1915 return (AR5K_AR5211_KEYCACHE_SIZE); 1916} 1917 1918HAL_BOOL 1919ar5k_ar5211_reset_key(struct ath_hal *hal, u_int16_t entry) 1920{ 1921 int i; 1922 1923 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 1924 1925 for (i = 0; i < AR5K_AR5211_KEYCACHE_SIZE; i++) 1926 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), 0); 1927 1928 /* Set NULL encryption */ 1929 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_TYPE(entry), 1930 AR5K_AR5211_KEYTABLE_TYPE_NULL); 1931 1932 return (AH_FALSE); 1933} 1934 1935HAL_BOOL 1936ar5k_ar5211_is_key_valid(struct ath_hal *hal, u_int16_t entry) 1937{ 1938 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 1939 1940 /* 1941 * Check the validation flag at the end of the entry 1942 */ 1943 if (AR5K_REG_READ(AR5K_AR5211_KEYTABLE_MAC1(entry)) & 1944 AR5K_AR5211_KEYTABLE_VALID) 1945 return (AH_TRUE); 1946 1947 return (AH_FALSE); 1948} 1949 1950HAL_BOOL 1951ar5k_ar5211_set_key(struct ath_hal *hal, u_int16_t entry, 1952 const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused) 1953{ 1954 int i; 1955 u_int32_t key_v[AR5K_AR5211_KEYCACHE_SIZE - 2]; 1956 1957 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 1958 1959 bzero(&key_v, sizeof(key_v)); 1960 1961 switch (keyval->wk_len) { 1962 case AR5K_KEYVAL_LENGTH_40: 1963 bcopy(keyval->wk_key, &key_v[0], 4); 1964 bcopy(keyval->wk_key + 4, &key_v[1], 1); 1965 key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_40; 1966 break; 1967 1968 case AR5K_KEYVAL_LENGTH_104: 1969 bcopy(keyval->wk_key, &key_v[0], 4); 1970 bcopy(keyval->wk_key + 4, &key_v[1], 2); 1971 bcopy(keyval->wk_key + 6, &key_v[2], 4); 1972 bcopy(keyval->wk_key + 10, &key_v[3], 2); 1973 bcopy(keyval->wk_key + 12, &key_v[4], 1); 1974 key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_104; 1975 break; 1976 1977 case AR5K_KEYVAL_LENGTH_128: 1978 bcopy(keyval->wk_key, &key_v[0], 4); 1979 bcopy(keyval->wk_key + 4, &key_v[1], 2); 1980 bcopy(keyval->wk_key + 6, &key_v[2], 4); 1981 bcopy(keyval->wk_key + 10, &key_v[3], 2); 1982 bcopy(keyval->wk_key + 12, &key_v[4], 4); 1983 key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_128; 1984 break; 1985 1986 default: 1987 /* Unsupported key length (not WEP40/104/128) */ 1988 return (AH_FALSE); 1989 } 1990 1991 for (i = 0; i < nitems(key_v); i++) 1992 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), key_v[i]); 1993 1994 return (ar5k_ar5211_set_key_lladdr(hal, entry, mac)); 1995} 1996 1997HAL_BOOL 1998ar5k_ar5211_set_key_lladdr(struct ath_hal *hal, u_int16_t entry, 1999 const u_int8_t *mac) 2000{ 2001 u_int32_t low_id, high_id; 2002 const u_int8_t *mac_v; 2003 2004 /* 2005 * Invalid entry (key table overflow) 2006 */ 2007 AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE); 2008 2009 /* MAC may be NULL if it's a broadcast key */ 2010 mac_v = mac == NULL ? etherbroadcastaddr : mac; 2011 2012 low_id = AR5K_LOW_ID(mac_v); 2013 high_id = AR5K_HIGH_ID(mac_v) | AR5K_AR5211_KEYTABLE_VALID; 2014 2015 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC0(entry), low_id); 2016 AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC1(entry), high_id); 2017 2018 return (AH_TRUE); 2019} 2020 2021HAL_BOOL 2022ar5k_ar5211_softcrypto(struct ath_hal *hal, HAL_BOOL enable) 2023{ 2024 u_int32_t bits; 2025 int i; 2026 2027 bits = AR5K_AR5211_DIAG_SW_DIS_ENC | AR5K_AR5211_DIAG_SW_DIS_DEC; 2028 if (enable == AH_TRUE) { 2029 /* Disable the hardware crypto engine */ 2030 AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, bits); 2031 } else { 2032 /* Enable the hardware crypto engine */ 2033 AR5K_REG_DISABLE_BITS(AR5K_AR5211_DIAG_SW, bits); 2034 } 2035 2036 /* Reset the key cache */ 2037 for (i = 0; i < AR5K_AR5211_KEYTABLE_SIZE; i++) 2038 ar5k_ar5211_reset_key(hal, i); 2039 2040 return (AH_TRUE); 2041} 2042 2043/* 2044 * Power management functions 2045 */ 2046 2047HAL_BOOL 2048ar5k_ar5211_set_power(struct ath_hal *hal, HAL_POWER_MODE mode, 2049 HAL_BOOL set_chip, u_int16_t sleep_duration) 2050{ 2051 u_int32_t staid; 2052 int i; 2053 2054 staid = AR5K_REG_READ(AR5K_AR5211_STA_ID1); 2055 2056 switch (mode) { 2057 case HAL_PM_AUTO: 2058 staid &= ~AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA; 2059 /* FALLTHROUGH */ 2060 case HAL_PM_NETWORK_SLEEP: 2061 if (set_chip == AH_TRUE) { 2062 AR5K_REG_WRITE(AR5K_AR5211_SCR, 2063 AR5K_AR5211_SCR_SLE | sleep_duration); 2064 } 2065 staid |= AR5K_AR5211_STA_ID1_PWR_SV; 2066 break; 2067 2068 case HAL_PM_FULL_SLEEP: 2069 if (set_chip == AH_TRUE) { 2070 AR5K_REG_WRITE(AR5K_AR5211_SCR, 2071 AR5K_AR5211_SCR_SLE_SLP); 2072 } 2073 staid |= AR5K_AR5211_STA_ID1_PWR_SV; 2074 break; 2075 2076 case HAL_PM_AWAKE: 2077 if (set_chip == AH_FALSE) 2078 goto commit; 2079 2080 AR5K_REG_WRITE(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLE_WAKE); 2081 2082 for (i = 5000; i > 0; i--) { 2083 /* Check if the AR5211 did wake up */ 2084 if ((AR5K_REG_READ(AR5K_AR5211_PCICFG) & 2085 AR5K_AR5211_PCICFG_SPWR_DN) == 0) 2086 break; 2087 2088 /* Wait a bit and retry */ 2089 AR5K_DELAY(200); 2090 AR5K_REG_WRITE(AR5K_AR5211_SCR, 2091 AR5K_AR5211_SCR_SLE_WAKE); 2092 } 2093 2094 /* Fail if the AR5211 didn't wake up */ 2095 if (i <= 0) 2096 return (AH_FALSE); 2097 2098 staid &= ~AR5K_AR5211_STA_ID1_PWR_SV; 2099 break; 2100 2101 default: 2102 return (AH_FALSE); 2103 } 2104 2105 commit: 2106 hal->ah_power_mode = mode; 2107 2108 AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, staid); 2109 2110 return (AH_TRUE); 2111} 2112 2113HAL_POWER_MODE 2114ar5k_ar5211_get_power_mode(struct ath_hal *hal) 2115{ 2116 return (hal->ah_power_mode); 2117} 2118 2119HAL_BOOL 2120ar5k_ar5211_query_pspoll_support(struct ath_hal *hal) 2121{ 2122 /* nope */ 2123 return (AH_FALSE); 2124} 2125 2126HAL_BOOL 2127ar5k_ar5211_init_pspoll(struct ath_hal *hal) 2128{ 2129 /* 2130 * Not used on the AR5211 2131 */ 2132 return (AH_FALSE); 2133} 2134 2135HAL_BOOL 2136ar5k_ar5211_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid, 2137 u_int16_t assoc_id) 2138{ 2139 return (AH_FALSE); 2140} 2141 2142HAL_BOOL 2143ar5k_ar5211_disable_pspoll(struct ath_hal *hal) 2144{ 2145 return (AH_FALSE); 2146} 2147 2148/* 2149 * Beacon functions 2150 */ 2151 2152void 2153ar5k_ar5211_init_beacon(struct ath_hal *hal, u_int32_t next_beacon, 2154 u_int32_t interval) 2155{ 2156 u_int32_t timer1, timer2, timer3; 2157 2158 /* 2159 * Set the additional timers by mode 2160 */ 2161 switch (hal->ah_op_mode) { 2162 case HAL_M_STA: 2163 timer1 = 0x0000ffff; 2164 timer2 = 0x0007ffff; 2165 break; 2166 2167 default: 2168 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 2169 0x00000003; 2170 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 2171 0x00000003; 2172 } 2173 2174 timer3 = next_beacon + 2175 (hal->ah_atim_window ? hal->ah_atim_window : 1); 2176 2177 /* 2178 * Enable all timers and set the beacon register 2179 * (next beacon, DMA beacon, software beacon, ATIM window time) 2180 */ 2181 AR5K_REG_WRITE(AR5K_AR5211_TIMER0, next_beacon); 2182 AR5K_REG_WRITE(AR5K_AR5211_TIMER1, timer1); 2183 AR5K_REG_WRITE(AR5K_AR5211_TIMER2, timer2); 2184 AR5K_REG_WRITE(AR5K_AR5211_TIMER3, timer3); 2185 2186 AR5K_REG_WRITE(AR5K_AR5211_BEACON, interval & 2187 (AR5K_AR5211_BEACON_PERIOD | AR5K_AR5211_BEACON_RESET_TSF | 2188 AR5K_AR5211_BEACON_ENABLE)); 2189} 2190 2191void 2192ar5k_ar5211_set_beacon_timers(struct ath_hal *hal, 2193 const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count, 2194 u_int32_t cfp_count) 2195{ 2196 u_int32_t cfp_period, next_cfp; 2197 2198 /* Return on an invalid beacon state */ 2199 if (state->bs_interval < 1) 2200 return; 2201 2202 /* 2203 * PCF support? 2204 */ 2205 if (state->bs_cfp_period > 0) { 2206 /* Enable CFP mode and set the CFP and timer registers */ 2207 cfp_period = state->bs_cfp_period * state->bs_dtim_period * 2208 state->bs_interval; 2209 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * 2210 state->bs_interval; 2211 2212 AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, 2213 AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | 2214 AR5K_AR5211_STA_ID1_PCF); 2215 AR5K_REG_WRITE(AR5K_AR5211_CFP_PERIOD, cfp_period); 2216 AR5K_REG_WRITE(AR5K_AR5211_CFP_DUR, state->bs_cfp_max_duration); 2217 AR5K_REG_WRITE(AR5K_AR5211_TIMER2, 2218 (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3); 2219 } else { 2220 /* Disable PCF mode */ 2221 AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, 2222 AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | 2223 AR5K_AR5211_STA_ID1_PCF); 2224 } 2225 2226 /* 2227 * Enable the beacon timer register 2228 */ 2229 AR5K_REG_WRITE(AR5K_AR5211_TIMER0, state->bs_next_beacon); 2230 2231 /* 2232 * Start the beacon timers 2233 */ 2234 AR5K_REG_WRITE(AR5K_AR5211_BEACON, 2235 (AR5K_REG_READ(AR5K_AR5211_BEACON) &~ 2236 (AR5K_AR5211_BEACON_PERIOD | AR5K_AR5211_BEACON_TIM)) | 2237 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, 2238 AR5K_AR5211_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, 2239 AR5K_AR5211_BEACON_PERIOD)); 2240 2241 /* 2242 * Write new beacon miss threshold, if it appears to be valid 2243 */ 2244 if ((AR5K_AR5211_RSSI_THR_BMISS >> AR5K_AR5211_RSSI_THR_BMISS_S) < 2245 state->bs_bmiss_threshold) 2246 return; 2247 2248 AR5K_REG_WRITE_BITS(AR5K_AR5211_RSSI_THR_M, 2249 AR5K_AR5211_RSSI_THR_BMISS, state->bs_bmiss_threshold); 2250 AR5K_REG_WRITE_BITS(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLDUR, 2251 (state->bs_sleepduration - 3) << 3); 2252} 2253 2254void 2255ar5k_ar5211_reset_beacon(struct ath_hal *hal) 2256{ 2257 /* 2258 * Disable beacon timer 2259 */ 2260 AR5K_REG_WRITE(AR5K_AR5211_TIMER0, 0); 2261 2262 /* 2263 * Disable some beacon register values 2264 */ 2265 AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1, 2266 AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | AR5K_AR5211_STA_ID1_PCF); 2267 AR5K_REG_WRITE(AR5K_AR5211_BEACON, AR5K_AR5211_BEACON_PERIOD); 2268} 2269 2270HAL_BOOL 2271ar5k_ar5211_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr) 2272{ 2273 HAL_BOOL ret; 2274 2275 /* 2276 * Wait for beacon queue to be done 2277 */ 2278 ret = ar5k_register_timeout(hal, 2279 AR5K_AR5211_QCU_STS(HAL_TX_QUEUE_ID_BEACON), 2280 AR5K_AR5211_QCU_STS_FRMPENDCNT, 0, AH_FALSE); 2281 2282 if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, HAL_TX_QUEUE_ID_BEACON)) 2283 return (AH_FALSE); 2284 2285 return (ret); 2286} 2287 2288/* 2289 * Interrupt handling 2290 */ 2291 2292HAL_BOOL 2293ar5k_ar5211_is_intr_pending(struct ath_hal *hal) 2294{ 2295 return (AR5K_REG_READ(AR5K_AR5211_INTPEND) == 0 ? AH_FALSE : AH_TRUE); 2296} 2297 2298HAL_BOOL 2299ar5k_ar5211_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask) 2300{ 2301 u_int32_t data; 2302 2303 /* 2304 * Read interrupt status from the Read-And-Clear shadow register 2305 */ 2306 data = AR5K_REG_READ(AR5K_AR5211_RAC_PISR); 2307 2308 /* 2309 * Get abstract interrupt mask (HAL-compatible) 2310 */ 2311 *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr; 2312 2313 if (data == HAL_INT_NOCARD) 2314 return (AH_FALSE); 2315 2316 if (data & (AR5K_AR5211_PISR_RXOK | AR5K_AR5211_PISR_RXERR)) 2317 *interrupt_mask |= HAL_INT_RX; 2318 2319 if (data & (AR5K_AR5211_PISR_TXOK | AR5K_AR5211_PISR_TXERR)) 2320 *interrupt_mask |= HAL_INT_TX; 2321 2322 if (data & (AR5K_AR5211_PISR_HIUERR)) 2323 *interrupt_mask |= HAL_INT_FATAL; 2324 2325 /* 2326 * Special interrupt handling (not caught by the driver) 2327 */ 2328 if (((*interrupt_mask) & AR5K_AR5211_PISR_RXPHY) && 2329 hal->ah_radar.r_enabled == AH_TRUE) 2330 ar5k_radar_alert(hal); 2331 2332 return (AH_TRUE); 2333} 2334 2335u_int32_t 2336ar5k_ar5211_get_intr(struct ath_hal *hal) 2337{ 2338 /* Return the interrupt mask stored previously */ 2339 return (hal->ah_imr); 2340} 2341 2342HAL_INT 2343ar5k_ar5211_set_intr(struct ath_hal *hal, HAL_INT new_mask) 2344{ 2345 HAL_INT old_mask, int_mask; 2346 2347 /* 2348 * Disable card interrupts to prevent any race conditions 2349 * (they will be re-enabled afterwards). 2350 */ 2351 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE); 2352 2353 old_mask = hal->ah_imr; 2354 2355 /* 2356 * Add additional, chipset-dependent interrupt mask flags 2357 * and write them to the IMR (interrupt mask register). 2358 */ 2359 int_mask = new_mask & HAL_INT_COMMON; 2360 2361 if (new_mask & HAL_INT_RX) 2362 int_mask |= 2363 AR5K_AR5211_PIMR_RXOK | 2364 AR5K_AR5211_PIMR_RXERR | 2365 AR5K_AR5211_PIMR_RXORN | 2366 AR5K_AR5211_PIMR_RXDESC; 2367 2368 if (new_mask & HAL_INT_TX) 2369 int_mask |= 2370 AR5K_AR5211_PIMR_TXOK | 2371 AR5K_AR5211_PIMR_TXERR | 2372 AR5K_AR5211_PIMR_TXDESC | 2373 AR5K_AR5211_PIMR_TXURN; 2374 2375 if (new_mask & HAL_INT_FATAL) { 2376 int_mask |= AR5K_AR5211_PIMR_HIUERR; 2377 AR5K_REG_ENABLE_BITS(AR5K_AR5211_SIMR2, 2378 AR5K_AR5211_SIMR2_MCABT | 2379 AR5K_AR5211_SIMR2_SSERR | 2380 AR5K_AR5211_SIMR2_DPERR); 2381 } 2382 2383 AR5K_REG_WRITE(AR5K_AR5211_PIMR, int_mask); 2384 2385 /* Store new interrupt mask */ 2386 hal->ah_imr = new_mask; 2387 2388 /* ..re-enable interrupts */ 2389 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE); 2390 2391 return (old_mask); 2392} 2393 2394/* 2395 * Misc internal functions 2396 */ 2397 2398HAL_BOOL 2399ar5k_ar5211_get_capabilities(struct ath_hal *hal) 2400{ 2401 u_int16_t ee_header; 2402 u_int a, b, g; 2403 2404 /* Capabilities stored in the EEPROM */ 2405 ee_header = hal->ah_capabilities.cap_eeprom.ee_header; 2406 2407 a = AR5K_EEPROM_HDR_11A(ee_header); 2408 b = AR5K_EEPROM_HDR_11B(ee_header); 2409 g = AR5K_EEPROM_HDR_11G(ee_header); 2410 2411 /* 2412 * If the EEPROM is not reporting any mode, we try 11b. 2413 * This might fix a few broken devices with invalid EEPROM. 2414 */ 2415 if (!a && !b && !g) 2416 b = 1; 2417 2418 /* 2419 * XXX The AR5211 transceiver supports frequencies from 4920 to 6100GHz 2420 * XXX and from 2312 to 2732GHz. There are problems with the current 2421 * XXX ieee80211 implementation because the IEEE channel mapping 2422 * XXX does not support negative channel numbers (2312MHz is channel 2423 * XXX -19). Of course, this doesn't matter because these channels 2424 * XXX are out of range but some regulation domains like MKK (Japan) 2425 * XXX will support frequencies somewhere around 4.8GHz. 2426 */ 2427 2428 /* 2429 * Set radio capabilities 2430 */ 2431 2432 if (a) { 2433 hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */ 2434 hal->ah_capabilities.cap_range.range_5ghz_max = 6100; 2435 2436 /* Set supported modes */ 2437 hal->ah_capabilities.cap_mode = HAL_MODE_11A | HAL_MODE_TURBO; 2438 } 2439 2440 /* This chip will support 802.11b if the 2GHz radio is connected */ 2441 if (b || g) { 2442 hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */ 2443 hal->ah_capabilities.cap_range.range_2ghz_max = 2732; 2444 2445 if (b) 2446 hal->ah_capabilities.cap_mode |= HAL_MODE_11B; 2447#if 0 2448 if (g) 2449 hal->ah_capabilities.cap_mode |= HAL_MODE_11G; 2450#endif 2451 } 2452 2453 /* GPIO */ 2454 hal->ah_gpio_npins = AR5K_AR5211_NUM_GPIO; 2455 2456 /* Set number of supported TX queues */ 2457 hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5211_TX_NUM_QUEUES; 2458 2459 return (AH_TRUE); 2460} 2461 2462void 2463ar5k_ar5211_radar_alert(struct ath_hal *hal, HAL_BOOL enable) 2464{ 2465 /* 2466 * Enable radar detection 2467 */ 2468 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE); 2469 2470 if (enable == AH_TRUE) { 2471 AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR, 2472 AR5K_AR5211_PHY_RADAR_ENABLE); 2473 AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, 2474 AR5K_AR5211_PIMR_RXPHY); 2475 } else { 2476 AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR, 2477 AR5K_AR5211_PHY_RADAR_DISABLE); 2478 AR5K_REG_DISABLE_BITS(AR5K_AR5211_PIMR, 2479 AR5K_AR5211_PIMR_RXPHY); 2480 } 2481 2482 AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE); 2483} 2484 2485/* 2486 * EEPROM access functions 2487 */ 2488 2489HAL_BOOL 2490ar5k_ar5211_eeprom_is_busy(struct ath_hal *hal) 2491{ 2492 return (AR5K_REG_READ(AR5K_AR5211_CFG) & AR5K_AR5211_CFG_EEBS ? 2493 AH_TRUE : AH_FALSE); 2494} 2495 2496int 2497ar5k_ar5211_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data) 2498{ 2499 u_int32_t status, i; 2500 2501 /* 2502 * Initialize EEPROM access 2503 */ 2504 AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset); 2505 AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, 2506 AR5K_AR5211_EEPROM_CMD_READ); 2507 2508 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 2509 status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS); 2510 if (status & AR5K_AR5211_EEPROM_STAT_RDDONE) { 2511 if (status & AR5K_AR5211_EEPROM_STAT_RDERR) 2512 return (EIO); 2513 *data = (u_int16_t) 2514 (AR5K_REG_READ(AR5K_AR5211_EEPROM_DATA) & 0xffff); 2515 return (0); 2516 } 2517 AR5K_DELAY(15); 2518 } 2519 2520 return (ETIMEDOUT); 2521} 2522 2523int 2524ar5k_ar5211_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data) 2525{ 2526 u_int32_t status, timeout; 2527 2528 /* Enable eeprom access */ 2529 AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, 2530 AR5K_AR5211_EEPROM_CMD_RESET); 2531 AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD, 2532 AR5K_AR5211_EEPROM_CMD_WRITE); 2533 2534 /* 2535 * Prime write pump 2536 */ 2537 AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset - 1); 2538 2539 for (timeout = 10000; timeout > 0; timeout--) { 2540 AR5K_DELAY(1); 2541 status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS); 2542 if (status & AR5K_AR5211_EEPROM_STAT_WRDONE) { 2543 if (status & AR5K_AR5211_EEPROM_STAT_WRERR) 2544 return (EIO); 2545 return (0); 2546 } 2547 } 2548 2549 return (ETIMEDOUT); 2550} 2551 2552/* 2553 * RF register settings 2554 */ 2555 2556HAL_BOOL 2557ar5k_ar5211_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int freq, 2558 u_int ee_mode) 2559{ 2560 struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom; 2561 struct ar5k_ar5211_ini_rf rf[nitems(ar5211_rf)]; 2562 u_int32_t ob, db, xpds, xpdp, x_gain; 2563 u_int i; 2564 int obdb; 2565 2566 bcopy(ar5211_rf, rf, sizeof(rf)); 2567 obdb = 0; 2568 2569 if (freq == AR5K_INI_RFGAIN_2GHZ && 2570 hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) { 2571 ob = ar5k_bitswap(ee->ee_ob[ee_mode][0], 3); 2572 db = ar5k_bitswap(ee->ee_db[ee_mode][0], 3); 2573 rf[25].rf_value[freq] = 2574 ((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0); 2575 rf[26].rf_value[freq] = 2576 (((ob >> 2) & 0x1) | ((db << 1) & 0xe)) | 2577 (rf[26].rf_value[freq] & ~0xf); 2578 } 2579 2580 if (freq == AR5K_INI_RFGAIN_5GHZ) { 2581 /* For 11a and Turbo */ 2582 obdb = channel->c_channel >= 5725 ? 3 : 2583 (channel->c_channel >= 5500 ? 2 : 2584 (channel->c_channel >= 5260 ? 1 : 2585 (channel->c_channel > 4000 ? 0 : -1))); 2586 } 2587 2588 /* bogus channel: bad beacon? */ 2589 if (obdb < 0) 2590 return (AH_FALSE); 2591 2592 ob = ee->ee_ob[ee_mode][obdb]; 2593 db = ee->ee_db[ee_mode][obdb]; 2594 x_gain = ee->ee_x_gain[ee_mode]; 2595 xpds = ee->ee_xpd[ee_mode]; 2596 xpdp = !xpds; 2597 2598 rf[11].rf_value[freq] = (rf[11].rf_value[freq] & ~0xc0) | 2599 (((ar5k_bitswap(x_gain, 4) << 7) | (xpdp << 6)) & 0xc0); 2600 rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x7) | 2601 ((ar5k_bitswap(x_gain, 4) >> 1) & 0x7); 2602 rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x80) | 2603 ((ar5k_bitswap(ob, 3) << 7) & 0x80); 2604 rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x3) | 2605 ((ar5k_bitswap(ob, 3) >> 1) & 0x3); 2606 rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x1c) | 2607 ((ar5k_bitswap(db, 3) << 2) & 0x1c); 2608 rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) | 2609 ((xpds << 3) & 0x8); 2610 2611 for (i = 0; i < nitems(rf); i++) { 2612 AR5K_REG_WAIT(i); 2613 AR5K_REG_WRITE((u_int32_t)rf[i].rf_register, 2614 rf[i].rf_value[freq]); 2615 } 2616 2617 hal->ah_rf_gain = HAL_RFGAIN_INACTIVE; 2618 2619 return (AH_TRUE); 2620} 2621 2622HAL_BOOL 2623ar5k_ar5211_set_txpower_limit(struct ath_hal *hal, u_int power) 2624{ 2625 /* Not implemented */ 2626 return (AH_FALSE); 2627} 2628