pciecam.c revision 1.3
1/* $OpenBSD: pciecam.c,v 1.3 2021/06/25 17:41:22 patrick Exp $ */ 2/* 3 * Copyright (c) 2013,2017 Patrick Wildt <patrick@blueri.se> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18#include <sys/param.h> 19#include <sys/systm.h> 20#include <sys/queue.h> 21#include <sys/malloc.h> 22#include <sys/extent.h> 23#include <sys/device.h> 24#include <sys/evcount.h> 25#include <sys/socket.h> 26#include <sys/timeout.h> 27 28#include <machine/intr.h> 29#include <machine/bus.h> 30#include <machine/fdt.h> 31 32#include <dev/pci/pcivar.h> 33 34#include <dev/ofw/fdt.h> 35#include <dev/ofw/openfirm.h> 36#include <dev/ofw/ofw_clock.h> 37#include <dev/ofw/ofw_pinctrl.h> 38#include <dev/ofw/ofw_misc.h> 39 40/* Assembling ECAM Configuration Address */ 41#define PCIE_BUS_SHIFT 20 42#define PCIE_SLOT_SHIFT 15 43#define PCIE_FUNC_SHIFT 12 44#define PCIE_BUS_MASK 0xff 45#define PCIE_SLOT_MASK 0x1f 46#define PCIE_FUNC_MASK 0x7 47#define PCIE_REG_MASK 0xfff 48 49#define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ 50 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ 51 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ 52 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ 53 ((reg) & PCIE_REG_MASK)) 54 55#define HREAD4(sc, reg) \ 56 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 57#define HWRITE4(sc, reg, val) \ 58 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 59#define HSET4(sc, reg, bits) \ 60 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 61#define HCLR4(sc, reg, bits) \ 62 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 63 64struct pciecam_range { 65 uint32_t flags; 66 uint64_t pci_base; 67 uint64_t phys_base; 68 uint64_t size; 69}; 70 71struct pciecam_softc { 72 struct device sc_dev; 73 int sc_node; 74 bus_space_tag_t sc_iot; 75 bus_space_handle_t sc_ioh; 76 bus_dma_tag_t sc_dmat; 77 78 int sc_dw_quirk; 79 80 int sc_acells; 81 int sc_scells; 82 int sc_pacells; 83 int sc_pscells; 84 85 struct bus_space sc_bus; 86 struct pciecam_range *sc_pciranges; 87 int sc_pcirangeslen; 88 struct extent *sc_ioex; 89 struct extent *sc_memex; 90 char sc_ioex_name[32]; 91 char sc_memex_name[32]; 92 struct machine_pci_chipset sc_pc; 93}; 94 95struct pciecam_intr_handle { 96 struct machine_intr_handle pih_ih; 97 bus_dma_tag_t pih_dmat; 98 bus_dmamap_t pih_map; 99}; 100 101int pciecam_match(struct device *, void *, void *); 102void pciecam_attach(struct device *, struct device *, void *); 103void pciecam_attach_hook(struct device *, struct device *, struct pcibus_attach_args *); 104int pciecam_bus_maxdevs(void *, int); 105pcitag_t pciecam_make_tag(void *, int, int, int); 106void pciecam_decompose_tag(void *, pcitag_t, int *, int *, int *); 107int pciecam_conf_size(void *, pcitag_t); 108pcireg_t pciecam_conf_read(void *, pcitag_t, int); 109void pciecam_conf_write(void *, pcitag_t, int, pcireg_t); 110int pciecam_probe_device_hook(void *, struct pci_attach_args *); 111int pciecam_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 112const char *pciecam_intr_string(void *, pci_intr_handle_t); 113void *pciecam_intr_establish(void *, pci_intr_handle_t, int, 114 struct cpu_info *, int (*func)(void *), void *, char *); 115void pciecam_intr_disestablish(void *, void *); 116int pciecam_bs_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 117paddr_t pciecam_bs_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 118 119struct interrupt_controller pciecam_ic = { 120 .ic_barrier = intr_barrier 121}; 122 123struct cfattach pciecam_ca = { 124 sizeof (struct pciecam_softc), pciecam_match, pciecam_attach 125}; 126 127struct cfdriver pciecam_cd = { 128 NULL, "pciecam", DV_DULL 129}; 130 131int 132pciecam_match(struct device *parent, void *match, void *aux) 133{ 134 struct fdt_attach_args *faa = aux; 135 136 return (OF_is_compatible(faa->fa_node, "pci-host-ecam-generic") || 137 OF_is_compatible(faa->fa_node, "snps,dw-pcie-ecam")); 138} 139 140void 141pciecam_attach(struct device *parent, struct device *self, void *aux) 142{ 143 struct fdt_attach_args *faa = aux; 144 struct pciecam_softc *sc = (struct pciecam_softc *) self; 145 struct pcibus_attach_args pba; 146 uint32_t *ranges; 147 int i, j, nranges, rangeslen; 148 149 sc->sc_node = faa->fa_node; 150 sc->sc_iot = faa->fa_iot; 151 sc->sc_dmat = faa->fa_dmat; 152 153 if (OF_is_compatible(faa->fa_node, "snps,dw-pcie-ecam")) 154 sc->sc_dw_quirk = 1; 155 156 sc->sc_acells = OF_getpropint(sc->sc_node, "#address-cells", 157 faa->fa_acells); 158 sc->sc_scells = OF_getpropint(sc->sc_node, "#size-cells", 159 faa->fa_scells); 160 sc->sc_pacells = faa->fa_acells; 161 sc->sc_pscells = faa->fa_scells; 162 163 rangeslen = OF_getproplen(sc->sc_node, "ranges"); 164 if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) || 165 (rangeslen / sizeof(uint32_t)) % (sc->sc_acells + 166 sc->sc_pacells + sc->sc_scells)) 167 panic("pciecam_attach: invalid ranges property"); 168 169 ranges = malloc(rangeslen, M_TEMP, M_WAITOK); 170 OF_getpropintarray(sc->sc_node, "ranges", ranges, 171 rangeslen); 172 173 nranges = (rangeslen / sizeof(uint32_t)) / 174 (sc->sc_acells + sc->sc_pacells + sc->sc_scells); 175 sc->sc_pciranges = mallocarray(nranges, 176 sizeof(struct pciecam_range), M_TEMP, M_WAITOK); 177 sc->sc_pcirangeslen = nranges; 178 179 for (i = 0, j = 0; i < nranges; i++) { 180 sc->sc_pciranges[i].flags = ranges[j++]; 181 sc->sc_pciranges[i].pci_base = ranges[j++]; 182 if (sc->sc_acells - 1 == 2) { 183 sc->sc_pciranges[i].pci_base <<= 32; 184 sc->sc_pciranges[i].pci_base |= ranges[j++]; 185 } 186 sc->sc_pciranges[i].phys_base = ranges[j++]; 187 if (sc->sc_pacells == 2) { 188 sc->sc_pciranges[i].phys_base <<= 32; 189 sc->sc_pciranges[i].phys_base |= ranges[j++]; 190 } 191 sc->sc_pciranges[i].size = ranges[j++]; 192 if (sc->sc_scells == 2) { 193 sc->sc_pciranges[i].size <<= 32; 194 sc->sc_pciranges[i].size |= ranges[j++]; 195 } 196 } 197 198 free(ranges, M_TEMP, rangeslen); 199 200 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, 201 faa->fa_reg[0].size, 0, &sc->sc_ioh)) 202 panic("pciecam_attach: bus_space_map failed!"); 203 204 printf("\n"); 205 206 /* 207 * Map PCIe address space. 208 */ 209 snprintf(sc->sc_ioex_name, sizeof(sc->sc_ioex_name), 210 "%s pciio", sc->sc_dev.dv_xname); 211 sc->sc_ioex = extent_create(sc->sc_ioex_name, 0, (u_long)-1L, 212 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 213 214 snprintf(sc->sc_memex_name, sizeof(sc->sc_memex_name), 215 "%s pcimem", sc->sc_dev.dv_xname); 216 sc->sc_memex = extent_create(sc->sc_memex_name, 0, (u_long)-1L, 217 M_DEVBUF, NULL, 0, EX_NOWAIT | EX_FILLED); 218 219 for (i = 0; i < nranges; i++) { 220 if (sc->sc_pciranges[i].flags >> 24 == 0) 221 continue; 222 if (sc->sc_pciranges[i].flags >> 24 == 1) 223 extent_free(sc->sc_ioex, sc->sc_pciranges[i].pci_base, 224 sc->sc_pciranges[i].size, EX_NOWAIT); 225 else 226 extent_free(sc->sc_memex, sc->sc_pciranges[i].pci_base, 227 sc->sc_pciranges[i].size, EX_NOWAIT); 228 } 229 230 memcpy(&sc->sc_bus, sc->sc_iot, sizeof(sc->sc_bus)); 231 sc->sc_bus.bus_private = sc; 232 sc->sc_bus._space_map = pciecam_bs_map; 233 sc->sc_bus._space_mmap = pciecam_bs_mmap; 234 235 sc->sc_pc.pc_conf_v = sc; 236 sc->sc_pc.pc_attach_hook = pciecam_attach_hook; 237 sc->sc_pc.pc_bus_maxdevs = pciecam_bus_maxdevs; 238 sc->sc_pc.pc_make_tag = pciecam_make_tag; 239 sc->sc_pc.pc_decompose_tag = pciecam_decompose_tag; 240 sc->sc_pc.pc_conf_size = pciecam_conf_size; 241 sc->sc_pc.pc_conf_read = pciecam_conf_read; 242 sc->sc_pc.pc_conf_write = pciecam_conf_write; 243 sc->sc_pc.pc_probe_device_hook = pciecam_probe_device_hook; 244 245 sc->sc_pc.pc_intr_v = sc; 246 sc->sc_pc.pc_intr_map = pciecam_intr_map; 247 sc->sc_pc.pc_intr_map_msi = _pci_intr_map_msi; 248 sc->sc_pc.pc_intr_map_msix = _pci_intr_map_msix; 249 sc->sc_pc.pc_intr_string = pciecam_intr_string; 250 sc->sc_pc.pc_intr_establish = pciecam_intr_establish; 251 sc->sc_pc.pc_intr_disestablish = pciecam_intr_disestablish; 252 253 bzero(&pba, sizeof(pba)); 254 pba.pba_dmat = sc->sc_dmat; 255 256 pba.pba_busname = "pci"; 257 pba.pba_iot = &sc->sc_bus; 258 pba.pba_memt = &sc->sc_bus; 259 pba.pba_ioex = sc->sc_ioex; 260 pba.pba_memex = sc->sc_memex; 261 pba.pba_pmemex = sc->sc_memex; 262 pba.pba_pc = &sc->sc_pc; 263 pba.pba_domain = pci_ndomains++; 264 pba.pba_bus = 0; 265 266 if (OF_getproplen(sc->sc_node, "msi-map") > 0 || 267 OF_getproplen(sc->sc_node, "msi-parent") > 0) 268 pba.pba_flags |= PCI_FLAGS_MSI_ENABLED; 269 270 config_found(self, &pba, NULL); 271} 272 273void 274pciecam_attach_hook(struct device *parent, struct device *self, 275 struct pcibus_attach_args *pba) 276{ 277} 278 279int 280pciecam_bus_maxdevs(void *v, int bus) 281{ 282 struct pciecam_softc *sc = (struct pciecam_softc *)v; 283 284 if (bus == 0 && sc->sc_dw_quirk) 285 return 1; 286 return 32; 287} 288 289#define BUS_SHIFT 24 290#define DEVICE_SHIFT 19 291#define FNC_SHIFT 16 292 293pcitag_t 294pciecam_make_tag(void *sc, int bus, int dev, int fnc) 295{ 296 return (bus << BUS_SHIFT) | (dev << DEVICE_SHIFT) | (fnc << FNC_SHIFT); 297} 298 299void 300pciecam_decompose_tag(void *sc, pcitag_t tag, int *busp, int *devp, int *fncp) 301{ 302 if (busp != NULL) 303 *busp = (tag >> BUS_SHIFT) & 0xff; 304 if (devp != NULL) 305 *devp = (tag >> DEVICE_SHIFT) & 0x1f; 306 if (fncp != NULL) 307 *fncp = (tag >> FNC_SHIFT) & 0x7; 308} 309 310int 311pciecam_conf_size(void *sc, pcitag_t tag) 312{ 313 return PCIE_CONFIG_SPACE_SIZE; 314} 315 316pcireg_t 317pciecam_conf_read(void *v, pcitag_t tag, int reg) 318{ 319 struct pciecam_softc *sc = (struct pciecam_softc *)v; 320 int bus, dev, fn; 321 322 pciecam_decompose_tag(sc, tag, &bus, &dev, &fn); 323 324 return HREAD4(sc, PCIE_ADDR_OFFSET(bus, dev, fn, reg & ~0x3)); 325} 326 327void 328pciecam_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 329{ 330 struct pciecam_softc *sc = (struct pciecam_softc *)v; 331 int bus, dev, fn; 332 333 pciecam_decompose_tag(sc, tag, &bus, &dev, &fn); 334 335 HWRITE4(sc, PCIE_ADDR_OFFSET(bus, dev, fn, reg & ~0x3), data); 336} 337 338int 339pciecam_probe_device_hook(void *v, struct pci_attach_args *pa) 340{ 341 struct pciecam_softc *sc = (struct pciecam_softc *)v; 342 uint16_t rid; 343 int i; 344 345 rid = pci_requester_id(pa->pa_pc, pa->pa_tag); 346 pa->pa_dmat = iommu_device_map_pci(sc->sc_node, rid, pa->pa_dmat); 347 348 for (i = 0; i < sc->sc_pcirangeslen; i++) { 349 if (sc->sc_pciranges[i].flags >> 24 == 0) 350 continue; 351 iommu_reserve_region_pci(sc->sc_node, rid, 352 sc->sc_pciranges[i].pci_base, sc->sc_pciranges[i].size); 353 } 354 355 return 0; 356} 357 358int 359pciecam_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 360{ 361 ihp->ih_pc = pa->pa_pc; 362 ihp->ih_tag = pa->pa_intrtag; 363 ihp->ih_intrpin = pa->pa_intrpin; 364 ihp->ih_type = PCI_INTX; 365 366 return 0; 367} 368 369const char * 370pciecam_intr_string(void *sc, pci_intr_handle_t ih) 371{ 372 switch (ih.ih_type) { 373 case PCI_MSI: 374 return "msi"; 375 case PCI_MSIX: 376 return "msix"; 377 } 378 379 return "irq"; 380} 381 382void * 383pciecam_intr_establish(void *self, pci_intr_handle_t ih, int level, 384 struct cpu_info *ci, int (*func)(void *), void *arg, char *name) 385{ 386 struct pciecam_softc *sc = (struct pciecam_softc *)self; 387 struct pciecam_intr_handle *pih; 388 bus_dma_segment_t seg; 389 void *cookie; 390 391 KASSERT(ih.ih_type != PCI_NONE); 392 393 if (ih.ih_type != PCI_INTX) { 394 uint64_t addr, data; 395 396 /* Assume hardware passes Requester ID as sideband data. */ 397 data = pci_requester_id(ih.ih_pc, ih.ih_tag); 398 cookie = fdt_intr_establish_msi_cpu(sc->sc_node, &addr, 399 &data, level, ci, func, arg, (void *)name); 400 if (cookie == NULL) 401 return NULL; 402 403 pih = malloc(sizeof(*pih), M_DEVBUF, M_WAITOK); 404 pih->pih_ih.ih_ic = &pciecam_ic; 405 pih->pih_ih.ih_ih = cookie; 406 pih->pih_dmat = ih.ih_dmat; 407 408 if (bus_dmamap_create(pih->pih_dmat, sizeof(uint32_t), 1, 409 sizeof(uint32_t), 0, BUS_DMA_WAITOK, &pih->pih_map)) { 410 free(pih, M_DEVBUF, sizeof(*pih)); 411 fdt_intr_disestablish(cookie); 412 return NULL; 413 } 414 415 memset(&seg, 0, sizeof(seg)); 416 seg.ds_addr = addr; 417 seg.ds_len = sizeof(uint32_t); 418 419 if (bus_dmamap_load_raw(pih->pih_dmat, pih->pih_map, 420 &seg, 1, sizeof(uint32_t), BUS_DMA_WAITOK)) { 421 bus_dmamap_destroy(pih->pih_dmat, pih->pih_map); 422 free(pih, M_DEVBUF, sizeof(*pih)); 423 fdt_intr_disestablish(cookie); 424 return NULL; 425 } 426 427 addr = pih->pih_map->dm_segs[0].ds_addr; 428 if (ih.ih_type == PCI_MSIX) { 429 pci_msix_enable(ih.ih_pc, ih.ih_tag, 430 &sc->sc_bus, ih.ih_intrpin, addr, data); 431 } else 432 pci_msi_enable(ih.ih_pc, ih.ih_tag, addr, data); 433 } else { 434 int bus, dev, fn; 435 uint32_t reg[4]; 436 437 pciecam_decompose_tag(sc, ih.ih_tag, &bus, &dev, &fn); 438 439 reg[0] = bus << 16 | dev << 11 | fn << 8; 440 reg[1] = reg[2] = 0; 441 reg[3] = ih.ih_intrpin; 442 443 cookie = fdt_intr_establish_imap_cpu(sc->sc_node, reg, 444 sizeof(reg), level, ci, func, arg, name); 445 if (cookie == NULL) 446 return NULL; 447 448 pih = malloc(sizeof(*pih), M_DEVBUF, M_WAITOK); 449 pih->pih_ih.ih_ic = &pciecam_ic; 450 pih->pih_ih.ih_ih = cookie; 451 pih->pih_dmat = NULL; 452 } 453 454 return pih; 455} 456 457void 458pciecam_intr_disestablish(void *sc, void *cookie) 459{ 460 struct pciecam_intr_handle *pih = cookie; 461 462 fdt_intr_disestablish(pih->pih_ih.ih_ih); 463 if (pih->pih_dmat) { 464 bus_dmamap_unload(pih->pih_dmat, pih->pih_map); 465 bus_dmamap_destroy(pih->pih_dmat, pih->pih_map); 466 } 467 free(pih, M_DEVBUF, sizeof(*pih)); 468} 469 470/* 471 * Translate memory address if needed. 472 */ 473int 474pciecam_bs_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, 475 int flag, bus_space_handle_t *bshp) 476{ 477 struct pciecam_softc *sc = t->bus_private; 478 uint64_t physbase, pcibase, psize; 479 int i; 480 481 for (i = 0; i < sc->sc_pcirangeslen; i++) { 482 physbase = sc->sc_pciranges[i].phys_base; 483 pcibase = sc->sc_pciranges[i].pci_base; 484 psize = sc->sc_pciranges[i].size; 485 486 if (bpa >= pcibase && bpa + size <= pcibase + psize) 487 return bus_space_map(sc->sc_iot, 488 bpa - pcibase + physbase, size, flag, bshp); 489 } 490 491 return ENXIO; 492} 493 494paddr_t 495pciecam_bs_mmap(bus_space_tag_t t, bus_addr_t bpa, off_t off, 496 int prot, int flags) 497{ 498 struct pciecam_softc *sc = t->bus_private; 499 uint64_t physbase, pcibase, psize; 500 int i; 501 502 for (i = 0; i < sc->sc_pcirangeslen; i++) { 503 physbase = sc->sc_pciranges[i].phys_base; 504 pcibase = sc->sc_pciranges[i].pci_base; 505 psize = sc->sc_pciranges[i].size; 506 507 if (bpa >= pcibase && bpa < pcibase + psize) 508 return bus_space_mmap(sc->sc_iot, 509 bpa - pcibase + physbase, off, prot, flags); 510 } 511 512 return -1; 513} 514