iommuvar.h revision 1.18
1/* $OpenBSD: iommuvar.h,v 1.18 2019/06/25 22:30:56 dlg Exp $ */ 2/* $NetBSD: iommuvar.h,v 1.9 2001/10/07 20:30:41 eeh Exp $ */ 3 4/* 5 * Copyright (c) 2003 Henric Jungheim 6 * Copyright (c) 1999 Matthew R. Green 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 25 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 27 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33#ifndef _SPARC64_DEV_IOMMUVAR_H_ 34#define _SPARC64_DEV_IOMMUVAR_H_ 35 36#ifndef _SYS_TREE_H_ 37#include <sys/tree.h> 38#endif 39 40#include <sys/extent.h> 41#include <sys/mutex.h> 42 43/* 44 * per-Streaming Buffer state 45 */ 46struct strbuf_ctl { 47 bus_space_tag_t sb_bustag; /* streaming buffer registers */ 48 bus_space_handle_t sb_sb; /* Handle for our regs */ 49 struct iommu_state *sb_iommu; /* Associated IOMMU */ 50 /* 51 * Since implementing the per-map IOMMU state, these per-STC 52 * flush areas are not used other than as a boolean flag to indicate 53 * the presence of a working and enabled STC. For inconsistency's 54 * sake, the "sb" pointers of iommu_state are sometimes used for the 55 * same purpose. This should be consolidated. DEFINATELY, since 56 * mutex operations must happen at this level. 57 */ 58 struct mutex sb_mtx; /* one flush at a time */ 59 60 paddr_t sb_flushpa; /* to flush streaming buffers */ 61 volatile int64_t *sb_flush; 62}; 63 64/* 65 * per-map STC flush area 66 */ 67struct strbuf_flush { 68 char sbf_area[0x80]; /* Holds 64-byte long/aligned buffer */ 69 void *sbf_flush; /* Kernel virtual address of buffer */ 70 paddr_t sbf_flushpa; /* Physical address of buffer area */ 71}; 72 73/* 74 * per-map DVMA page table 75 */ 76struct iommu_page_entry { 77 SPLAY_ENTRY(iommu_page_entry) ipe_node; 78 paddr_t ipe_pa; 79 bus_addr_t ipe_va; 80}; 81struct iommu_page_map { 82 SPLAY_HEAD(iommu_page_tree, iommu_page_entry) ipm_tree; 83 int ipm_maxpage; /* Size of allocated page map */ 84 int ipm_pagecnt; /* Number of entries in use */ 85 struct iommu_page_entry ipm_map[1]; 86}; 87 88/* 89 * per-map IOMMU state 90 * 91 * This is what bus_dvmamap_t'c _dm_cookie should be pointing to. 92 */ 93struct iommu_map_state { 94 struct strbuf_flush ims_flush; /* flush should be first (alignment) */ 95 struct strbuf_ctl *ims_sb; /* Link to parent */ 96 struct iommu_state *ims_iommu; 97 int ims_flags; 98 struct extent_region ims_er; 99 struct iommu_page_map ims_map; /* map must be last (array at end) */ 100}; 101#define IOMMU_MAP_STREAM 1 102 103struct iommu_hw { 104 void (*ihw_enable)(struct iommu_state *); 105 106 unsigned long ihw_dvma_pa; 107 108 unsigned long ihw_bypass; 109 unsigned long ihw_bypass_nc; /* non-cached */ 110 unsigned long ihw_bypass_ro; /* relaxed ordering */ 111 112 unsigned int ihw_flags; 113#define IOMMU_HW_FLUSH_CACHE (1 << 0) 114}; 115 116extern const struct iommu_hw iommu_hw_default; 117 118/* 119 * per-IOMMU state 120 */ 121struct iommu_state { 122 paddr_t is_ptsb; /* TSB physical address */ 123 int64_t *is_tsb; /* TSB virtual address */ 124 int is_tsbsize; /* 0 = 8K, ... */ 125 u_int is_dvmabase; 126 u_int is_dvmaend; 127 int64_t is_cr; /* Control register value */ 128 struct mutex is_mtx; 129 struct extent *is_dvmamap; /* DVMA map for this instance */ 130 const struct iommu_hw *is_hw; 131 132 struct strbuf_ctl *is_sb[2]; /* Streaming buffers if any */ 133 134 paddr_t is_scratch; /* Scratch page */ 135 136 /* copies of our parents state, to allow us to be self contained */ 137 bus_space_tag_t is_bustag; /* our bus tag */ 138 bus_space_handle_t is_iommu; /* IOMMU registers */ 139 uint64_t is_devhandle; 140}; 141 142/* interfaces for PCI/SBus code */ 143void iommu_init(char *, const struct iommu_hw *, struct iommu_state *, 144 int, u_int32_t); 145void iommu_reset(struct iommu_state *); 146paddr_t iommu_extract(struct iommu_state *, bus_addr_t); 147int64_t iommu_lookup_tte(struct iommu_state *, bus_addr_t); 148int64_t iommu_fetch_tte(struct iommu_state *, paddr_t); 149/* bus_dma_tag_t implementation functions */ 150int iommu_dvmamap_create(bus_dma_tag_t, bus_dma_tag_t, struct strbuf_ctl *, 151 bus_size_t, int, bus_size_t, bus_size_t, int, bus_dmamap_t *); 152void iommu_dvmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 153int iommu_dvmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, void *, 154 bus_size_t, struct proc *, int); 155void iommu_dvmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 156int iommu_dvmamap_load_raw(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 157 bus_dma_segment_t *, int, bus_size_t, int); 158void iommu_dvmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 159 bus_addr_t, bus_size_t, int); 160int iommu_dvmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, bus_size_t, 161 bus_size_t, bus_size_t, bus_dma_segment_t *, int, int *, int); 162void iommu_dvmamem_free(bus_dma_tag_t, bus_dma_tag_t, bus_dma_segment_t *, 163 int); 164 165#define IOMMUREG_READ(is, reg) \ 166 bus_space_read_8((is)->is_bustag, \ 167 (is)->is_iommu, \ 168 IOMMUREG(reg)) 169 170#define IOMMUREG_WRITE(is, reg, v) \ 171 bus_space_write_8((is)->is_bustag, \ 172 (is)->is_iommu, \ 173 IOMMUREG(reg), \ 174 (v)) 175 176#endif /* _SPARC64_DEV_IOMMUVAR_H_ */ 177 178