1/* $OpenBSD: fhcreg.h,v 1.4 2007/05/01 19:44:56 kettenis Exp $ */ 2 3/* 4 * Copyright (c) 2004 Jason L. Wright (jason@thought.net). 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#define FHC_P_ID 0x00000000 /* ID */ 30#define FHC_P_RCS 0x00000010 /* reset ctrl/status */ 31#define FHC_P_CTRL 0x00000020 /* control */ 32#define FHC_P_BSR 0x00000030 /* board status */ 33#define FHC_P_ECC 0x00000040 /* ECC control */ 34#define FHC_P_JCTRL 0x000000f0 /* JTAG control */ 35 36#define FHC_P_CTRL_ICS 0x00100000 /* ignore centerplane sigs */ 37#define FHC_P_CTRL_FRST 0x00080000 /* fatal error reset enable */ 38#define FHC_P_CTRL_LFAT 0x00080000 /* AC/DC local error */ 39#define FHC_P_CTRL_SLINE 0x00010000 /* firmware sync line */ 40#define FHC_P_CTRL_DCD 0x00008000 /* DC/DC converter disable */ 41#define FHC_P_CTRL_POFF 0x00004000 /* AC/DC ctlr PLL disable */ 42#define FHC_P_CTRL_FOFF 0x00002000 /* FHC ctlr PLL disable */ 43#define FHC_P_CTRL_AOFF 0x00001000 /* cpu a sram low pwr mode */ 44#define FHC_P_CTRL_BOFF 0x00000800 /* cpu b sram low pwr mode */ 45#define FHC_P_CTRL_PSOFF 0x00000400 /* disable fhc power supply */ 46#define FHC_P_CTRL_IXIST 0x00000200 /* fhc notifies clock-board */ 47#define FHC_P_CTRL_XMSTR 0x00000100 /* xir master enable */ 48#define FHC_P_CTRL_LLED 0x00000040 /* left led (reversed) */ 49#define FHC_P_CTRL_MLED 0x00000020 /* middle led */ 50#define FHC_P_CTRL_RLED 0x00000010 /* right led */ 51#define FHC_P_CTRL_BPINS 0x00000003 /* spare bidir pins */ 52 53#define FHC_I_IGN 0x00000000 /* IGN register */ 54 55#define FHC_F_IMAP 0x00000000 /* fanfail intr map */ 56#define FHC_F_ICLR 0x00000010 /* fanfail intr clr */ 57 58#define FHC_S_IMAP 0x00000000 /* system intr map */ 59#define FHC_S_ICLR 0x00000010 /* system intr clr */ 60 61#define FHC_U_IMAP 0x00000000 /* uart intr map */ 62#define FHC_U_ICLR 0x00000010 /* uart intr clr */ 63 64#define FHC_T_IMAP 0x00000000 /* tod intr map */ 65#define FHC_T_ICLR 0x00000010 /* tod intr clr */ 66 67struct fhc_intr_reg { 68 u_int64_t imap; 69 u_int64_t unused_0; 70 u_int64_t iclr; 71 u_int64_t unused_1; 72}; 73 74#define FHC_INO(ino) ((ino) & 0x7) 75#define FHC_S_INO 0 76#define FHC_U_INO 1 77#define FHC_T_INO 2 78#define FHC_F_INO 3 79