shpcicvar.h revision 1.2
1/* $OpenBSD: shpcicvar.h,v 1.2 2006/10/07 20:52:40 miod Exp $ */ 2/* $NetBSD: shpcicvar.h,v 1.6 2005/12/11 12:18:58 christos Exp $ */ 3 4/*- 5 * Copyright (c) 2005 NONAKA Kimihiro 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <machine/bus.h> 31 32bus_space_tag_t shpcic_get_bus_io_tag(void); 33bus_space_tag_t shpcic_get_bus_mem_tag(void); 34bus_dma_tag_t shpcic_get_bus_dma_tag(void); 35 36int shpcic_bus_maxdevs(void *v, int busno); 37pcitag_t shpcic_make_tag(void *v, int bus, int device, int function); 38void shpcic_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp); 39pcireg_t shpcic_conf_read(void *v, pcitag_t tag, int reg); 40void shpcic_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data); 41 42int shpcic_set_intr_priority(int intr, int level); 43void *shpcic_intr_establish(int evtcode, int (*ih_func)(void *), void *ih_arg, 44 const char *ih_name); 45void shpcic_intr_disestablish(void *ih); 46 47/* 48 * shpcic io/mem bus space 49 */ 50int shpcic_iomem_map(void *v, bus_addr_t bpa, bus_size_t size, int flags, 51 bus_space_handle_t *bshp); 52void shpcic_iomem_unmap(void *v, bus_space_handle_t bsh, bus_size_t size); 53int shpcic_iomem_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset, 54 bus_size_t size, bus_space_handle_t *nbshp); 55int shpcic_iomem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend, 56 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags, 57 bus_addr_t *bpap, bus_space_handle_t *bshp); 58void shpcic_iomem_free(void *v, bus_space_handle_t bsh, bus_size_t size); 59 60/* read single */ 61uint8_t shpcic_io_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset); 62uint16_t shpcic_io_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset); 63uint32_t shpcic_io_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset); 64uint8_t shpcic_mem_read_1(void *v, bus_space_handle_t bsh, bus_size_t offset); 65uint16_t shpcic_mem_read_2(void *v, bus_space_handle_t bsh, bus_size_t offset); 66uint32_t shpcic_mem_read_4(void *v, bus_space_handle_t bsh, bus_size_t offset); 67 68/* read multi */ 69void shpcic_io_read_multi_1(void *v, bus_space_handle_t bsh, 70 bus_size_t offset, uint8_t *addr, bus_size_t count); 71void shpcic_io_read_multi_2(void *v, bus_space_handle_t bsh, 72 bus_size_t offset, uint16_t *addr, bus_size_t count); 73void shpcic_io_read_multi_4(void *v, bus_space_handle_t bsh, 74 bus_size_t offset, uint32_t *addr, bus_size_t count); 75void shpcic_mem_read_multi_1(void *v, bus_space_handle_t bsh, 76 bus_size_t offset, uint8_t *addr, bus_size_t count); 77void shpcic_mem_read_multi_2(void *v, bus_space_handle_t bsh, 78 bus_size_t offset, uint16_t *addr, bus_size_t count); 79void shpcic_mem_read_multi_4(void *v, bus_space_handle_t bsh, 80 bus_size_t offset, uint32_t *addr, bus_size_t count); 81 82/* read raw multi */ 83void shpcic_io_read_raw_multi_2(void *v, bus_space_handle_t bsh, 84 bus_size_t offset, uint8_t *addr, bus_size_t count); 85void shpcic_io_read_raw_multi_4(void *v, bus_space_handle_t bsh, 86 bus_size_t offset, uint8_t *addr, bus_size_t count); 87void shpcic_mem_read_raw_multi_2(void *v, bus_space_handle_t bsh, 88 bus_size_t offset, uint8_t *addr, bus_size_t count); 89void shpcic_mem_read_raw_multi_4(void *v, bus_space_handle_t bsh, 90 bus_size_t offset, uint8_t *addr, bus_size_t count); 91 92/* read region */ 93void shpcic_io_read_region_1(void *v, bus_space_handle_t bsh, 94 bus_size_t offset, uint8_t *addr, bus_size_t count); 95void shpcic_io_read_region_2(void *v, bus_space_handle_t bsh, 96 bus_size_t offset, uint16_t *addr, bus_size_t count); 97void shpcic_io_read_region_4(void *v, bus_space_handle_t bsh, 98 bus_size_t offset, uint32_t *addr, bus_size_t count); 99void shpcic_mem_read_region_1(void *v, bus_space_handle_t bsh, 100 bus_size_t offset, uint8_t *addr, bus_size_t count); 101void shpcic_mem_read_region_2(void *v, bus_space_handle_t bsh, 102 bus_size_t offset, uint16_t *addr, bus_size_t count); 103void shpcic_mem_read_region_4(void *v, bus_space_handle_t bsh, 104 bus_size_t offset, uint32_t *addr, bus_size_t count); 105 106/* read raw region */ 107void shpcic_io_read_raw_region_2(void *v, bus_space_handle_t bsh, 108 bus_size_t offset, uint8_t *addr, bus_size_t count); 109void shpcic_io_read_raw_region_4(void *v, bus_space_handle_t bsh, 110 bus_size_t offset, uint8_t *addr, bus_size_t count); 111void shpcic_mem_read_raw_region_2(void *v, bus_space_handle_t bsh, 112 bus_size_t offset, uint8_t *addr, bus_size_t count); 113void shpcic_mem_read_raw_region_4(void *v, bus_space_handle_t bsh, 114 bus_size_t offset, uint8_t *addr, bus_size_t count); 115 116/* write single */ 117void shpcic_io_write_1(void *v, bus_space_handle_t bsh, 118 bus_size_t offset, uint8_t data); 119void shpcic_io_write_2(void *v, bus_space_handle_t bsh, 120 bus_size_t offset, uint16_t data); 121void shpcic_io_write_4(void *v, bus_space_handle_t bsh, 122 bus_size_t offset, uint32_t data); 123void shpcic_mem_write_1(void *v, bus_space_handle_t bsh, 124 bus_size_t offset, uint8_t data); 125void shpcic_mem_write_2(void *v, bus_space_handle_t bsh, 126 bus_size_t offset, uint16_t data); 127void shpcic_mem_write_4(void *v, bus_space_handle_t bsh, 128 bus_size_t offset, uint32_t data); 129 130/* write multi */ 131void shpcic_io_write_multi_1(void *v, bus_space_handle_t bsh, 132 bus_size_t offset, const uint8_t *addr, bus_size_t count); 133void shpcic_io_write_multi_2(void *v, bus_space_handle_t bsh, 134 bus_size_t offset, const uint16_t *addr, bus_size_t count); 135void shpcic_io_write_multi_4(void *v, bus_space_handle_t bsh, 136 bus_size_t offset, const uint32_t *addr, bus_size_t count); 137void shpcic_mem_write_multi_1(void *v, bus_space_handle_t bsh, 138 bus_size_t offset, const uint8_t *addr, bus_size_t count); 139void shpcic_mem_write_multi_2(void *v, bus_space_handle_t bsh, 140 bus_size_t offset, const uint16_t *addr, bus_size_t count); 141void shpcic_mem_write_multi_4(void *v, bus_space_handle_t bsh, 142 bus_size_t offset, const uint32_t *addr, bus_size_t count); 143 144/* write raw multi */ 145void shpcic_io_write_raw_multi_2(void *v, bus_space_handle_t bsh, 146 bus_size_t offset, const uint8_t *addr, bus_size_t count); 147void shpcic_io_write_raw_multi_4(void *v, bus_space_handle_t bsh, 148 bus_size_t offset, const uint8_t *addr, bus_size_t count); 149void shpcic_mem_write_raw_multi_2(void *v, bus_space_handle_t bsh, 150 bus_size_t offset, const uint8_t *addr, bus_size_t count); 151void shpcic_mem_write_raw_multi_4(void *v, bus_space_handle_t bsh, 152 bus_size_t offset, const uint8_t *addr, bus_size_t count); 153 154/* write region */ 155void shpcic_io_write_region_1(void *v, bus_space_handle_t bsh, 156 bus_size_t offset, const uint8_t *addr, bus_size_t count); 157void shpcic_io_write_region_2(void *v, bus_space_handle_t bsh, 158 bus_size_t offset, const uint16_t *addr, bus_size_t count); 159void shpcic_io_write_region_4(void *v, bus_space_handle_t bsh, 160 bus_size_t offset, const uint32_t *addr, bus_size_t count); 161void shpcic_mem_write_region_1(void *v, bus_space_handle_t bsh, 162 bus_size_t offset, const uint8_t *addr, bus_size_t count); 163void shpcic_mem_write_region_2(void *v, bus_space_handle_t bsh, 164 bus_size_t offset, const uint16_t *addr, bus_size_t count); 165void shpcic_mem_write_region_4(void *v, bus_space_handle_t bsh, 166 bus_size_t offset, const uint32_t *addr, bus_size_t count); 167 168/* write raw region */ 169void shpcic_io_write_raw_region_2(void *v, bus_space_handle_t bsh, 170 bus_size_t offset, const uint8_t *addr, bus_size_t count); 171void shpcic_io_write_raw_region_4(void *v, bus_space_handle_t bsh, 172 bus_size_t offset, const uint8_t *addr, bus_size_t count); 173void shpcic_mem_write_raw_region_2(void *v, bus_space_handle_t bsh, 174 bus_size_t offset, const uint8_t *addr, bus_size_t count); 175void shpcic_mem_write_raw_region_4(void *v, bus_space_handle_t bsh, 176 bus_size_t offset, const uint8_t *addr, bus_size_t count); 177 178/* set multi */ 179void shpcic_io_set_multi_1(void *v, bus_space_handle_t bsh, 180 bus_size_t offset, uint8_t val, bus_size_t count); 181void shpcic_io_set_multi_2(void *v, bus_space_handle_t bsh, 182 bus_size_t offset, uint16_t val, bus_size_t count); 183void shpcic_io_set_multi_4(void *v, bus_space_handle_t bsh, 184 bus_size_t offset, uint32_t val, bus_size_t count); 185void shpcic_mem_set_multi_1(void *v, bus_space_handle_t bsh, 186 bus_size_t offset, uint8_t val, bus_size_t count); 187void shpcic_mem_set_multi_2(void *v, bus_space_handle_t bsh, 188 bus_size_t offset, uint16_t val, bus_size_t count); 189void shpcic_mem_set_multi_4(void *v, bus_space_handle_t bsh, 190 bus_size_t offset, uint32_t val, bus_size_t count); 191 192/* set region */ 193void shpcic_io_set_region_1(void *v, bus_space_handle_t bsh, 194 bus_size_t offset, uint8_t val, bus_size_t count); 195void shpcic_io_set_region_2(void *v, bus_space_handle_t bsh, 196 bus_size_t offset, uint16_t val, bus_size_t count); 197void shpcic_io_set_region_4(void *v, bus_space_handle_t bsh, 198 bus_size_t offset, uint32_t val, bus_size_t count); 199void shpcic_mem_set_region_1(void *v, bus_space_handle_t bsh, 200 bus_size_t offset, uint8_t val, bus_size_t count); 201void shpcic_mem_set_region_2(void *v, bus_space_handle_t bsh, 202 bus_size_t offset, uint16_t val, bus_size_t count); 203void shpcic_mem_set_region_4(void *v, bus_space_handle_t bsh, 204 bus_size_t offset, uint32_t val, bus_size_t count); 205 206/* copy region */ 207void shpcic_io_copy_region_1(void *v, bus_space_handle_t bsh1, 208 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 209 bus_size_t count); 210void shpcic_io_copy_region_2(void *v, bus_space_handle_t bsh1, 211 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 212 bus_size_t count); 213void shpcic_io_copy_region_4(void *v, bus_space_handle_t bsh1, 214 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 215 bus_size_t count); 216void shpcic_mem_copy_region_1(void *v, bus_space_handle_t bsh1, 217 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 218 bus_size_t count); 219void shpcic_mem_copy_region_2(void *v, bus_space_handle_t bsh1, 220 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 221 bus_size_t count); 222void shpcic_mem_copy_region_4(void *v, bus_space_handle_t bsh1, 223 bus_size_t off1, bus_space_handle_t bsh2, bus_size_t off2, 224 bus_size_t count); 225