1/* $OpenBSD: pte.h,v 1.3 2024/01/23 19:51:10 kettenis Exp $ */ 2 3/* 4 * Copyright (c) 2019 Brian Bamsch <bbamsch@google.com> 5 * Copyright (c) 2014 Dale Rahn <drahn@dalerahn.com> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19#ifndef _RISCV64_PTE_H_ 20#define _RISCV64_PTE_H_ 21 22#include "machine/vmparam.h" 23 24#define Lx_TABLE_ALIGN (4096) 25 26/* Block and Page attributes */ 27/* Bits 9:8 are reserved for software */ 28#define PTE_ATTR_MASK (0x3ffUL) 29#define PTE_SW_MANAGED (1 << 9) 30#define PTE_SW_WIRED (1 << 8) 31#define PTE_D (1 << 7) /* Dirty */ 32#define PTE_A (1 << 6) /* Accessed */ 33#define PTE_G (1 << 5) /* Global */ 34#define PTE_U (1 << 4) /* User */ 35#define PTE_X (1 << 3) /* Execute */ 36#define PTE_W (1 << 2) /* Write */ 37#define PTE_R (1 << 1) /* Read */ 38#define PTE_V (1 << 0) /* Valid */ 39#define PTE_RWX (PTE_R | PTE_W | PTE_X) 40#define PTE_RX (PTE_R | PTE_X) 41#define PTE_KERN (PTE_V | PTE_R | PTE_W | PTE_A | PTE_D) 42 43/* T-Head extended page attributes */ 44#define PTE_THEAD_SO (1ULL << 63) 45#define PTE_THEAD_C (1ULL << 62) 46#define PTE_THEAD_B (1ULL << 61) 47#define PTE_THEAD_SH (1ULL << 60) 48 49/* Level 0 table, 512GiB per entry */ 50#define L0_SHIFT 39 51 52/* Level 1 table, 1GiB per entry */ 53#define L1_SHIFT 30 54#define L1_SIZE (1UL << L1_SHIFT) 55#define L1_OFFSET (L1_SIZE - 1) 56 57/* Level 2 table, 2MiB per entry */ 58#define L2_SHIFT 21 59#define L2_SIZE (1UL << L2_SHIFT) 60#define L2_OFFSET (L2_SIZE - 1) 61 62/* Level 3 table, 4KiB per entry */ 63#define L3_SHIFT 12 64#define L3_SIZE (1UL << L3_SHIFT) 65#define L3_OFFSET (L3_SIZE - 1) 66 67/* page mapping */ 68#define Ln_ENTRIES_SHIFT 9 69#define Ln_ENTRIES (1 << Ln_ENTRIES_SHIFT) 70#define Ln_ADDR_MASK (Ln_ENTRIES - 1) 71#define Ln_TABLE_MASK ((1 << 12) - 1) 72 73/* physical page number mask */ 74#define PTE_RPGN (((1ULL << 56) - 1) & ~PAGE_MASK) 75 76#define PTE_PPN0_S 10 77#define PTE_PPN1_S 19 78#define PTE_PPN2_S 28 79#define PTE_PPN3_S 37 80#define PTE_SIZE 8 81 82#ifndef _LOCORE 83typedef uint64_t pt_entry_t; /* page table entry */ 84typedef uint64_t pn_t; /* page number */ 85#endif /* !_LOCORE */ 86 87#endif /* _RISCV64_PTE_H_ */ 88