1/*	$OpenBSD: pte.h,v 1.8 2023/01/25 09:53:53 kettenis Exp $	*/
2
3/*
4 * Copyright (c) 2020 Mark Kettenis <kettenis@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19#ifndef _MACHINE_PTE_H_
20#define _MACHINE_PTE_H_
21
22/*
23 * Page Table Entry bits that should work for all 64-bit POWER CPUs as
24 * well as the PowerPC 970.
25 */
26
27struct pte {
28	uint64_t pte_hi;
29	uint64_t pte_lo;
30};
31
32/* High doubleword: */
33#define PTE_VALID		0x0000000000000001ULL
34#define PTE_HID			0x0000000000000002ULL
35#define PTE_WIRED		0x0000000000000008ULL /* SW */
36#define PTE_AVPN		0x3fffffffffffff80ULL
37#define PTE_VSID_SHIFT		12
38
39/* Low doubleword: */
40#define PTE_PP			0x0000000000000003ULL
41#define PTE_RO			0x0000000000000003ULL
42#define PTE_RW			0x0000000000000002ULL
43#define PTE_N			0x0000000000000004ULL
44#define PTE_G			0x0000000000000008ULL
45#define PTE_M			0x0000000000000010ULL
46#define PTE_I			0x0000000000000020ULL
47#define PTE_W			0x0000000000000040ULL
48#define PTE_CHG			0x0000000000000080ULL
49#define PTE_REF			0x0000000000000100ULL
50#define PTE_AC			0x0000000000000200ULL
51#define PTE_RPGN		0x0ffffffffffff000ULL
52
53#define ADDR_PIDX		0x000000000ffff000ULL
54#define ADDR_PIDX_SHIFT		12
55#define ADDR_ESID_SHIFT		28
56#define ADDR_VSID_SHIFT		28
57
58struct pate {
59	uint64_t pate_htab;
60	uint64_t pate_prt;
61};
62
63#define SLBE_ESID_SHIFT	28
64#define SLBE_VALID	0x0000000008000000UL
65
66#define SLBV_VSID_SHIFT	12
67
68struct slb {
69	uint64_t slb_slbe;
70	uint64_t slb_slbv;
71};
72
73#define VSID_VRMA	0x1ffffff
74
75#define USER_ADDR	0xcfffffff00000000ULL
76#define USER_ESID	(USER_ADDR >> ADDR_ESID_SHIFT)
77#define SEGMENT_SIZE	(256 * 1024 * 1024ULL)
78#define SEGMENT_MASK 	(SEGMENT_SIZE - 1)
79
80#endif /* _MACHINE_PTE_H_ */
81