intr.h revision 1.22
1/* $OpenBSD: intr.h,v 1.22 2019/09/05 05:31:38 visa Exp $ */ 2 3/* 4 * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29#ifndef _MACHINE_INTR_H_ 30#define _MACHINE_INTR_H_ 31 32/* 33 * The interrupt level ipl is a logical level; per-platform interrupt 34 * code will turn it into the appropriate hardware interrupt masks 35 * values. 36 * 37 * Interrupt sources on the CPU are kept enabled regardless of the 38 * current ipl value; individual hardware sources interrupting while 39 * logically masked are masked on the fly, remembered as pending, and 40 * unmasked at the first splx() opportunity. 41 * 42 * An exception to this rule is the clock interrupt. Clock interrupts 43 * are always allowed to happen, but will (of course!) not be serviced 44 * if logically masked. The reason for this is that clocks usually sit on 45 * INT5 and cannot be easily masked if external hardware masking is used. 46 */ 47 48/* Interrupt priority `levels'; not mutually exclusive. */ 49#define IPL_NONE 0 /* nothing */ 50#define IPL_SOFTINT 1 /* soft interrupts */ 51#define IPL_SOFTCLOCK 1 /* soft clock interrupts */ 52#define IPL_SOFTNET 2 /* soft network interrupts */ 53#define IPL_SOFTTTY 3 /* soft terminal interrupts */ 54#define IPL_SOFTHIGH IPL_SOFTTTY /* highest level of soft interrupts */ 55#define IPL_BIO 4 /* block I/O */ 56#define IPL_AUDIO IPL_BIO 57#define IPL_NET 5 /* network */ 58#define IPL_TTY 6 /* terminal */ 59#define IPL_VM 7 /* memory allocation */ 60#define IPL_CLOCK 8 /* clock */ 61#define IPL_SCHED IPL_CLOCK 62#define IPL_HIGH 9 /* everything */ 63#define IPL_IPI 10 /* interprocessor interrupt */ 64#define NIPLS 11 /* number of levels */ 65 66#define IPL_MPFLOOR IPL_TTY 67 68/* Interrupt priority 'flags'. */ 69#define IPL_MPSAFE 0x100 70 71/* Interrupt sharing types. */ 72#define IST_NONE 0 /* none */ 73#define IST_PULSE 1 /* pulsed */ 74#define IST_EDGE 2 /* edge-triggered */ 75#define IST_LEVEL 3 /* level-triggered */ 76 77#define SINTBIT(q) (q) 78#define SINTMASK(q) (1 << SINTBIT(q)) 79 80/* Soft interrupt masks. */ 81 82#define SI_SOFTCLOCK 0 /* for IPL_SOFTCLOCK */ 83#define SI_SOFTNET 1 /* for IPL_SOFTNET */ 84#define SI_SOFTTTY 2 /* for IPL_SOFTTTY */ 85 86#define SI_NQUEUES 3 87 88#ifndef _LOCORE 89 90#include <sys/mutex.h> 91#include <sys/queue.h> 92 93struct soft_intrhand { 94 TAILQ_ENTRY(soft_intrhand) sih_list; 95 void (*sih_func)(void *); 96 void *sih_arg; 97 struct soft_intrq *sih_siq; 98 int sih_pending; 99}; 100 101struct soft_intrq { 102 TAILQ_HEAD(, soft_intrhand) siq_list; 103 int siq_si; 104 struct mutex siq_mtx; 105}; 106 107void softintr_disestablish(void *); 108void softintr_dispatch(int); 109void *softintr_establish(int, void (*)(void *), void *); 110void softintr_init(void); 111void softintr_schedule(void *); 112 113#define splbio() splraise(IPL_BIO) 114#define splnet() splraise(IPL_NET) 115#define spltty() splraise(IPL_TTY) 116#define splaudio() splraise(IPL_AUDIO) 117#define splvm() splraise(IPL_VM) 118#define splclock() splraise(IPL_CLOCK) 119#define splsched() splraise(IPL_SCHED) 120#define splhigh() splraise(IPL_HIGH) 121 122#define splsoftclock() splraise(IPL_SOFTCLOCK) 123#define splsoftnet() splraise(IPL_SOFTNET) 124#define splstatclock() splhigh() 125 126#define spl0() spllower(0) 127 128void splinit(void); 129 130#ifdef DIAGNOSTIC 131/* 132 * Although this function is implemented in MI code, it must be in this MD 133 * header because we don't want this header to include MI includes. 134 */ 135void splassert_fail(int, int, const char *); 136extern int splassert_ctl; 137void splassert_check(int, const char *); 138#define splassert(__wantipl) do { \ 139 if (splassert_ctl > 0) { \ 140 splassert_check(__wantipl, __func__); \ 141 } \ 142} while (0) 143#define splsoftassert(wantipl) splassert(wantipl) 144#else 145#define splassert(X) 146#define splsoftassert(X) 147#endif 148 149void register_splx_handler(void (*)(int)); 150int splraise(int); 151void splx(int); 152int spllower(int); 153 154void intr_barrier(void *); 155 156/* 157 * Low level interrupt dispatcher registration data. 158 */ 159 160/* Schedule priorities for base interrupts (CPU) */ 161#define INTPRI_IPI 0 162#define INTPRI_CLOCK 1 163/* other values are system-specific */ 164 165#define NLOWINT 16 /* Number of low level registrations possible */ 166 167extern uint32_t idle_mask; 168 169struct trapframe; 170void set_intr(int, uint32_t, uint32_t(*)(uint32_t, struct trapframe *)); 171 172uint32_t updateimask(uint32_t); 173void dosoftint(void); 174 175struct intr_controller { 176 void *ic_cookie; 177 void (*ic_init)(void); 178 void *(*ic_establish)(int, int, int (*)(void *), void *, 179 const char *); 180 void *(*ic_establish_fdt_idx)(void *, int, int, int, 181 int (*)(void *), void *, const char *); 182 void (*ic_disestablish)(void *); 183 void (*ic_intr_barrier)(void *); 184 185#ifdef MULTIPROCESSOR 186 int (*ic_ipi_establish)(int (*)(void *), cpuid_t); 187 void (*ic_ipi_set)(cpuid_t); 188 void (*ic_ipi_clear)(cpuid_t); 189#endif /* MULTIPROCESSOR */ 190 191 int ic_node; 192 int ic_phandle; 193 LIST_ENTRY(intr_controller) ic_list; 194}; 195 196#ifdef MULTIPROCESSOR 197#define ENABLEIPI() updateimask(~CR_INT_1) /* enable IPI interrupt level */ 198#endif 199 200void *octeon_intr_establish(int, int, int (*)(void *), 201 void *, const char *); 202void octeon_intr_disestablish(void *); 203void octeon_intr_init(void); 204void octeon_intr_register(struct intr_controller *); 205 206void *octeon_intr_establish_fdt(int, int, int (*)(void *), 207 void *, const char *); 208void *octeon_intr_establish_fdt_idx(int, int, int, int (*)(void *), 209 void *, const char *); 210void octeon_intr_disestablish_fdt(void *); 211 212#endif /* _LOCORE */ 213 214#endif /* _MACHINE_INTR_H_ */ 215