intr.h revision 1.2
1/* $OpenBSD: intr.h,v 1.2 2011/05/08 13:24:55 syuu Exp $ */ 2 3/* 4 * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29#ifndef _MACHINE_INTR_H_ 30#define _MACHINE_INTR_H_ 31 32/* 33 * The interrupt level ipl is a logical level; per-platform interrupt 34 * code will turn it into the appropriate hardware interrupt masks 35 * values. 36 * 37 * Interrupt sources on the CPU are kept enabled regardless of the 38 * current ipl value; individual hardware sources interrupting while 39 * logically masked are masked on the fly, remembered as pending, and 40 * unmasked at the first splx() opportunity. 41 * 42 * An exception to this rule is the clock interrupt. Clock interrupts 43 * are always allowed to happen, but will (of course!) not be serviced 44 * if logically masked. The reason for this is that clocks usually sit on 45 * INT5 and cannot be easily masked if external hardware masking is used. 46 */ 47 48/* Interrupt priority `levels'; not mutually exclusive. */ 49#define IPL_NONE 0 /* nothing */ 50#define IPL_SOFTINT 1 /* soft interrupts */ 51#define IPL_BIO 2 /* block I/O */ 52#define IPL_AUDIO IPL_BIO 53#define IPL_NET 3 /* network */ 54#define IPL_TTY 4 /* terminal */ 55#define IPL_VM 5 /* memory allocation */ 56#define IPL_CLOCK 6 /* clock */ 57#define IPL_SCHED IPL_CLOCK 58#define IPL_HIGH 7 /* everything */ 59#define IPL_IPI 8 /* interprocessor interrupt */ 60#define NIPLS 9 /* Number of levels */ 61 62/* Interrupt sharing types. */ 63#define IST_NONE 0 /* none */ 64#define IST_PULSE 1 /* pulsed */ 65#define IST_EDGE 2 /* edge-triggered */ 66#define IST_LEVEL 3 /* level-triggered */ 67 68#define SINTBIT(q) (q) 69#define SINTMASK(q) (1 << SINTBIT(q)) 70 71/* Soft interrupt masks. */ 72 73#define IPL_SOFT 0 74#define IPL_SOFTCLOCK 1 75#define IPL_SOFTNET 2 76#define IPL_SOFTTTY 3 77 78#define SI_SOFT 0 /* for IPL_SOFT */ 79#define SI_SOFTCLOCK 1 /* for IPL_SOFTCLOCK */ 80#define SI_SOFTNET 2 /* for IPL_SOFTNET */ 81#define SI_SOFTTTY 3 /* for IPL_SOFTTTY */ 82 83#define SI_NQUEUES 4 84 85#ifndef _LOCORE 86 87#include <machine/mutex.h> 88#include <sys/queue.h> 89 90struct soft_intrhand { 91 TAILQ_ENTRY(soft_intrhand) sih_list; 92 void (*sih_func)(void *); 93 void *sih_arg; 94 struct soft_intrq *sih_siq; 95 int sih_pending; 96}; 97 98struct soft_intrq { 99 TAILQ_HEAD(, soft_intrhand) siq_list; 100 int siq_si; 101 struct mutex siq_mtx; 102}; 103 104void softintr_disestablish(void *); 105void softintr_dispatch(int); 106void *softintr_establish(int, void (*)(void *), void *); 107void softintr_init(void); 108void softintr_schedule(void *); 109 110/* XXX For legacy software interrupts. */ 111extern struct soft_intrhand *softnet_intrhand; 112 113#define setsoftnet() softintr_schedule(softnet_intrhand) 114 115#define splsoft() splraise(IPL_SOFTINT) 116#define splbio() splraise(IPL_BIO) 117#define splnet() splraise(IPL_NET) 118#define spltty() splraise(IPL_TTY) 119#define splaudio() splraise(IPL_AUDIO) 120#define splvm() splraise(IPL_VM) 121#define splclock() splraise(IPL_CLOCK) 122#define splsched() splraise(IPL_SCHED) 123#define splhigh() splraise(IPL_HIGH) 124 125#define splsoftclock() splsoft() 126#define splsoftnet() splsoft() 127#define splstatclock() splhigh() 128 129#define spllock() splhigh() 130#define spl0() spllower(0) 131 132void splinit(void); 133 134#define splassert(X) 135#define splsoftassert(X) 136 137/* Inlines */ 138static __inline void register_splx_handler(void (*)(int)); 139 140typedef void (int_f)(int); 141extern int_f *splx_hand; 142 143static __inline void 144register_splx_handler(void(*handler)(int)) 145{ 146 splx_hand = handler; 147} 148 149int splraise(int); 150void splx(int); 151int spllower(int); 152 153/* 154 * Interrupt control struct used by interrupt dispatchers 155 * to hold interrupt handler info. 156 */ 157 158#include <sys/evcount.h> 159 160struct intrhand { 161 struct intrhand *ih_next; 162 int (*ih_fun)(void *); 163 void *ih_arg; 164 int ih_level; 165 int ih_irq; 166 struct evcount ih_count; 167 int ih_flags; 168#define IH_ALLOCATED 0x01 169}; 170 171/* 172 * Low level interrupt dispatcher registration data. 173 */ 174 175/* Schedule priorities for base interrupts (CPU) */ 176#define INTPRI_IPI 0 177#define INTPRI_CLOCK 1 178/* other values are system-specific */ 179 180#define NLOWINT 16 /* Number of low level registrations possible */ 181 182extern uint32_t idle_mask; 183 184struct trap_frame; 185void set_intr(int, uint32_t, uint32_t(*)(uint32_t, struct trap_frame *)); 186 187uint32_t updateimask(uint32_t); 188void dosoftint(void); 189 190#ifdef MULTIPROCESSOR 191#define ENABLEIPI() updateimask(~CR_INT_1) /* enable IPI interrupt level */ 192#endif 193void octeon_intr_init(void); 194void octeon_setintrmask(int); 195void *octeon_intr_establish(int, int, int (*)(void *), 196 void *, const char *); 197void octeon_intr_disestablish(void *); 198void octeon_intr_init(void); 199 200#endif /* _LOCORE */ 201 202#endif /* _MACHINE_INTR_H_ */ 203