intr.h revision 1.14 
1/*	$OpenBSD: intr.h,v 1.14 2017/07/28 14:51:46 visa Exp $ */
2
3/*
4 * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29#ifndef _MACHINE_INTR_H_
30#define _MACHINE_INTR_H_
31
32/*
33 * The interrupt level ipl is a logical level; per-platform interrupt
34 * code will turn it into the appropriate hardware interrupt masks
35 * values.
36 *
37 * Interrupt sources on the CPU are kept enabled regardless of the
38 * current ipl value; individual hardware sources interrupting while
39 * logically masked are masked on the fly, remembered as pending, and
40 * unmasked at the first splx() opportunity.
41 *
42 * An exception to this rule is the clock interrupt. Clock interrupts
43 * are always allowed to happen, but will (of course!) not be serviced
44 * if logically masked.  The reason for this is that clocks usually sit on
45 * INT5 and cannot be easily masked if external hardware masking is used.
46 */
47
48/* Interrupt priority `levels'; not mutually exclusive. */
49#define	IPL_NONE	0	/* nothing */
50#define	IPL_SOFTINT	1	/* soft interrupts */
51#define	IPL_BIO		2	/* block I/O */
52#define IPL_AUDIO	IPL_BIO
53#define	IPL_NET		3	/* network */
54#define	IPL_TTY		4	/* terminal */
55#define	IPL_VM		5	/* memory allocation */
56#define	IPL_CLOCK	6	/* clock */
57#define	IPL_SCHED	IPL_CLOCK
58#define	IPL_HIGH	7	/* everything */
59#define	IPL_IPI         8       /* interprocessor interrupt */
60#define	NIPLS		9	/* Number of levels */
61
62#define IPL_MPFLOOR	IPL_TTY
63
64/* Interrupt priority 'flags'. */
65#define	IPL_MPSAFE	0x100
66
67/* Interrupt sharing types. */
68#define	IST_NONE	0	/* none */
69#define	IST_PULSE	1	/* pulsed */
70#define	IST_EDGE	2	/* edge-triggered */
71#define	IST_LEVEL	3	/* level-triggered */
72
73#define	SINTBIT(q)	(q)
74#define	SINTMASK(q)	(1 << SINTBIT(q))
75
76/* Soft interrupt masks. */
77
78#define	IPL_SOFT	0
79#define	IPL_SOFTCLOCK	1
80#define	IPL_SOFTNET	2
81#define	IPL_SOFTTTY	3
82
83#define	SI_SOFT		0	/* for IPL_SOFT */
84#define	SI_SOFTCLOCK	1	/* for IPL_SOFTCLOCK */
85#define	SI_SOFTNET	2	/* for IPL_SOFTNET */
86#define	SI_SOFTTTY	3	/* for IPL_SOFTTTY */
87
88#define	SI_NQUEUES	4
89
90#ifndef _LOCORE
91
92#include <machine/mutex.h>
93#include <sys/queue.h>
94
95struct soft_intrhand {
96	TAILQ_ENTRY(soft_intrhand) sih_list;
97	void	(*sih_func)(void *);
98	void	*sih_arg;
99	struct soft_intrq *sih_siq;
100	int	sih_pending;
101};
102
103struct soft_intrq {
104	TAILQ_HEAD(, soft_intrhand) siq_list;
105	int siq_si;
106	struct mutex siq_mtx;
107};
108
109void	 softintr_disestablish(void *);
110void	 softintr_dispatch(int);
111void	*softintr_establish(int, void (*)(void *), void *);
112void	 softintr_init(void);
113void	 softintr_schedule(void *);
114
115#define	splsoft()	splraise(IPL_SOFTINT)
116#define splbio()	splraise(IPL_BIO)
117#define splnet()	splraise(IPL_NET)
118#define spltty()	splraise(IPL_TTY)
119#define splaudio()	splraise(IPL_AUDIO)
120#define splvm()		splraise(IPL_VM)
121#define splclock()	splraise(IPL_CLOCK)
122#define splsched()	splraise(IPL_SCHED)
123#define splhigh()	splraise(IPL_HIGH)
124
125#define splsoftclock()	splsoft()
126#define splsoftnet()	splsoft()
127#define splstatclock()	splhigh()
128
129#define spllock()	splhigh()
130#define spl0()		spllower(0)
131
132void	splinit(void);
133
134#define	splassert(X)
135#define	splsoftassert(X)
136
137void	register_splx_handler(void (*)(int));
138int	splraise(int);
139void	splx(int);
140int	spllower(int);
141
142/*
143 * Interrupt control struct used by interrupt dispatchers
144 * to hold interrupt handler info.
145 */
146
147#include <sys/evcount.h>
148
149struct intrhand {
150	struct	intrhand	*ih_next;
151	int			(*ih_fun)(void *);
152	void			*ih_arg;
153	int			 ih_level;
154	int			 ih_irq;
155	struct evcount		 ih_count;
156	int			 ih_flags;
157#define	IH_ALLOCATED		0x01
158#define	IH_MPSAFE		0x02
159};
160
161void	intr_barrier(void *);
162
163/*
164 * Low level interrupt dispatcher registration data.
165 */
166
167/* Schedule priorities for base interrupts (CPU) */
168#define	INTPRI_IPI	0
169#define	INTPRI_CLOCK	1
170/* other values are system-specific */
171
172#define NLOWINT	16		/* Number of low level registrations possible */
173
174extern uint32_t idle_mask;
175
176struct trapframe;
177void	set_intr(int, uint32_t, uint32_t(*)(uint32_t, struct trapframe *));
178
179uint32_t updateimask(uint32_t);
180void	dosoftint(void);
181
182struct intr_controller {
183	void	  *ic_cookie;
184	void	 (*ic_init)(void);
185	void	*(*ic_establish)(int, int, int (*)(void *), void *,
186		    const char *);
187	void	*(*ic_establish_fdt_idx)(void *, int, int, int,
188		    int (*)(void *), void *, const char *);
189	void	 (*ic_disestablish)(void *);
190
191#ifdef MULTIPROCESSOR
192	int	 (*ic_ipi_establish)(int (*)(void *), cpuid_t);
193	void	 (*ic_ipi_set)(cpuid_t);
194	void	 (*ic_ipi_clear)(cpuid_t);
195#endif /* MULTIPROCESSOR */
196
197	int	   ic_node;
198	int	   ic_phandle;
199	LIST_ENTRY(intr_controller) ic_list;
200};
201
202#ifdef MULTIPROCESSOR
203#define ENABLEIPI() updateimask(~CR_INT_1) /* enable IPI interrupt level */
204#endif
205
206void   *octeon_intr_establish(int, int, int (*)(void *),
207	    void *, const char *);
208void	octeon_intr_disestablish(void *);
209void	octeon_intr_init(void);
210void	octeon_intr_register(struct intr_controller *);
211
212void	*octeon_intr_establish_fdt(int, int, int (*)(void *),
213	    void *, const char *);
214void	*octeon_intr_establish_fdt_idx(int, int, int, int (*)(void *),
215	    void *, const char *);
216void	 octeon_intr_disestablish_fdt(void *);
217
218/* XXX Needed by 'MI' code in sys/dev/fdt. */
219#define arm_intr_establish_fdt		octeon_intr_establish_fdt
220#define arm_intr_disestablish_fdt	octeon_intr_disestablish_fdt
221
222#endif /* _LOCORE */
223
224#endif /* _MACHINE_INTR_H_ */
225