intr.h revision 1.10
1/* $OpenBSD: intr.h,v 1.10 2017/06/11 10:01:23 visa Exp $ */ 2 3/* 4 * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29#ifndef _MACHINE_INTR_H_ 30#define _MACHINE_INTR_H_ 31 32/* 33 * The interrupt level ipl is a logical level; per-platform interrupt 34 * code will turn it into the appropriate hardware interrupt masks 35 * values. 36 * 37 * Interrupt sources on the CPU are kept enabled regardless of the 38 * current ipl value; individual hardware sources interrupting while 39 * logically masked are masked on the fly, remembered as pending, and 40 * unmasked at the first splx() opportunity. 41 * 42 * An exception to this rule is the clock interrupt. Clock interrupts 43 * are always allowed to happen, but will (of course!) not be serviced 44 * if logically masked. The reason for this is that clocks usually sit on 45 * INT5 and cannot be easily masked if external hardware masking is used. 46 */ 47 48/* Interrupt priority `levels'; not mutually exclusive. */ 49#define IPL_NONE 0 /* nothing */ 50#define IPL_SOFTINT 1 /* soft interrupts */ 51#define IPL_BIO 2 /* block I/O */ 52#define IPL_AUDIO IPL_BIO 53#define IPL_NET 3 /* network */ 54#define IPL_TTY 4 /* terminal */ 55#define IPL_VM 5 /* memory allocation */ 56#define IPL_CLOCK 6 /* clock */ 57#define IPL_SCHED IPL_CLOCK 58#define IPL_HIGH 7 /* everything */ 59#define IPL_IPI 8 /* interprocessor interrupt */ 60#define NIPLS 9 /* Number of levels */ 61 62#define IPL_MPFLOOR IPL_TTY 63 64/* Interrupt priority 'flags'. */ 65#define IPL_MPSAFE 0x100 66 67/* Interrupt sharing types. */ 68#define IST_NONE 0 /* none */ 69#define IST_PULSE 1 /* pulsed */ 70#define IST_EDGE 2 /* edge-triggered */ 71#define IST_LEVEL 3 /* level-triggered */ 72 73#define SINTBIT(q) (q) 74#define SINTMASK(q) (1 << SINTBIT(q)) 75 76/* Soft interrupt masks. */ 77 78#define IPL_SOFT 0 79#define IPL_SOFTCLOCK 1 80#define IPL_SOFTNET 2 81#define IPL_SOFTTTY 3 82 83#define SI_SOFT 0 /* for IPL_SOFT */ 84#define SI_SOFTCLOCK 1 /* for IPL_SOFTCLOCK */ 85#define SI_SOFTNET 2 /* for IPL_SOFTNET */ 86#define SI_SOFTTTY 3 /* for IPL_SOFTTTY */ 87 88#define SI_NQUEUES 4 89 90#ifndef _LOCORE 91 92#include <machine/mutex.h> 93#include <sys/queue.h> 94 95struct soft_intrhand { 96 TAILQ_ENTRY(soft_intrhand) sih_list; 97 void (*sih_func)(void *); 98 void *sih_arg; 99 struct soft_intrq *sih_siq; 100 int sih_pending; 101}; 102 103struct soft_intrq { 104 TAILQ_HEAD(, soft_intrhand) siq_list; 105 int siq_si; 106 struct mutex siq_mtx; 107}; 108 109void softintr_disestablish(void *); 110void softintr_dispatch(int); 111void *softintr_establish(int, void (*)(void *), void *); 112void softintr_init(void); 113void softintr_schedule(void *); 114 115/* XXX For legacy software interrupts. */ 116extern struct soft_intrhand *softnet_intrhand; 117 118#define setsoftnet() softintr_schedule(softnet_intrhand) 119 120#define splsoft() splraise(IPL_SOFTINT) 121#define splbio() splraise(IPL_BIO) 122#define splnet() splraise(IPL_NET) 123#define spltty() splraise(IPL_TTY) 124#define splaudio() splraise(IPL_AUDIO) 125#define splvm() splraise(IPL_VM) 126#define splclock() splraise(IPL_CLOCK) 127#define splsched() splraise(IPL_SCHED) 128#define splhigh() splraise(IPL_HIGH) 129 130#define splsoftclock() splsoft() 131#define splsoftnet() splsoft() 132#define splstatclock() splhigh() 133 134#define spllock() splhigh() 135#define spl0() spllower(0) 136 137void splinit(void); 138 139#define splassert(X) 140#define splsoftassert(X) 141 142void register_splx_handler(void (*)(int)); 143int splraise(int); 144void splx(int); 145int spllower(int); 146 147/* 148 * Interrupt control struct used by interrupt dispatchers 149 * to hold interrupt handler info. 150 */ 151 152#include <sys/evcount.h> 153 154struct intrhand { 155 struct intrhand *ih_next; 156 int (*ih_fun)(void *); 157 void *ih_arg; 158 int ih_level; 159 int ih_irq; 160 struct evcount ih_count; 161 int ih_flags; 162#define IH_ALLOCATED 0x01 163#define IH_MPSAFE 0x02 164}; 165 166void intr_barrier(void *); 167 168/* 169 * Low level interrupt dispatcher registration data. 170 */ 171 172/* Schedule priorities for base interrupts (CPU) */ 173#define INTPRI_IPI 0 174#define INTPRI_CLOCK 1 175/* other values are system-specific */ 176 177#define NLOWINT 16 /* Number of low level registrations possible */ 178 179extern uint32_t idle_mask; 180 181struct trapframe; 182void set_intr(int, uint32_t, uint32_t(*)(uint32_t, struct trapframe *)); 183 184uint32_t updateimask(uint32_t); 185void dosoftint(void); 186 187#ifdef MULTIPROCESSOR 188#define ENABLEIPI() updateimask(~CR_INT_1) /* enable IPI interrupt level */ 189#endif 190void octeon_intr_init(void); 191void octeon_setintrmask(int); 192void *octeon_intr_establish(int, int, int (*)(void *), 193 void *, const char *); 194void octeon_intr_disestablish(void *); 195void octeon_intr_init(void); 196 197void *octeon_intr_establish_fdt(int, int, int (*)(void *), 198 void *, const char *); 199void *octeon_intr_establish_fdt_idx(int, int, int, int (*)(void *), 200 void *, const char *); 201void octeon_intr_disestablish_fdt(void *); 202 203#endif /* _LOCORE */ 204 205#endif /* _MACHINE_INTR_H_ */ 206