pte.h revision 1.21
1/* $OpenBSD: pte.h,v 1.21 2016/10/09 03:29:53 visa Exp $ */ 2 3/* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department and Ralph Campbell. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: Utah Hdr: pte.h 1.11 89/09/03 37 * from: @(#)pte.h 8.1 (Berkeley) 6/10/93 38 */ 39 40/* 41 * R4000 and R8000 hardware page table entries 42 */ 43 44#ifndef _LOCORE 45 46/* 47 * Structure defining a TLB entry data set. 48 */ 49struct tlb_entry { 50 u_int64_t tlb_mask; 51 u_int64_t tlb_hi; 52 u_int64_t tlb_lo0; 53 u_int64_t tlb_lo1; 54}; 55 56u_int tlb_get_pid(void); 57void tlb_read(unsigned int, struct tlb_entry *); 58 59#ifdef MIPS_PTE64 60typedef u_int64_t pt_entry_t; 61#else 62typedef u_int32_t pt_entry_t; 63#endif 64 65#endif /* _LOCORE */ 66 67#ifdef MIPS_PTE64 68#define PTE_BITS 64 69#define PTE_LOAD ld 70#define PTE_LOG 3 71#define PTE_OFFS 8 72#else 73#define PTE_BITS 32 74#define PTE_LOAD lwu 75#define PTE_LOG 2 76#define PTE_OFFS 4 77#endif 78 79#if defined(CPU_MIPS64R2) && !defined(CPU_LOONGSON2) 80#define PTE_CLEAR_SWBITS(reg) \ 81 .set push; \ 82 .set mips64r2; \ 83 /* Clear SW bits around PG_XI. */ \ 84 dins reg, zero, (PTE_BITS - 1), 1; \ 85 dins reg, zero, PG_FRAMEBITS, (PTE_BITS - 2 - PG_FRAMEBITS); \ 86 .set pop 87#else 88#define PTE_CLEAR_SWBITS(reg) \ 89 /* Clear SW bits left of PG_FRAMEBITS. */ \ 90 dsll reg, reg, (64 - PG_FRAMEBITS); \ 91 dsrl reg, reg, (64 - PG_FRAMEBITS) 92#endif 93 94/* entryhi values */ 95 96#ifndef CPU_R8000 97#define PG_HVPN (-2 * PAGE_SIZE) /* Hardware page number mask */ 98#define PG_ODDPG PAGE_SIZE 99#endif /* !R8000 */ 100 101/* Address space ID */ 102#ifdef CPU_R8000 103#define PG_ASID_MASK 0x0000000000000ff0 104#define PG_ASID_SHIFT 4 105#define ICACHE_ASID_SHIFT 40 106#define MIN_USER_ASID 0 107#else 108#define PG_ASID_MASK 0x00000000000000ff 109#define PG_ASID_SHIFT 0 110#define MIN_USER_ASID 1 111#endif 112#define PG_ASID_COUNT 256 /* Number of available ASID */ 113 114/* entrylo values */ 115 116#ifdef CPU_R8000 117#define PG_FRAME 0xfffff000 118#define PG_SHIFT 0 119#else 120#ifdef MIPS_PTE64 121#define PG_FRAMEBITS 61 122#else 123#define PG_FRAMEBITS 29 124#endif 125#define PG_FRAME ((1ULL << PG_FRAMEBITS) - (1ULL << PG_SHIFT)) 126#define PG_SHIFT 6 127#endif 128 129/* software pte bits - not put in entrylo */ 130#if defined(CPU_R8000) 131#define PG_WIRED 0x00000010 132#define PG_RO 0x00000020 133#elif defined(CPU_R4000) 134#define PG_WIRED (1ULL << (PG_FRAMEBITS + 2)) 135#define PG_RO (1ULL << (PG_FRAMEBITS + 1)) 136#define PG_SP (1ULL << (PG_FRAMEBITS + 0)) /* ``special'' bit */ 137#else 138#define PG_WIRED (1ULL << (PG_FRAMEBITS + 2)) 139 /* 1ULL << (PG_FRAMEBITS + 1) is PG_XI. */ 140#define PG_RO (1ULL << (PG_FRAMEBITS + 0)) 141#endif 142 143#ifdef CPU_MIPS64R2 144#define PG_XI (1ULL << (PTE_BITS - 2)) 145#else 146#define PG_XI 0x00000000 147#endif 148 149#define PG_NV 0x00000000 150#ifdef CPU_R8000 151#define PG_G 0x00000000 /* no such concept for R8000 */ 152#define PG_V 0x00000080 153#define PG_M 0x00000100 154#define PG_CCA_SHIFT 9 155#else 156#define PG_G 0x00000001 157#define PG_V 0x00000002 158#define PG_M 0x00000004 159#define PG_CCA_SHIFT 3 160#endif 161#define PG_NV 0x00000000 162 163#define PG_UNCACHED (CCA_NC << PG_CCA_SHIFT) 164#define PG_CACHED_NC (CCA_NONCOHERENT << PG_CCA_SHIFT) 165#define PG_CACHED_CE (CCA_COHERENT_EXCL << PG_CCA_SHIFT) 166#define PG_CACHED_CEW (CCA_COHERENT_EXCLWRITE << PG_CCA_SHIFT) 167#define PG_CACHED (CCA_CACHED << PG_CCA_SHIFT) 168#define PG_CACHEMODE (7 << PG_CCA_SHIFT) 169 170#define PG_ATTR (PG_CACHEMODE | PG_M | PG_V | PG_G) 171#define PG_ROPAGE (PG_V | PG_RO | PG_CACHED) /* Write protected */ 172#define PG_RWPAGE (PG_V | PG_M | PG_CACHED) /* Not w-prot not clean */ 173#define PG_CWPAGE (PG_V | PG_CACHED) /* Not w-prot but clean */ 174#define PG_IOPAGE (PG_G | PG_V | PG_M | PG_UNCACHED) 175 176#define pfn_to_pad(pa) ((((paddr_t)pa) & PG_FRAME) << PG_SHIFT) 177#define vad_to_pfn(va) (((va) >> PG_SHIFT) & PG_FRAME) 178 179#ifndef CPU_R8000 180#define PG_SIZE_4K 0x00000000 181#define PG_SIZE_16K 0x00006000 182#define PG_SIZE_64K 0x0001e000 183#define PG_SIZE_256K 0x0007e000 184#define PG_SIZE_1M 0x001fe000 185#define PG_SIZE_4M 0x007fe000 186#define PG_SIZE_16M 0x01ffe000 187#if PAGE_SHIFT == 12 188#define TLB_PAGE_MASK PG_SIZE_4K 189#elif PAGE_SHIFT == 14 190#define TLB_PAGE_MASK PG_SIZE_16K 191#endif 192#endif /* !R8000 */ 193