pte.h revision 1.19 
1/*	$OpenBSD: pte.h,v 1.19 2016/08/14 08:23:52 visa Exp $	*/
2
3/*
4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1992, 1993
6 *	The Regents of the University of California.  All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department and Ralph Campbell.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 *    notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 *    notice, this list of conditions and the following disclaimer in the
19 *    documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 *    may be used to endorse or promote products derived from this software
22 *    without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 *	from: Utah Hdr: pte.h 1.11 89/09/03
37 *	from: @(#)pte.h	8.1 (Berkeley) 6/10/93
38 */
39
40/*
41 * R4000 and R8000 hardware page table entries
42 */
43
44#ifndef _LOCORE
45
46/*
47 * Structure defining a TLB entry data set.
48 */
49struct tlb_entry {
50	u_int64_t	tlb_mask;
51	u_int64_t	tlb_hi;
52	u_int64_t	tlb_lo0;
53	u_int64_t	tlb_lo1;
54};
55
56u_int	tlb_get_pid(void);
57void	tlb_read(unsigned int, struct tlb_entry *);
58
59#ifdef MIPS_PTE64
60typedef u_int64_t pt_entry_t;
61#else
62typedef u_int32_t pt_entry_t;
63#endif
64
65#endif /* _LOCORE */
66
67#ifdef MIPS_PTE64
68#define	PTE_BITS	64
69#else
70#define	PTE_BITS	32
71#endif
72
73#ifdef CPU_MIPS64R2
74#define	PTE_CLEAR_SWBITS(reg)						\
75	.set	push;							\
76	.set	mips64r2;						\
77	/* Clear SW bits around PG_XI. */				\
78	dins	reg, zero, (PTE_BITS - 1), 1;				\
79	dins	reg, zero, PG_FRAMEBITS, (PTE_BITS - 2 - PG_FRAMEBITS);	\
80	.set	pop
81#else
82#define	PTE_CLEAR_SWBITS(reg)						\
83	/* Clear SW bits left of PG_FRAMEBITS. */			\
84	dsll	reg, reg, (64 - PG_FRAMEBITS);				\
85	dsrl	reg, reg, (64 - PG_FRAMEBITS)
86#endif
87
88/* entryhi values */
89
90#ifndef CPU_R8000
91#define	PG_HVPN		(-2 * PAGE_SIZE)	/* Hardware page number mask */
92#define	PG_ODDPG	PAGE_SIZE
93#endif	/* !R8000 */
94
95/* Address space ID */
96#ifdef CPU_R8000
97#define	PG_ASID_MASK		0x0000000000000ff0
98#define	PG_ASID_SHIFT		4
99#define	ICACHE_ASID_SHIFT	40
100#define	MIN_USER_ASID		0
101#else
102#define	PG_ASID_MASK		0x00000000000000ff
103#define	PG_ASID_SHIFT		0
104#define	MIN_USER_ASID		1
105#endif
106#define	PG_ASID_COUNT		256	/* Number of available ASID */
107
108/* entrylo values */
109
110#ifdef CPU_R8000
111#define	PG_FRAME	0xfffff000
112#define	PG_SHIFT	0
113#else
114#ifdef MIPS_PTE64
115#define	PG_FRAMEBITS	61
116#else
117#define	PG_FRAMEBITS	29
118#endif
119#define	PG_FRAME	((1ULL << PG_FRAMEBITS) - (1ULL << PG_SHIFT))
120#define	PG_SHIFT	6
121#endif
122
123/* software pte bits - not put in entrylo */
124#if defined(CPU_R8000)
125#define	PG_WIRED	0x00000010
126#define	PG_RO		0x00000020
127#elif defined(CPU_R4000)
128#define	PG_WIRED	(1ULL << (PG_FRAMEBITS + 2))
129#define	PG_RO		(1ULL << (PG_FRAMEBITS + 1))
130#define	PG_SP		(1ULL << (PG_FRAMEBITS + 0))	/* ``special'' bit */
131#else
132#define	PG_WIRED	(1ULL << (PG_FRAMEBITS + 2))
133			/* 1ULL << (PG_FRAMEBITS + 1) is PG_XI. */
134#define	PG_RO		(1ULL << (PG_FRAMEBITS + 0))
135#endif
136
137#ifdef CPU_MIPS64R2
138#define	PG_XI		(1ULL << (PTE_BITS - 2))
139#else
140#define	PG_XI		0x00000000
141#endif
142
143#define	PG_NV		0x00000000
144#ifdef CPU_R8000
145#define	PG_G		0x00000000	/* no such concept for R8000 */
146#define	PG_V		0x00000080
147#define	PG_M		0x00000100
148#define	PG_CCA_SHIFT	9
149#else
150#define	PG_G		0x00000001
151#define	PG_V		0x00000002
152#define	PG_M		0x00000004
153#define	PG_CCA_SHIFT	3
154#endif
155#define	PG_NV		0x00000000
156
157#define	PG_UNCACHED	(CCA_NC << PG_CCA_SHIFT)
158#define	PG_CACHED_NC	(CCA_NONCOHERENT << PG_CCA_SHIFT)
159#define	PG_CACHED_CE	(CCA_COHERENT_EXCL << PG_CCA_SHIFT)
160#define	PG_CACHED_CEW	(CCA_COHERENT_EXCLWRITE << PG_CCA_SHIFT)
161#define	PG_CACHED	(CCA_CACHED << PG_CCA_SHIFT)
162#define	PG_CACHEMODE	(7 << PG_CCA_SHIFT)
163
164#define	PG_ATTR		(PG_CACHEMODE | PG_M | PG_V | PG_G)
165#define	PG_ROPAGE	(PG_V | PG_RO | PG_CACHED) /* Write protected */
166#define	PG_RWPAGE	(PG_V | PG_M | PG_CACHED)  /* Not w-prot not clean */
167#define	PG_CWPAGE	(PG_V | PG_CACHED)	   /* Not w-prot but clean */
168#define	PG_IOPAGE	(PG_G | PG_V | PG_M | PG_UNCACHED)
169
170#define	pfn_to_pad(pa)	((((paddr_t)pa) & PG_FRAME) << PG_SHIFT)
171#define	vad_to_pfn(va)	(((va) >> PG_SHIFT) & PG_FRAME)
172
173#ifndef CPU_R8000
174#define	PG_SIZE_4K	0x00000000
175#define	PG_SIZE_16K	0x00006000
176#define	PG_SIZE_64K	0x0001e000
177#define	PG_SIZE_256K	0x0007e000
178#define	PG_SIZE_1M	0x001fe000
179#define	PG_SIZE_4M	0x007fe000
180#define	PG_SIZE_16M	0x01ffe000
181#if PAGE_SHIFT == 12
182#define	TLB_PAGE_MASK	PG_SIZE_4K
183#elif PAGE_SHIFT == 14
184#define	TLB_PAGE_MASK	PG_SIZE_16K
185#endif
186#endif	/* !R8000 */
187