pte.h revision 1.17
1/* $OpenBSD: pte.h,v 1.17 2014/02/08 09:34:04 miod Exp $ */ 2 3/* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department and Ralph Campbell. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: Utah Hdr: pte.h 1.11 89/09/03 37 * from: @(#)pte.h 8.1 (Berkeley) 6/10/93 38 */ 39 40/* 41 * R4000 and R8000 hardware page table entries 42 */ 43 44#ifndef _LOCORE 45 46/* 47 * Structure defining a TLB entry data set. 48 */ 49struct tlb_entry { 50 u_int64_t tlb_mask; 51 u_int64_t tlb_hi; 52 u_int64_t tlb_lo0; 53 u_int64_t tlb_lo1; 54}; 55 56u_int tlb_get_pid(void); 57void tlb_read(unsigned int, struct tlb_entry *); 58 59#ifdef MIPS_PTE64 60typedef u_int64_t pt_entry_t; 61#else 62typedef u_int32_t pt_entry_t; 63#endif 64 65#endif /* _LOCORE */ 66 67/* entryhi values */ 68#ifndef CPU_R8000 69#define PG_HVPN (-2 * PAGE_SIZE) /* Hardware page number mask */ 70#define PG_ODDPG PAGE_SIZE 71#endif /* !R8000 */ 72 73/* Address space ID */ 74#ifdef CPU_R8000 75#define PG_ASID_MASK 0x0000000000000ff0 76#define PG_ASID_SHIFT 4 77#define ICACHE_ASID_SHIFT 40 78#define MIN_USER_ASID 0 79#else 80#define PG_ASID_MASK 0x00000000000000ff 81#define PG_ASID_SHIFT 0 82#define MIN_USER_ASID 1 83#endif 84#define PG_ASID_COUNT 256 /* Number of available ASID */ 85 86/* entrylo values */ 87#ifdef CPU_R8000 88#define PG_WIRED 0x00000010 /* SW */ 89#define PG_RO 0x00000020 /* SW */ 90#define PG_G 0x00000000 /* no such concept for R8000 */ 91#define PG_V 0x00000080 92#define PG_M 0x00000100 93#define PG_CCA_SHIFT 9 94#else 95#ifdef MIPS_PTE64 96#define PG_WIRED 0x8000000000000000ULL /* SW */ 97#define PG_RO 0x4000000000000000ULL /* SW */ 98#else 99#define PG_WIRED 0x80000000 /* SW */ 100#define PG_RO 0x40000000 /* SW */ 101#endif 102#define PG_G 0x00000001 /* HW */ 103#define PG_V 0x00000002 104#define PG_M 0x00000004 105#define PG_CCA_SHIFT 3 106#endif 107#define PG_NV 0x00000000 108 109#define PG_UNCACHED (CCA_NC << PG_CCA_SHIFT) 110#define PG_CACHED_NC (CCA_NONCOHERENT << PG_CCA_SHIFT) 111#define PG_CACHED_CE (CCA_COHERENT_EXCL << PG_CCA_SHIFT) 112#define PG_CACHED_CEW (CCA_COHERENT_EXCLWRITE << PG_CCA_SHIFT) 113#define PG_CACHED (CCA_CACHED << PG_CCA_SHIFT) 114#define PG_CACHEMODE (7 << PG_CCA_SHIFT) 115 116#define PG_ATTR (PG_CACHEMODE | PG_M | PG_V | PG_G) 117#define PG_ROPAGE (PG_V | PG_RO | PG_CACHED) /* Write protected */ 118#define PG_RWPAGE (PG_V | PG_M | PG_CACHED) /* Not w-prot not clean */ 119#define PG_CWPAGE (PG_V | PG_CACHED) /* Not w-prot but clean */ 120#define PG_IOPAGE (PG_G | PG_V | PG_M | PG_UNCACHED) 121 122#ifdef CPU_R8000 123#define PG_FRAME 0xfffff000 124#define PG_SHIFT 0 125#else 126#ifdef MIPS_PTE64 127#define PG_FRAME 0x3fffffffffffffc0ULL 128#define PG_FRAMEBITS 62 129#else 130#define PG_FRAME 0x3fffffc0 131#define PG_FRAMEBITS 30 132#endif 133#define PG_SHIFT 6 134#endif 135 136#define pfn_to_pad(pa) ((((paddr_t)pa) & PG_FRAME) << PG_SHIFT) 137#define vad_to_pfn(va) (((va) >> PG_SHIFT) & PG_FRAME) 138 139#ifndef CPU_R8000 140#define PG_SIZE_4K 0x00000000 141#define PG_SIZE_16K 0x00006000 142#define PG_SIZE_64K 0x0001e000 143#define PG_SIZE_256K 0x0007e000 144#define PG_SIZE_1M 0x001fe000 145#define PG_SIZE_4M 0x007fe000 146#define PG_SIZE_16M 0x01ffe000 147#if PAGE_SHIFT == 12 148#define TLB_PAGE_MASK PG_SIZE_4K 149#elif PAGE_SHIFT == 14 150#define TLB_PAGE_MASK PG_SIZE_16K 151#endif 152#endif /* !R8000 */ 153