pte.h revision 1.12
1/* $OpenBSD: pte.h,v 1.12 2012/04/24 20:00:59 miod Exp $ */ 2 3/* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department and Ralph Campbell. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: Utah Hdr: pte.h 1.11 89/09/03 37 * from: @(#)pte.h 8.1 (Berkeley) 6/10/93 38 */ 39 40/* 41 * R4000 hardware page table entry 42 */ 43 44#ifndef _LOCORE 45 46/* 47 * Structure defining an tlb entry data set. 48 */ 49 50struct tlb_entry { 51 u_int64_t tlb_mask; 52 u_int64_t tlb_hi; 53 u_int64_t tlb_lo0; 54 u_int64_t tlb_lo1; 55}; 56 57typedef u_int32_t pt_entry_t; /* Mips page table entry */ 58#define NPTEPG (PMAP_L2SIZE / sizeof(pt_entry_t)) 59 60#endif /* _LOCORE */ 61 62/* entryhi values */ 63#if PAGE_SHIFT == 12 64#define PG_SVPN 0xfffffffffffff000 /* Software page no mask */ 65#define PG_HVPN 0xffffffffffffe000 /* Hardware page no mask */ 66#define PG_ODDPG 0x0000000000001000 /* Odd even pte entry */ 67#elif PAGE_SHIFT == 14 68#define PG_SVPN 0xffffffffffffc000 /* Software page no mask */ 69#define PG_HVPN 0xffffffffffff8000 /* Hardware page no mask */ 70#define PG_ODDPG 0x0000000000004000 /* Odd even pte entry */ 71#endif 72#define PG_ASID 0x00000000000000ff /* Address space ID */ 73/* entrylo values */ 74#define PG_RO 0x40000000 /* SW */ 75#define PG_G 0x00000001 /* HW */ 76#define PG_V 0x00000002 77#define PG_NV 0x00000000 78#define PG_M 0x00000004 79#define PG_UNCACHED (CCA_NC << 3) 80#define PG_CACHED_NC (CCA_NONCOHERENT << 3) 81#define PG_CACHED_CE (CCA_COHERENT_EXCL << 3) 82#define PG_CACHED_CEW (CCA_COHERENT_EXCLWRITE << 3) 83#define PG_CACHED (CCA_CACHED << 3) 84#define PG_CACHEMODE 0x00000038 85#define PG_ATTR 0x0000003f 86#define PG_ROPAGE (PG_V | PG_RO | PG_CACHED) /* Write protected */ 87#define PG_RWPAGE (PG_V | PG_M | PG_CACHED) /* Not w-prot not clean */ 88#define PG_CWPAGE (PG_V | PG_CACHED) /* Not w-prot but clean */ 89#define PG_IOPAGE (PG_G | PG_V | PG_M | PG_UNCACHED) 90#define PG_FRAME 0x3fffffc0 91#define PG_FRAMEBITS 30 92#define PG_SHIFT 6 93 94#define pfn_to_pad(pa) ((((paddr_t)pa) & PG_FRAME) << PG_SHIFT) 95#define vad_to_pfn(va) (((va) >> PG_SHIFT) & PG_FRAME) 96 97#define PG_SIZE_4K 0x00000000 98#define PG_SIZE_16K 0x00006000 99#define PG_SIZE_64K 0x0001e000 100#define PG_SIZE_256K 0x0007e000 101#define PG_SIZE_1M 0x001fe000 102#define PG_SIZE_4M 0x007fe000 103#define PG_SIZE_16M 0x01ffe000 104 105#if PAGE_SHIFT == 12 106#define TLB_PAGE_MASK PG_SIZE_4K 107#elif PAGE_SHIFT == 14 108#define TLB_PAGE_MASK PG_SIZE_16K 109#endif 110 111#if defined(_KERNEL) && !defined(_LOCORE) 112 113/* Kernel virtual address to page table entry */ 114#define kvtopte(va) \ 115 (Sysmap + (((vaddr_t)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT)) 116/* User virtual address to pte page entry */ 117#define uvtopte(adr) (((adr) >> PGSHIFT) & (NPTEPG -1)) 118 119extern pt_entry_t *Sysmap; /* kernel pte table */ 120extern u_int Sysmapsize; /* number of pte's in Sysmap */ 121#endif 122