loongson3.h revision 1.1 
1/*	$OpenBSD: loongson3.h,v 1.1 2016/11/06 10:20:33 visa Exp $	*/
2
3/*
4 * Copyright (c) 2016 Visa Hankala
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19#ifndef _MIPS64_LOONGSON3_H_
20#define _MIPS64_LOONGSON3_H_
21
22/*
23 * Definitions for Loongson 3A.
24 */
25
26#define LS3_CFG_BASE(node)		(0x100000004000ull*(node) + 0x3ff00000)
27#define LS3_MEM_BASE(node)		(0x100000000000ull*(node))
28
29#define LS3_IPI_ISR_OFFSET(core)	(0x100 * (core))
30#define LS3_IPI_IMR_OFFSET(core)	(0x100 * (core) + 0x04)
31#define LS3_IPI_SET_OFFSET(core)	(0x100 * (core) + 0x08)
32#define LS3_IPI_CLEAR_OFFSET(core)	(0x100 * (core) + 0x0c)
33#define LS3_IPI_MBOX0_OFFSET(core)	(0x100 * (core) + 0x20)
34#define LS3_IPI_MBOX1_OFFSET(core)	(0x100 * (core) + 0x28)
35#define LS3_IPI_MBOX2_OFFSET(core)	(0x100 * (core) + 0x30)
36#define LS3_IPI_MBOX3_OFFSET(core)	(0x100 * (core) + 0x38)
37
38static inline uint32_t
39loongson3_get_cpuid(void)
40{
41	uint32_t tmp;
42
43	asm volatile (
44	"	.set push\n"
45	"	.set mips64\n"
46	"	mfc0 %0, $15, 1\n"	/* EBase */
47	"	.set pop\n"
48	: "=r" (tmp));
49
50	return tmp & 0xf;
51}
52
53#define LS3_COREID(cpuid) ((cpuid) & 3)
54#define LS3_NODEID(cpuid) ((cpuid) >> 2)
55
56/*
57 * Interrupt router registers
58 */
59
60#define LS3_IRT_ENTRY(node, irq)	(LS3_CFG_BASE(node) + 0x1400 + (irq))
61#define LS3_IRT_INTISR(node)		(LS3_CFG_BASE(node) + 0x1420)
62#define LS3_IRT_INTEN(node)		(LS3_CFG_BASE(node) + 0x1424)
63#define LS3_IRT_INTENSET(node)		(LS3_CFG_BASE(node) + 0x1428)
64#define LS3_IRT_INTENCLR(node)		(LS3_CFG_BASE(node) + 0x142c)
65#define LS3_IRT_INTISR_CORE(node, cpu)	(LS3_CFG_BASE(node) + 0x1440 + (cpu)*8)
66
67/* sys int 0-3 */
68#define LS3_IRT_ENTRY_INT(node, x)	LS3_IRT_ENTRY((node), (x))
69/* PCI int 0-3 */
70#define LS3_IRT_ENTRY_PCI(node, x)	LS3_IRT_ENTRY((node), 0x04+(x))
71/* LPC int */
72#define LS3_IRT_ENTRY_LPC(node)		LS3_IRT_ENTRY((node), 0x0a)
73/* HT0 int 0-7 */
74#define LS3_IRT_ENTRY_HT0(node, x)	LS3_IRT_ENTRY((node), 0x10+(x))
75/* HT1 int 0-7 */
76#define LS3_IRT_ENTRY_HT1(node, x)	LS3_IRT_ENTRY((node), 0x18+(x))
77
78#define LS3_IRT_ROUTE(core, intr)	((0x01 << (core)) | (0x10 << (intr)))
79
80#define LS3_IRQ_INT(x)			(x)		/* sys int 0-3 */
81#define LS3_IRQ_PCI(x)			((x) + 0x04)	/* PCI int 0-3 */
82#define LS3_IRQ_LPC			0x0a		/* LPC int */
83#define LS3_IRQ_HT0(x)			((x) + 0x10)	/* HT0 int 0-7 */
84#define LS3_IRQ_HT1(x)			((x) + 0x18)	/* HT1 int 0-7 */
85#define LS3_IRQ_NUM			32
86
87#define LS3_IRQ_IS_HT(irq)		((irq) >= 0x10)
88
89#define LS3_IRQ_HT_MASK			0xffff0000u
90
91/*
92 * Number of HyperTransport interrupt vectors. In reality, each HT interface
93 * has 256 vectors, but the interrupt code uses only a subset of them.
94 */
95#define LS3_HT_IRQ_NUM			32
96
97/*
98 * HyperTransport registers
99 */
100
101#define LS3_HT1_CFG_BASE(n)		(LS3_MEM_BASE(n)+0x00000efdfb000000ull)
102
103#define LS3_HT_ISR_OFFSET(x)		(0x80 + (x) * 4)
104#define LS3_HT_IMR_OFFSET(x)		(0xa0 + (x) * 4)
105
106#endif	/* _MIPS64_LOONGSON3_H_ */
107