cpu.h revision 1.90
1/* $OpenBSD: cpu.h,v 1.90 2012/10/03 11:18:23 miod Exp $ */ 2 3/*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * Copyright (C) 1989 Digital Equipment Corporation. 35 * Permission to use, copy, modify, and distribute this software and 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 */ 44 45#ifndef _MIPS64_CPU_H_ 46#define _MIPS64_CPU_H_ 47 48#ifndef _LOCORE 49 50/* 51 * MIPS32-style segment definitions. 52 * They only cover the first 512MB of physical addresses. 53 */ 54#define CKSEG0_BASE 0xffffffff80000000UL 55#define CKSEG1_BASE 0xffffffffa0000000UL 56#define CKSSEG_BASE 0xffffffffc0000000UL 57#define CKSEG3_BASE 0xffffffffe0000000UL 58#define CKSEG_SIZE 0x0000000020000000UL 59 60#define CKSEG0_TO_PHYS(x) ((u_long)(x) & (CKSEG_SIZE - 1)) 61#define CKSEG1_TO_PHYS(x) ((u_long)(x) & (CKSEG_SIZE - 1)) 62#define PHYS_TO_CKSEG0(x) ((u_long)(x) | CKSEG0_BASE) 63#define PHYS_TO_CKSEG1(x) ((u_long)(x) | CKSEG1_BASE) 64 65/* 66 * MIPS64-style segment definitions. 67 * These allow for 36 bits of addressable physical memory, thus 64GB. 68 */ 69 70/* 71 * Cache Coherency Attributes. 72 */ 73/* r8k only */ 74#define CCA_NC_COPROCESSOR 0UL /* uncached, coprocessor ordered */ 75/* common to r4, r5k, r8k and r1xk */ 76#define CCA_NC 2UL /* uncached, write-around */ 77#define CCA_NONCOHERENT 3UL /* cached, non-coherent, write-back */ 78/* r8k, r1xk only */ 79#define CCA_COHERENT_EXCL 4UL /* cached, coherent, exclusive */ 80#define CCA_COHERENT_EXCLWRITE 5UL /* cached, coherent, exclusive write */ 81/* r4k only */ 82#define CCA_COHERENT_UPDWRITE 6UL /* cached, coherent, update on write */ 83/* r1xk only */ 84#define CCA_NC_ACCELERATED 7UL /* uncached accelerated */ 85 86#ifdef TGT_COHERENT 87#define CCA_CACHED CCA_COHERENT_EXCLWRITE 88#else 89#define CCA_CACHED CCA_NONCOHERENT 90#endif 91 92/* 93 * Uncached spaces. 94 * R1x000 processors use bits 58:57 of uncached virtual addresses (CCA_NC) 95 * to select different spaces. Unfortunately, other processors need these 96 * bits to be zero, so uncached address have to be decided at runtime. 97 */ 98#define SP_HUB 0UL /* Hub space */ 99#define SP_IO 1UL /* I/O space */ 100#define SP_SPECIAL 2UL /* Memory Special space */ 101#define SP_NC 3UL /* Memory Uncached space */ 102 103#define XKSSSEG_BASE 0x4000000000000000UL 104#define XKPHYS_BASE 0x8000000000000000UL 105#define XKSSEG_BASE 0xc000000000000000UL 106 107#define XKPHYS_TO_PHYS(x) ((paddr_t)(x) & 0x0000000fffffffffUL) 108#define PHYS_TO_XKPHYS(x,c) ((paddr_t)(x) | XKPHYS_BASE | ((c) << 59)) 109#define PHYS_TO_XKPHYS_UNCACHED(x,s) \ 110 (PHYS_TO_XKPHYS(x, CCA_NC) | ((s) << 57)) 111#define IS_XKPHYS(va) (((va) >> 62) == 2) 112#define XKPHYS_TO_CCA(x) (((x) >> 59) & 0x07) 113#define XKPHYS_TO_SP(x) (((x) >> 57) & 0x03) 114 115#endif /* _LOCORE */ 116 117/* 118 * Exported definitions unique to mips cpu support. 119 */ 120 121#if defined(_KERNEL) && !defined(_LOCORE) 122 123#include <sys/device.h> 124#include <sys/lock.h> 125#include <machine/intr.h> 126#include <sys/sched.h> 127 128struct cpu_hwinfo { 129 uint32_t c0prid; 130 uint32_t c1prid; 131 uint32_t clock; /* Hz */ 132 uint32_t tlbsize; 133 uint type; 134 uint32_t l2size; 135}; 136 137struct cpu_info { 138 struct device *ci_dev; /* our device */ 139 struct cpu_info *ci_self; /* pointer to this structure */ 140 struct cpu_info *ci_next; /* next cpu */ 141 struct proc *ci_curproc; 142 struct user *ci_curprocpaddr; 143 struct proc *ci_fpuproc; /* pointer to last proc to use FP */ 144 uint32_t ci_delayconst; 145 struct cpu_hwinfo 146 ci_hw; 147 148 /* cache information */ 149 uint ci_cacheconfiguration; 150 uint ci_cacheways; 151 uint ci_l1instcachesize; 152 uint ci_l1instcacheline; 153 uint ci_l1instcacheset; 154 uint ci_l1datacachesize; 155 uint ci_l1datacacheline; 156 uint ci_l1datacacheset; 157 uint ci_l2size; 158 uint ci_l2line; 159 uint ci_l3size; 160 161 /* function pointers for the cache handling routines */ 162 void (*ci_SyncCache)(struct cpu_info *); 163 void (*ci_InvalidateICache)(struct cpu_info *, vaddr_t, 164 size_t); 165 void (*ci_SyncDCachePage)(struct cpu_info *, vaddr_t, 166 paddr_t); 167 void (*ci_HitSyncDCache)(struct cpu_info *, vaddr_t, size_t); 168 void (*ci_HitInvalidateDCache)(struct cpu_info *, vaddr_t, 169 size_t); 170 void (*ci_IOSyncDCache)(struct cpu_info *, vaddr_t, size_t, 171 int); 172 173 struct schedstate_percpu 174 ci_schedstate; 175 int ci_want_resched; /* need_resched() invoked */ 176 cpuid_t ci_cpuid; /* our CPU ID */ 177 uint32_t ci_randseed; /* per cpu random seed */ 178 int ci_ipl; /* software IPL */ 179 uint32_t ci_softpending; /* pending soft interrupts */ 180 int ci_clock_started; 181 u_int32_t ci_cpu_counter_last; /* last compare value loaded */ 182 u_int32_t ci_cpu_counter_interval; /* # of counter ticks/tick */ 183 184 u_int32_t ci_pendingticks; 185 struct pmap *ci_curpmap; 186 uint ci_intrdepth; /* interrupt depth */ 187#ifdef MULTIPROCESSOR 188 u_long ci_flags; /* flags; see below */ 189 struct intrhand ci_ipiih; 190#endif 191 volatile int ci_ddb; 192#define CI_DDB_RUNNING 0 193#define CI_DDB_SHOULDSTOP 1 194#define CI_DDB_STOPPED 2 195#define CI_DDB_ENTERDDB 3 196#define CI_DDB_INDDB 4 197 198#ifdef DIAGNOSTIC 199 int ci_mutex_level; 200#endif 201}; 202 203#define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 204#define CPUF_PRESENT 0x02 /* CPU is present */ 205#define CPUF_RUNNING 0x04 /* CPU is running */ 206 207extern struct cpu_info cpu_info_primary; 208extern struct cpu_info *cpu_info_list; 209#define CPU_INFO_ITERATOR int 210#define CPU_INFO_FOREACH(cii, ci) for (cii = 0, ci = cpu_info_list; \ 211 ci != NULL; ci = ci->ci_next) 212 213#define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0) 214 215#ifdef MULTIPROCESSOR 216#define MAXCPUS 4 217#define getcurcpu() hw_getcurcpu() 218#define setcurcpu(ci) hw_setcurcpu(ci) 219extern struct cpu_info *get_cpu_info(int); 220#define curcpu() getcurcpu() 221#define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 222#define cpu_number() (curcpu()->ci_cpuid) 223 224extern struct cpuset cpus_running; 225void cpu_unidle(struct cpu_info *); 226void cpu_boot_secondary_processors(void); 227#define cpu_boot_secondary(ci) hw_cpu_boot_secondary(ci) 228#define cpu_hatch(ci) hw_cpu_hatch(ci) 229 230vaddr_t alloc_contiguous_pages(size_t); 231 232#define MIPS64_IPI_NOP 0x00000001 233#define MIPS64_IPI_RENDEZVOUS 0x00000002 234#define MIPS64_IPI_DDB 0x00000004 235#define MIPS64_NIPIS 3 /* must not exceed 32 */ 236 237void mips64_ipi_init(void); 238void mips64_send_ipi(unsigned int, unsigned int); 239void smp_rendezvous_cpus(unsigned long, void (*)(void *), void *arg); 240 241#include <sys/mplock.h> 242#else 243#define MAXCPUS 1 244#define curcpu() (&cpu_info_primary) 245#define CPU_IS_PRIMARY(ci) 1 246#define cpu_number() 0 247#define cpu_unidle(ci) 248#define get_cpu_info(i) (&cpu_info_primary) 249#endif 250 251extern void (*md_startclock)(struct cpu_info *); 252void cp0_calibrate(struct cpu_info *); 253 254#include <machine/frame.h> 255 256/* 257 * Arguments to hardclock encapsulate the previous machine state in 258 * an opaque clockframe. 259 */ 260#define clockframe trap_frame /* Use normal trap frame */ 261 262#define SR_KSU_USER 0x00000010 263#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 264#define CLKF_PC(framep) ((framep)->pc) 265#define CLKF_INTR(framep) (curcpu()->ci_intrdepth > 1) /* XXX */ 266 267/* 268 * This is used during profiling to integrate system time. 269 */ 270#define PROC_PC(p) ((p)->p_md.md_regs->pc) 271 272/* 273 * Preempt the current process if in interrupt from user mode, 274 * or after the current trap/syscall if in system mode. 275 */ 276#define need_resched(ci) \ 277 do { \ 278 (ci)->ci_want_resched = 1; \ 279 if ((ci)->ci_curproc != NULL) \ 280 aston((ci)->ci_curproc); \ 281 } while(0) 282#define clear_resched(ci) (ci)->ci_want_resched = 0 283 284/* 285 * Give a profiling tick to the current process when the user profiling 286 * buffer pages are invalid. On the PICA, request an ast to send us 287 * through trap, marking the proc as needing a profiling tick. 288 */ 289#define need_proftick(p) aston(p) 290 291/* 292 * Notify the current process (p) that it has a signal pending, 293 * process as soon as possible. 294 */ 295#ifdef MULTIPROCESSOR 296#define signotify(p) (aston(p), cpu_unidle(p->p_cpu)) 297#else 298#define signotify(p) aston(p) 299#endif 300 301#define aston(p) p->p_md.md_astpending = 1 302 303#ifdef CPU_R8000 304#define mips_sync() __asm__ __volatile__ ("lw $0, 0(%0)" :: \ 305 "r" (PHYS_TO_XKPHYS(0, CCA_NC)) : "memory") 306#else 307#define mips_sync() __asm__ __volatile__ ("sync" ::: "memory") 308#endif 309 310#endif /* _KERNEL && !_LOCORE */ 311 312#ifdef _KERNEL 313/* 314 * Values for the code field in a break instruction. 315 */ 316#define BREAK_INSTR 0x0000000d 317#define BREAK_VAL_MASK 0x03ff0000 318#define BREAK_VAL_SHIFT 16 319#define BREAK_KDB_VAL 512 320#define BREAK_SSTEP_VAL 513 321#define BREAK_BRKPT_VAL 514 322#define BREAK_SOVER_VAL 515 323#define BREAK_DDB_VAL 516 324#define BREAK_FPUEMUL_VAL 517 325#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 326#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 327#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 328#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 329#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) 330#define BREAK_FPUEMUL (BREAK_INSTR | (BREAK_FPUEMUL_VAL << BREAK_VAL_SHIFT)) 331 332#endif /* _KERNEL */ 333 334/* 335 * CTL_MACHDEP definitions. 336 */ 337#define CPU_ALLOWAPERTURE 1 /* allow mmap of /dev/xf86 */ 338 /* 2 formerly: keyboard reset */ 339#define CPU_MAXID 3 /* number of valid machdep ids */ 340 341#define CTL_MACHDEP_NAMES { \ 342 { 0, 0 }, \ 343 { "allowaperture", CTLTYPE_INT }, \ 344 { 0, 0 }, \ 345} 346 347/* 348 * MIPS CPU types (cp_imp). 349 */ 350#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 351#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 352#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 353#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 354#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 355#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 356#define MIPS_OCTEON 0x06 /* Cavium OCTEON MIPS64R2*/ 357#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 358#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 359#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 360#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 361#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ 362#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 363#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 364#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 365#define MIPS_R4600 0x20 /* PMCS R4600 Orion ISA III */ 366#define MIPS_R4700 0x21 /* PMCS R4700 Orion ISA III */ 367#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 368#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 369#define MIPS_RM7000 0x27 /* PMCS RM7000 CPU ISA IV */ 370#define MIPS_RM52X0 0x28 /* PMCS RM52X0 CPU ISA IV */ 371#define MIPS_RM9000 0x34 /* PMCS RM9000 CPU ISA IV */ 372#define MIPS_LOONGSON 0x42 /* STC LoongSon CPU ISA III */ 373#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ 374#define MIPS_LOONGSON2 0x63 /* STC LoongSon2/3 CPU ISA III+ */ 375 376/* 377 * MIPS FPU types. Only soft, rest is the same as cpu type. 378 */ 379#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 380 381 382#if defined(_KERNEL) && !defined(_LOCORE) 383 384extern register_t protosr; 385 386struct exec_package; 387struct user; 388 389void tlb_asid_wrap(struct cpu_info *); 390void tlb_flush(int); 391void tlb_flush_addr(vaddr_t); 392void tlb_init(unsigned int); 393void tlb_set_gbase(vaddr_t, vsize_t); 394void tlb_set_page_mask(uint32_t); 395void tlb_set_pid(u_int); 396void tlb_set_wired(uint32_t); 397int tlb_update(vaddr_t, register_t); 398 399void build_trampoline(vaddr_t, vaddr_t); 400void cpu_switchto_asm(struct proc *, struct proc *); 401int exec_md_map(struct proc *, struct exec_package *); 402void savectx(struct user *, int); 403 404void enable_fpu(struct proc *); 405void save_fpu(void); 406int fpe_branch_emulate(struct proc *, struct trap_frame *, uint32_t, 407 vaddr_t); 408void MipsSaveCurFPState(struct proc *); 409void MipsSaveCurFPState16(struct proc *); 410void MipsSwitchFPState(struct proc *, struct trap_frame *); 411void MipsSwitchFPState16(struct proc *, struct trap_frame *); 412 413int guarded_read_1(paddr_t, uint8_t *); 414int guarded_read_2(paddr_t, uint16_t *); 415int guarded_read_4(paddr_t, uint32_t *); 416int guarded_write_4(paddr_t, uint32_t); 417 418void MipsFPTrap(struct trap_frame *); 419register_t MipsEmulateBranch(struct trap_frame *, vaddr_t, uint32_t, uint32_t); 420 421/* 422 * Low level access routines to CPU registers 423 */ 424 425void setsoftintr0(void); 426void clearsoftintr0(void); 427void setsoftintr1(void); 428void clearsoftintr1(void); 429register_t enableintr(void); 430register_t disableintr(void); 431register_t getsr(void); 432register_t setsr(register_t); 433 434u_int cp0_get_count(void); 435register_t cp0_get_config(void); 436uint32_t cp0_get_config_1(void); 437uint32_t cp0_get_config_2(void); 438uint32_t cp0_get_config_3(void); 439register_t cp0_get_prid(void); 440void cp0_reset_cause(register_t); 441void cp0_set_compare(u_int); 442void cp0_set_config(register_t); 443void cp0_set_trapbase(register_t); 444u_int cp1_get_prid(void); 445 446/* 447 * Cache routines (may be overriden) 448 */ 449 450#ifndef Mips_SyncCache 451#define Mips_SyncCache(ci) \ 452 ((ci)->ci_SyncCache)(ci) 453#endif 454#ifndef Mips_InvalidateICache 455#define Mips_InvalidateICache(ci, va, l) \ 456 ((ci)->ci_InvalidateICache)(ci, va, l) 457#endif 458#ifndef Mips_SyncDCachePage 459#define Mips_SyncDCachePage(ci, va, pa) \ 460 ((ci)->ci_SyncDCachePage)(ci, va, pa) 461#endif 462#ifndef Mips_HitSyncDCache 463#define Mips_HitSyncDCache(ci, va, l) \ 464 ((ci)->ci_HitSyncDCache)(ci, va, l) 465#endif 466#ifndef Mips_HitInvalidateDCache 467#define Mips_HitInvalidateDCache(ci, va, l) \ 468 ((ci)->ci_HitInvalidateDCache)(ci, va, l) 469#endif 470#ifndef Mips_IOSyncDCache 471#define Mips_IOSyncDCache(ci, va, l, h) \ 472 ((ci)->ci_IOSyncDCache)(ci, va, l, h) 473#endif 474 475#endif /* _KERNEL && !_LOCORE */ 476#endif /* !_MIPS64_CPU_H_ */ 477