cpu.h revision 1.69
1/* $OpenBSD: cpu.h,v 1.69 2010/11/24 21:16:26 miod Exp $ */ 2 3/*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * Copyright (C) 1989 Digital Equipment Corporation. 35 * Permission to use, copy, modify, and distribute this software and 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 */ 44 45#ifndef _MIPS_CPU_H_ 46#define _MIPS_CPU_H_ 47 48#ifndef _LOCORE 49 50/* 51 * MIPS32-style segment definitions. 52 * They only cover the first 512MB of physical addresses. 53 */ 54#define CKSEG0_BASE 0xffffffff80000000UL 55#define CKSEG1_BASE 0xffffffffa0000000UL 56#define CKSSEG_BASE 0xffffffffc0000000UL 57#define CKSEG3_BASE 0xffffffffe0000000UL 58#define CKSEG_SIZE 0x0000000020000000UL 59 60#define CKSEG0_TO_PHYS(x) ((u_long)(x) & (CKSEG_SIZE - 1)) 61#define CKSEG1_TO_PHYS(x) ((u_long)(x) & (CKSEG_SIZE - 1)) 62#define PHYS_TO_CKSEG0(x) ((u_long)(x) | CKSEG0_BASE) 63#define PHYS_TO_CKSEG1(x) ((u_long)(x) | CKSEG1_BASE) 64 65/* 66 * MIPS64-style segment definitions. 67 * These allow for 36 bits of addressable physical memory, thus 64GB. 68 */ 69 70/* 71 * Cache Coherency Attributes. 72 */ 73/* r8k only */ 74#define CCA_NC_COPROCESSOR 0UL /* uncached, coprocessor ordered */ 75/* common to r4, r5k, r8k and r1xk */ 76#define CCA_NC 2UL /* uncached, write-around */ 77#define CCA_NONCOHERENT 3UL /* cached, non-coherent, write-back */ 78/* r8k, r1xk only */ 79#define CCA_COHERENT_EXCL 4UL /* cached, coherent, exclusive */ 80#define CCA_COHERENT_EXCLWRITE 5UL /* cached, coherent, exclusive write */ 81/* r1xk only */ 82#define CCA_NC_ACCELERATED 7UL /* uncached accelerated */ 83/* r4k only */ 84#define CCA_COHERENT_UPDWRITE 6UL /* cached, coherent, update on write */ 85 86#ifdef TGT_COHERENT 87#define CCA_CACHED CCA_COHERENT_EXCLWRITE 88#else 89#define CCA_CACHED CCA_NONCOHERENT 90#endif 91 92/* 93 * Uncached spaces. 94 * R1x000 processors use bits 58:57 of uncached virtual addresses (CCA_NC) 95 * to select different spaces. Unfortunately, other processors need these 96 * bits to be zero, so uncached address have to be decided at runtime. 97 */ 98#define SP_HUB 0UL /* Hub space */ 99#define SP_IO 1UL /* I/O space */ 100#define SP_SPECIAL 2UL /* Memory Special space */ 101#define SP_NC 3UL /* Memory Uncached space */ 102 103extern vaddr_t uncached_base; 104 105#define XKSSSEG_BASE 0x4000000000000000UL 106#define XKPHYS_BASE 0x8000000000000000UL 107#define XKSSEG_BASE 0xc000000000000000UL 108 109#define XKPHYS_TO_PHYS(x) ((paddr_t)(x) & 0x0000000fffffffffUL) 110#define PHYS_TO_XKPHYS(x,c) ((paddr_t)(x) | XKPHYS_BASE | ((c) << 59)) 111#define PHYS_TO_XKPHYS_UNCACHED(x,s) \ 112 (PHYS_TO_XKPHYS(x, CCA_NC) | ((s) << 57)) 113#define PHYS_TO_UNCACHED(x) ((paddr_t)(x) | uncached_base) 114#define IS_XKPHYS(va) (((va) >> 62) == 2) 115#define XKPHYS_TO_CCA(x) (((x) >> 59) & 0x07) 116#define XKPHYS_TO_SP(x) (((x) >> 57) & 0x03) 117 118#endif /* _LOCORE */ 119 120#if defined(_KERNEL) || defined(_STANDALONE) 121 122/* 123 * Status register. 124 */ 125#define SR_XX 0x80000000 126#define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */ 127#define SR_COP_0_BIT 0x10000000 128#define SR_COP_1_BIT 0x20000000 129#define SR_RP 0x08000000 130#define SR_FR_32 0x04000000 131#define SR_RE 0x02000000 132#define SR_DSD 0x01000000 /* Only on R12000 */ 133#define SR_BOOT_EXC_VEC 0x00400000 134#define SR_TLB_SHUTDOWN 0x00200000 135#define SR_SOFT_RESET 0x00100000 136#define SR_DIAG_CH 0x00040000 137#define SR_DIAG_CE 0x00020000 138#define SR_DIAG_DE 0x00010000 139#define SR_KX 0x00000080 140#define SR_SX 0x00000040 141#define SR_UX 0x00000020 142#define SR_KSU_MASK 0x00000018 143#define SR_KSU_USER 0x00000010 144#define SR_KSU_SUPER 0x00000008 145#define SR_KSU_KERNEL 0x00000000 146#define SR_ERL 0x00000004 147#define SR_EXL 0x00000002 148#define SR_INT_ENAB 0x00000001 149 150#define SR_INT_MASK 0x0000ff00 151#define SOFT_INT_MASK_0 0x00000100 152#define SOFT_INT_MASK_1 0x00000200 153#define SR_INT_MASK_0 0x00000400 154#define SR_INT_MASK_1 0x00000800 155#define SR_INT_MASK_2 0x00001000 156#define SR_INT_MASK_3 0x00002000 157#define SR_INT_MASK_4 0x00004000 158#define SR_INT_MASK_5 0x00008000 159/* 160 * Interrupt control register in RM7000. Expansion of interrupts. 161 */ 162#define IC_INT_MASK 0x00003f00 /* Two msb reserved */ 163#define IC_INT_MASK_6 0x00000100 164#define IC_INT_MASK_7 0x00000200 165#define IC_INT_MASK_8 0x00000400 166#define IC_INT_MASK_9 0x00000800 167#define IC_INT_TIMR 0x00001000 /* 12 Timer */ 168#define IC_INT_PERF 0x00002000 /* 13 Performance counter */ 169#define IC_INT_TE 0x00000080 /* Timer on INT11 */ 170 171#define ALL_INT_MASK ((IC_INT_MASK << 8) | SR_INT_MASK) 172#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 173#define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK) 174 175 176/* 177 * The bits in the cause register. 178 * 179 * CR_BR_DELAY Exception happened in branch delay slot. 180 * CR_COP_ERR Coprocessor error. 181 * CR_IP Interrupt pending bits defined below. 182 * CR_EXC_CODE The exception type (see exception codes below). 183 */ 184#define CR_BR_DELAY 0x80000000 185#define CR_COP_ERR 0x30000000 186#define CR_EXC_CODE 0x0000007c 187#define CR_EXC_CODE_SHIFT 2 188#define CR_IPEND 0x003fff00 189#define CR_INT_SOFT0 0x00000100 190#define CR_INT_SOFT1 0x00000200 191#define CR_INT_0 0x00000400 192#define CR_INT_1 0x00000800 193#define CR_INT_2 0x00001000 194#define CR_INT_3 0x00002000 195#define CR_INT_4 0x00004000 196#define CR_INT_5 0x00008000 197/* Following on RM7000 */ 198#define CR_INT_6 0x00010000 199#define CR_INT_7 0x00020000 200#define CR_INT_8 0x00040000 201#define CR_INT_9 0x00080000 202#define CR_INT_HARD 0x000ffc00 203#define CR_INT_TIMR 0x00100000 /* 12 Timer */ 204#define CR_INT_PERF 0x00200000 /* 13 Performance counter */ 205 206/* 207 * The bits in the context register. 208 */ 209#define CNTXT_PTE_BASE 0xff800000 210#define CNTXT_BAD_VPN2 0x007ffff0 211 212/* 213 * Location of exception vectors. 214 */ 215#define RESET_EXC_VEC (CKSEG1_BASE + 0x1fc00000) 216#define TLB_MISS_EXC_VEC (CKSEG0_BASE + 0x00000000) 217#define XTLB_MISS_EXC_VEC (CKSEG0_BASE + 0x00000080) 218#define CACHE_ERR_EXC_VEC (CKSEG0_BASE + 0x00000100) 219#define GEN_EXC_VEC (CKSEG0_BASE + 0x00000180) 220 221/* 222 * Coprocessor 0 registers: 223 */ 224#define COP_0_TLB_INDEX $0 225#define COP_0_TLB_RANDOM $1 226#define COP_0_TLB_LO0 $2 227#define COP_0_TLB_LO1 $3 228#define COP_0_TLB_CONTEXT $4 229#define COP_0_TLB_PG_MASK $5 230#define COP_0_TLB_WIRED $6 231#define COP_0_BAD_VADDR $8 232#define COP_0_COUNT $9 233#define COP_0_TLB_HI $10 234#define COP_0_COMPARE $11 235#define COP_0_STATUS_REG $12 236#define COP_0_CAUSE_REG $13 237#define COP_0_EXC_PC $14 238#define COP_0_PRID $15 239#define COP_0_CONFIG $16 240#define COP_0_LLADDR $17 241#define COP_0_WATCH_LO $18 242#define COP_0_WATCH_HI $19 243#define COP_0_TLB_XCONTEXT $20 244#define COP_0_TLB_FR_MASK $21 /* R10000 onwards */ 245#define COP_0_DIAG $22 /* Loongson 2F */ 246#define COP_0_ECC $26 247#define COP_0_CACHE_ERR $27 248#define COP_0_TAG_LO $28 249#define COP_0_TAG_HI $29 250#define COP_0_ERROR_PC $30 251 252/* 253 * RM7000 specific 254 */ 255#define COP_0_WATCH_1 $18 256#define COP_0_WATCH_2 $19 257#define COP_0_WATCH_M $24 258#define COP_0_PC_COUNT $25 259#define COP_0_PC_CTRL $22 260 261#define COP_0_ICR $20 /* Use cfc0/ctc0 to access */ 262 263/* 264 * Octeon specific 265 */ 266#define COP_0_TLB_PG_GRAIN $5, 1 267#define COP_0_CVMCTL $9, 7 268#define COP_0_CVMMEMCTL $11, 7 269#define COP_0_EBASE $15, 1 270 271/* 272 * Values for the code field in a break instruction. 273 */ 274#define BREAK_INSTR 0x0000000d 275#define BREAK_VAL_MASK 0x03ff0000 276#define BREAK_VAL_SHIFT 16 277#define BREAK_KDB_VAL 512 278#define BREAK_SSTEP_VAL 513 279#define BREAK_BRKPT_VAL 514 280#define BREAK_SOVER_VAL 515 281#define BREAK_DDB_VAL 516 282#define BREAK_FPUEMUL_VAL 517 283#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 284#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 285#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 286#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 287#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) 288#define BREAK_FPUEMUL (BREAK_INSTR | (BREAK_FPUEMUL_VAL << BREAK_VAL_SHIFT)) 289 290/* 291 * The floating point version and status registers. 292 */ 293#define FPC_ID $0 294#define FPC_CSR $31 295 296/* 297 * The low part of the TLB entry. 298 */ 299#define VMTLB_PF_NUM 0x3fffffc0 300#define VMTLB_ATTR_MASK 0x00000038 301#define VMTLB_MOD_BIT 0x00000004 302#define VMTLB_VALID_BIT 0x00000002 303#define VMTLB_GLOBAL_BIT 0x00000001 304 305#define VMTLB_PHYS_PAGE_SHIFT 6 306 307/* 308 * The high part of the TLB entry. 309 */ 310#define VMTLB_VIRT_PAGE_NUM 0xffffe000 311#define VMTLB_PID 0x000000ff 312#define VMTLB_PID_SHIFT 0 313#define VMTLB_VIRT_PAGE_SHIFT 12 314 315/* 316 * The number of process id entries. 317 */ 318#define VMNUM_PIDS 256 319 320/* 321 * TLB probe return codes. 322 */ 323#define VMTLB_NOT_FOUND 0 324#define VMTLB_FOUND 1 325#define VMTLB_FOUND_WITH_PATCH 2 326#define VMTLB_PROBE_ERROR 3 327 328#endif /* _KERNEL || _STANDALONE */ 329 330/* 331 * Exported definitions unique to mips cpu support. 332 */ 333 334#if defined(_KERNEL) && !defined(_LOCORE) 335 336#include <sys/device.h> 337#include <sys/lock.h> 338#include <machine/intr.h> 339#include <sys/sched.h> 340 341struct cpu_hwinfo { 342 uint32_t c0prid; 343 uint32_t c1prid; 344 uint32_t clock; /* Hz */ 345 uint32_t tlbsize; 346 uint type; 347 uint32_t l2size; 348}; 349 350struct cpu_info { 351 struct device *ci_dev; /* our device */ 352 struct cpu_info *ci_self; /* pointer to this structure */ 353 struct cpu_info *ci_next; /* next cpu */ 354 struct proc *ci_curproc; 355 struct user *ci_curprocpaddr; 356 struct proc *ci_fpuproc; /* pointer to last proc to use FP */ 357 uint32_t ci_delayconst; 358 struct cpu_hwinfo 359 ci_hw; 360 361 /* cache information */ 362 uint ci_cacheconfiguration; 363 uint ci_cacheways; 364 uint ci_l1instcachesize; 365 uint ci_l1instcacheline; 366 uint ci_l1instcacheset; 367 uint ci_l1datacachesize; 368 uint ci_l1datacacheline; 369 uint ci_l1datacacheset; 370 uint ci_l2size; 371 uint ci_l3size; 372 373 struct schedstate_percpu 374 ci_schedstate; 375 int ci_want_resched; /* need_resched() invoked */ 376 cpuid_t ci_cpuid; /* our CPU ID */ 377 uint32_t ci_randseed; /* per cpu random seed */ 378 int ci_ipl; /* software IPL */ 379 uint32_t ci_softpending; /* pending soft interrupts */ 380 int ci_clock_started; 381 u_int32_t ci_cpu_counter_last; /* last compare value loaded */ 382 u_int32_t ci_cpu_counter_interval; /* # of counter ticks/tick */ 383 384 u_int32_t ci_pendingticks; 385 struct pmap *ci_curpmap; 386 uint ci_intrdepth; /* interrupt depth */ 387#ifdef MULTIPROCESSOR 388 u_long ci_flags; /* flags; see below */ 389 struct intrhand ci_ipiih; 390#endif 391 volatile int ci_ddb; 392#define CI_DDB_RUNNING 0 393#define CI_DDB_SHOULDSTOP 1 394#define CI_DDB_STOPPED 2 395#define CI_DDB_ENTERDDB 3 396#define CI_DDB_INDDB 4 397 398#ifdef DIAGNOSTIC 399 int ci_mutex_level; 400#endif 401}; 402 403#define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 404#define CPUF_PRESENT 0x02 /* CPU is present */ 405#define CPUF_RUNNING 0x04 /* CPU is running */ 406 407extern struct cpu_info cpu_info_primary; 408extern struct cpu_info *cpu_info_list; 409#define CPU_INFO_ITERATOR int 410#define CPU_INFO_FOREACH(cii, ci) for (cii = 0, ci = cpu_info_list; \ 411 ci != NULL; ci = ci->ci_next) 412 413#define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0) 414 415#ifdef MULTIPROCESSOR 416#define MAXCPUS 4 417#define getcurcpu() hw_getcurcpu() 418#define setcurcpu(ci) hw_setcurcpu(ci) 419extern struct cpu_info *get_cpu_info(int); 420#define curcpu() getcurcpu() 421#define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 422#define cpu_number() (curcpu()->ci_cpuid) 423 424extern struct cpuset cpus_running; 425void cpu_unidle(struct cpu_info *); 426void cpu_boot_secondary_processors(void); 427#define cpu_boot_secondary(ci) hw_cpu_boot_secondary(ci) 428#define cpu_hatch(ci) hw_cpu_hatch(ci) 429 430vaddr_t alloc_contiguous_pages(size_t); 431 432#define MIPS64_IPI_NOP 0x00000001 433#define MIPS64_IPI_RENDEZVOUS 0x00000002 434#define MIPS64_IPI_DDB 0x00000004 435#define MIPS64_NIPIS 3 /* must not exceed 32 */ 436 437void mips64_ipi_init(void); 438void mips64_send_ipi(unsigned int, unsigned int); 439void smp_rendezvous_cpus(unsigned long, void (*)(void *), void *arg); 440 441#include <sys/mplock.h> 442#else 443#define MAXCPUS 1 444#define curcpu() (&cpu_info_primary) 445#define CPU_IS_PRIMARY(ci) 1 446#define cpu_number() 0 447#define cpu_unidle(ci) 448#define get_cpu_info(i) (&cpu_info_primary) 449#endif 450 451void cpu_startclock(struct cpu_info *); 452 453#include <machine/frame.h> 454 455/* 456 * Arguments to hardclock encapsulate the previous machine state in 457 * an opaque clockframe. 458 */ 459#define clockframe trap_frame /* Use normal trap frame */ 460 461#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 462#define CLKF_PC(framep) ((framep)->pc) 463#define CLKF_INTR(framep) (curcpu()->ci_intrdepth > 1) /* XXX */ 464 465/* 466 * This is used during profiling to integrate system time. 467 */ 468#define PROC_PC(p) ((p)->p_md.md_regs->pc) 469 470/* 471 * Preempt the current process if in interrupt from user mode, 472 * or after the current trap/syscall if in system mode. 473 */ 474#define need_resched(ci) \ 475 do { \ 476 (ci)->ci_want_resched = 1; \ 477 if ((ci)->ci_curproc != NULL) \ 478 aston((ci)->ci_curproc); \ 479 } while(0) 480#define clear_resched(ci) (ci)->ci_want_resched = 0 481 482/* 483 * Give a profiling tick to the current process when the user profiling 484 * buffer pages are invalid. On the PICA, request an ast to send us 485 * through trap, marking the proc as needing a profiling tick. 486 */ 487#define need_proftick(p) aston(p) 488 489/* 490 * Notify the current process (p) that it has a signal pending, 491 * process as soon as possible. 492 */ 493#ifdef MULTIPROCESSOR 494#define signotify(p) (aston(p), cpu_unidle(p->p_cpu)) 495#else 496#define signotify(p) aston(p) 497#endif 498 499#define aston(p) p->p_md.md_astpending = 1 500 501#endif /* _KERNEL && !_LOCORE */ 502 503/* 504 * CTL_MACHDEP definitions. 505 */ 506#define CPU_ALLOWAPERTURE 1 /* allow mmap of /dev/xf86 */ 507#define CPU_KBDRESET 2 /* keyboard reset */ 508#define CPU_MAXID 3 /* number of valid machdep ids */ 509 510#define CTL_MACHDEP_NAMES { \ 511 { 0, 0 }, \ 512 { "allowaperture", CTLTYPE_INT }, \ 513 { "kbdreset", CTLTYPE_INT }, \ 514} 515 516/* 517 * MIPS CPU types (cp_imp). 518 */ 519#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 520#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 521#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 522#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 523#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 524#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 525#define MIPS_OCTEON 0x06 /* Cavium OCTEON MIPS64R2*/ 526#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 527#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 528#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 529#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 530#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ 531#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 532#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 533#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 534#define MIPS_R4600 0x20 /* PMCS R4600 Orion ISA III */ 535#define MIPS_R4700 0x21 /* PMCS R4700 Orion ISA III */ 536#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 537#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 538#define MIPS_RM7000 0x27 /* PMCS RM7000 CPU ISA IV */ 539#define MIPS_RM52X0 0x28 /* PMCS RM52X0 CPU ISA IV */ 540#define MIPS_RM9000 0x34 /* PMCS RM9000 CPU ISA IV */ 541#define MIPS_LOONGSON 0x42 /* STC LoongSon CPU ISA III */ 542#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ 543#define MIPS_LOONGSON2 0x63 /* STC LoongSon2 CPU ISA III */ 544 545/* 546 * MIPS FPU types. Only soft, rest is the same as cpu type. 547 */ 548#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 549 550 551#if defined(_KERNEL) && !defined(_LOCORE) 552 553extern vaddr_t CpuCacheAliasMask; 554 555struct exec_package; 556struct tlb_entry; 557struct user; 558 559u_int cp0_get_count(void); 560uint32_t cp0_get_config(void); 561uint32_t cp0_get_prid(void); 562void cp0_set_compare(u_int); 563u_int cp1_get_prid(void); 564void tlb_set_page_mask(uint32_t); 565void tlb_set_pid(int); 566void tlb_set_wired(int); 567 568/* 569 * Available cache operation routines. See <machine/cpu.h> for more. 570 */ 571int Octeon_ConfigCache(struct cpu_info *); 572void Octeon_SyncCache(struct cpu_info *); 573void Octeon_InvalidateICache(struct cpu_info *, vaddr_t, size_t); 574void Octeon_SyncDCachePage(struct cpu_info *, paddr_t); 575void Octeon_HitSyncDCache(struct cpu_info *, paddr_t, size_t); 576void Octeon_HitInvalidateDCache(struct cpu_info *, paddr_t, size_t); 577void Octeon_IOSyncDCache(struct cpu_info *, paddr_t, size_t, int); 578 579int Loongson2_ConfigCache(struct cpu_info *); 580void Loongson2_SyncCache(struct cpu_info *); 581void Loongson2_InvalidateICache(struct cpu_info *, vaddr_t, size_t); 582void Loongson2_SyncDCachePage(struct cpu_info *, paddr_t); 583void Loongson2_HitSyncDCache(struct cpu_info *, paddr_t, size_t); 584void Loongson2_HitInvalidateDCache(struct cpu_info *, paddr_t, size_t); 585void Loongson2_IOSyncDCache(struct cpu_info *, paddr_t, size_t, int); 586 587int Mips5k_ConfigCache(struct cpu_info *); 588void Mips5k_SyncCache(struct cpu_info *); 589void Mips5k_InvalidateICache(struct cpu_info *, vaddr_t, size_t); 590void Mips5k_SyncDCachePage(struct cpu_info *, vaddr_t); 591void Mips5k_HitSyncDCache(struct cpu_info *, vaddr_t, size_t); 592void Mips5k_HitInvalidateDCache(struct cpu_info *, vaddr_t, size_t); 593void Mips5k_IOSyncDCache(struct cpu_info *, vaddr_t, size_t, int); 594 595int Mips10k_ConfigCache(struct cpu_info *); 596void Mips10k_SyncCache(struct cpu_info *); 597void Mips10k_InvalidateICache(struct cpu_info *, vaddr_t, size_t); 598void Mips10k_SyncDCachePage(struct cpu_info *, vaddr_t); 599void Mips10k_HitSyncDCache(struct cpu_info *, vaddr_t, size_t); 600void Mips10k_HitInvalidateDCache(struct cpu_info *, vaddr_t, size_t); 601void Mips10k_IOSyncDCache(struct cpu_info *, vaddr_t, size_t, int); 602 603void tlb_flush(int); 604void tlb_flush_addr(vaddr_t); 605void tlb_write_indexed(int, struct tlb_entry *); 606int tlb_update(vaddr_t, unsigned); 607void tlb_read(int, struct tlb_entry *); 608 609void build_trampoline(vaddr_t, vaddr_t); 610int exec_md_map(struct proc *, struct exec_package *); 611void savectx(struct user *, int); 612 613void enable_fpu(struct proc *); 614void save_fpu(void); 615int fpe_branch_emulate(struct proc *, struct trap_frame *, uint32_t, 616 vaddr_t); 617 618int guarded_read_4(paddr_t, uint32_t *); 619int guarded_write_4(paddr_t, uint32_t); 620 621void MipsFPTrap(struct trap_frame *); 622register_t MipsEmulateBranch(struct trap_frame *, vaddr_t, uint32_t, uint32_t); 623 624/* 625 * Low level access routines to CPU registers 626 */ 627 628void setsoftintr0(void); 629void clearsoftintr0(void); 630void setsoftintr1(void); 631void clearsoftintr1(void); 632uint32_t enableintr(void); 633uint32_t disableintr(void); 634uint32_t getsr(void); 635uint32_t setsr(uint32_t); 636 637#endif /* _KERNEL && !_LOCORE */ 638#endif /* !_MIPS_CPU_H_ */ 639