cpu.h revision 1.59
1/* $OpenBSD: cpu.h,v 1.59 2010/08/30 08:52:10 syuu Exp $ */ 2 3/*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * Copyright (C) 1989 Digital Equipment Corporation. 35 * Permission to use, copy, modify, and distribute this software and 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 */ 44 45#ifndef _MIPS_CPU_H_ 46#define _MIPS_CPU_H_ 47 48#ifndef _LOCORE 49 50/* 51 * MIPS32-style segment definitions. 52 * They only cover the first 512MB of physical addresses. 53 */ 54#define CKSEG0_BASE 0xffffffff80000000UL 55#define CKSEG1_BASE 0xffffffffa0000000UL 56#define CKSSEG_BASE 0xffffffffc0000000UL 57#define CKSEG3_BASE 0xffffffffe0000000UL 58#define CKSEG_SIZE 0x0000000020000000UL 59 60#define CKSEG0_TO_PHYS(x) ((u_long)(x) & (CKSEG_SIZE - 1)) 61#define CKSEG1_TO_PHYS(x) ((u_long)(x) & (CKSEG_SIZE - 1)) 62#define PHYS_TO_CKSEG0(x) ((u_long)(x) | CKSEG0_BASE) 63#define PHYS_TO_CKSEG1(x) ((u_long)(x) | CKSEG1_BASE) 64 65/* 66 * MIPS64-style segment definitions. 67 * These allow for 36 bits of addressable physical memory, thus 64GB. 68 */ 69 70/* 71 * Cache Coherency Attributes. 72 */ 73/* r8k only */ 74#define CCA_NC_COPROCESSOR 0UL /* uncached, coprocessor ordered */ 75/* common to r4, r5k, r8k and r1xk */ 76#define CCA_NC 2UL /* uncached, write-around */ 77#define CCA_NONCOHERENT 3UL /* cached, non-coherent, write-back */ 78/* r8k, r1xk only */ 79#define CCA_COHERENT_EXCL 4UL /* cached, coherent, exclusive */ 80#define CCA_COHERENT_EXCLWRITE 5UL /* cached, coherent, exclusive write */ 81/* r1xk only */ 82#define CCA_NC_ACCELERATED 7UL /* uncached accelerated */ 83/* r4k only */ 84#define CCA_COHERENT_UPDWRITE 6UL /* cached, coherent, update on write */ 85 86#ifdef TGT_COHERENT 87#define CCA_CACHED CCA_COHERENT_EXCLWRITE 88#else 89#define CCA_CACHED CCA_NONCOHERENT 90#endif 91 92/* 93 * Uncached spaces. 94 * R1x000 processors use bits 58:57 of uncached virtual addresses (CCA_NC) 95 * to select different spaces. Unfortunately, other processors need these 96 * bits to be zero, so uncached address have to be decided at runtime. 97 */ 98#define SP_HUB 0UL /* Hub space */ 99#define SP_IO 1UL /* I/O space */ 100#define SP_SPECIAL 2UL /* Memory Special space */ 101#define SP_NC 3UL /* Memory Uncached space */ 102 103extern vaddr_t uncached_base; 104 105#define XKSSSEG_BASE 0x4000000000000000UL 106#define XKPHYS_BASE 0x8000000000000000UL 107#define XKSSEG_BASE 0xc000000000000000UL 108 109#define XKPHYS_TO_PHYS(x) ((paddr_t)(x) & 0x0000000fffffffffUL) 110#define PHYS_TO_XKPHYS(x,c) ((paddr_t)(x) | XKPHYS_BASE | ((c) << 59)) 111#define PHYS_TO_XKPHYS_UNCACHED(x,s) \ 112 (PHYS_TO_XKPHYS(x, CCA_NC) | ((s) << 57)) 113#define PHYS_TO_UNCACHED(x) ((paddr_t)(x) | uncached_base) 114#define IS_XKPHYS(va) (((va) >> 62) == 2) 115#define XKPHYS_TO_CCA(x) (((x) >> 59) & 0x07) 116#define XKPHYS_TO_SP(x) (((x) >> 57) & 0x03) 117 118#endif /* _LOCORE */ 119 120#ifdef _KERNEL 121 122/* 123 * Status register. 124 */ 125#define SR_XX 0x80000000 126#define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */ 127#define SR_COP_0_BIT 0x10000000 128#define SR_COP_1_BIT 0x20000000 129#define SR_RP 0x08000000 130#define SR_FR_32 0x04000000 131#define SR_RE 0x02000000 132#define SR_DSD 0x01000000 /* Only on R12000 */ 133#define SR_BOOT_EXC_VEC 0x00400000 134#define SR_TLB_SHUTDOWN 0x00200000 135#define SR_SOFT_RESET 0x00100000 136#define SR_DIAG_CH 0x00040000 137#define SR_DIAG_CE 0x00020000 138#define SR_DIAG_DE 0x00010000 139#define SR_KX 0x00000080 140#define SR_SX 0x00000040 141#define SR_UX 0x00000020 142#define SR_KSU_MASK 0x00000018 143#define SR_KSU_USER 0x00000010 144#define SR_KSU_SUPER 0x00000008 145#define SR_KSU_KERNEL 0x00000000 146#define SR_ERL 0x00000004 147#define SR_EXL 0x00000002 148#define SR_INT_ENAB 0x00000001 149 150#define SR_INT_MASK 0x0000ff00 151#define SOFT_INT_MASK_0 0x00000100 152#define SOFT_INT_MASK_1 0x00000200 153#define SR_INT_MASK_0 0x00000400 154#define SR_INT_MASK_1 0x00000800 155#define SR_INT_MASK_2 0x00001000 156#define SR_INT_MASK_3 0x00002000 157#define SR_INT_MASK_4 0x00004000 158#define SR_INT_MASK_5 0x00008000 159/* 160 * Interrupt control register in RM7000. Expansion of interrupts. 161 */ 162#define IC_INT_MASK 0x00003f00 /* Two msb reserved */ 163#define IC_INT_MASK_6 0x00000100 164#define IC_INT_MASK_7 0x00000200 165#define IC_INT_MASK_8 0x00000400 166#define IC_INT_MASK_9 0x00000800 167#define IC_INT_TIMR 0x00001000 /* 12 Timer */ 168#define IC_INT_PERF 0x00002000 /* 13 Performance counter */ 169#define IC_INT_TE 0x00000080 /* Timer on INT11 */ 170 171#define ALL_INT_MASK ((IC_INT_MASK << 8) | SR_INT_MASK) 172#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 173#define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK) 174 175 176/* 177 * The bits in the cause register. 178 * 179 * CR_BR_DELAY Exception happened in branch delay slot. 180 * CR_COP_ERR Coprocessor error. 181 * CR_IP Interrupt pending bits defined below. 182 * CR_EXC_CODE The exception type (see exception codes below). 183 */ 184#define CR_BR_DELAY 0x80000000 185#define CR_COP_ERR 0x30000000 186#define CR_EXC_CODE 0x0000007c 187#define CR_EXC_CODE_SHIFT 2 188#define CR_IPEND 0x003fff00 189#define CR_INT_SOFT0 0x00000100 190#define CR_INT_SOFT1 0x00000200 191#define CR_INT_0 0x00000400 192#define CR_INT_1 0x00000800 193#define CR_INT_2 0x00001000 194#define CR_INT_3 0x00002000 195#define CR_INT_4 0x00004000 196#define CR_INT_5 0x00008000 197/* Following on RM7000 */ 198#define CR_INT_6 0x00010000 199#define CR_INT_7 0x00020000 200#define CR_INT_8 0x00040000 201#define CR_INT_9 0x00080000 202#define CR_INT_HARD 0x000ffc00 203#define CR_INT_TIMR 0x00100000 /* 12 Timer */ 204#define CR_INT_PERF 0x00200000 /* 13 Performance counter */ 205 206/* 207 * The bits in the context register. 208 */ 209#define CNTXT_PTE_BASE 0xff800000 210#define CNTXT_BAD_VPN2 0x007ffff0 211 212/* 213 * Location of exception vectors. 214 */ 215#define RESET_EXC_VEC (CKSEG1_BASE + 0x1fc00000) 216#define TLB_MISS_EXC_VEC (CKSEG0_BASE + 0x00000000) 217#define XTLB_MISS_EXC_VEC (CKSEG0_BASE + 0x00000080) 218#define CACHE_ERR_EXC_VEC (CKSEG0_BASE + 0x00000100) 219#define GEN_EXC_VEC (CKSEG0_BASE + 0x00000180) 220 221/* 222 * Coprocessor 0 registers: 223 */ 224#define COP_0_TLB_INDEX $0 225#define COP_0_TLB_RANDOM $1 226#define COP_0_TLB_LO0 $2 227#define COP_0_TLB_LO1 $3 228#define COP_0_TLB_CONTEXT $4 229#define COP_0_TLB_PG_MASK $5 230#define COP_0_TLB_WIRED $6 231#define COP_0_BAD_VADDR $8 232#define COP_0_COUNT $9 233#define COP_0_TLB_HI $10 234#define COP_0_COMPARE $11 235#define COP_0_STATUS_REG $12 236#define COP_0_CAUSE_REG $13 237#define COP_0_EXC_PC $14 238#define COP_0_PRID $15 239#define COP_0_CONFIG $16 240#define COP_0_LLADDR $17 241#define COP_0_WATCH_LO $18 242#define COP_0_WATCH_HI $19 243#define COP_0_TLB_XCONTEXT $20 244#define COP_0_TLB_FR_MASK $21 /* R10000 onwards */ 245#define COP_0_DIAG $22 /* Loongson 2F */ 246#define COP_0_ECC $26 247#define COP_0_CACHE_ERR $27 248#define COP_0_TAG_LO $28 249#define COP_0_TAG_HI $29 250#define COP_0_ERROR_PC $30 251 252/* 253 * RM7000 specific 254 */ 255#define COP_0_WATCH_1 $18 256#define COP_0_WATCH_2 $19 257#define COP_0_WATCH_M $24 258#define COP_0_PC_COUNT $25 259#define COP_0_PC_CTRL $22 260 261#define COP_0_ICR $20 /* Use cfc0/ctc0 to access */ 262 263/* 264 * Values for the code field in a break instruction. 265 */ 266#define BREAK_INSTR 0x0000000d 267#define BREAK_VAL_MASK 0x03ff0000 268#define BREAK_VAL_SHIFT 16 269#define BREAK_KDB_VAL 512 270#define BREAK_SSTEP_VAL 513 271#define BREAK_BRKPT_VAL 514 272#define BREAK_SOVER_VAL 515 273#define BREAK_DDB_VAL 516 274#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 275#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 276#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 277#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 278#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) 279 280/* 281 * The floating point version and status registers. 282 */ 283#define FPC_ID $0 284#define FPC_CSR $31 285 286/* 287 * The floating point coprocessor status register bits. 288 */ 289#define FPC_ROUNDING_BITS 0x00000003 290#define FPC_ROUND_RN 0x00000000 291#define FPC_ROUND_RZ 0x00000001 292#define FPC_ROUND_RP 0x00000002 293#define FPC_ROUND_RM 0x00000003 294#define FPC_STICKY_BITS 0x0000007c 295#define FPC_STICKY_INEXACT 0x00000004 296#define FPC_STICKY_UNDERFLOW 0x00000008 297#define FPC_STICKY_OVERFLOW 0x00000010 298#define FPC_STICKY_DIV0 0x00000020 299#define FPC_STICKY_INVALID 0x00000040 300#define FPC_ENABLE_BITS 0x00000f80 301#define FPC_ENABLE_INEXACT 0x00000080 302#define FPC_ENABLE_UNDERFLOW 0x00000100 303#define FPC_ENABLE_OVERFLOW 0x00000200 304#define FPC_ENABLE_DIV0 0x00000400 305#define FPC_ENABLE_INVALID 0x00000800 306#define FPC_EXCEPTION_BITS 0x0003f000 307#define FPC_EXCEPTION_INEXACT 0x00001000 308#define FPC_EXCEPTION_UNDERFLOW 0x00002000 309#define FPC_EXCEPTION_OVERFLOW 0x00004000 310#define FPC_EXCEPTION_DIV0 0x00008000 311#define FPC_EXCEPTION_INVALID 0x00010000 312#define FPC_EXCEPTION_UNIMPL 0x00020000 313#define FPC_COND_BIT 0x00800000 314#define FPC_FLUSH_BIT 0x01000000 315#define FPC_MBZ_BITS 0xfe7c0000 316 317/* 318 * Constants to determine if have a floating point instruction. 319 */ 320#define OPCODE_SHIFT 26 321#define OPCODE_C1 0x11 322 323/* 324 * The low part of the TLB entry. 325 */ 326#define VMTLB_PF_NUM 0x3fffffc0 327#define VMTLB_ATTR_MASK 0x00000038 328#define VMTLB_MOD_BIT 0x00000004 329#define VMTLB_VALID_BIT 0x00000002 330#define VMTLB_GLOBAL_BIT 0x00000001 331 332#define VMTLB_PHYS_PAGE_SHIFT 6 333 334/* 335 * The high part of the TLB entry. 336 */ 337#define VMTLB_VIRT_PAGE_NUM 0xffffe000 338#define VMTLB_PID 0x000000ff 339#define VMTLB_PID_SHIFT 0 340#define VMTLB_VIRT_PAGE_SHIFT 12 341 342/* 343 * The number of process id entries. 344 */ 345#define VMNUM_PIDS 256 346 347/* 348 * TLB probe return codes. 349 */ 350#define VMTLB_NOT_FOUND 0 351#define VMTLB_FOUND 1 352#define VMTLB_FOUND_WITH_PATCH 2 353#define VMTLB_PROBE_ERROR 3 354 355/* 356 * Exported definitions unique to mips cpu support. 357 */ 358 359#ifndef _LOCORE 360 361#include <sys/device.h> 362#include <sys/lock.h> 363#include <machine/intr.h> 364#include <sys/sched.h> 365 366struct cpu_hwinfo { 367 uint32_t c0prid; 368 uint32_t c1prid; 369 uint32_t clock; /* Hz */ 370 uint32_t tlbsize; 371 uint type; 372 uint32_t l2size; 373}; 374 375struct cpu_info { 376 struct device *ci_dev; /* our device */ 377 struct cpu_info *ci_self; /* pointer to this structure */ 378 struct cpu_info *ci_next; /* next cpu */ 379 struct proc *ci_curproc; 380 struct user *ci_curprocpaddr; 381 struct proc *ci_fpuproc; /* pointer to last proc to use FP */ 382 uint32_t ci_delayconst; 383 struct cpu_hwinfo 384 ci_hw; 385 386 /* cache information */ 387 uint ci_cacheconfiguration; 388 uint ci_cacheways; 389 uint ci_l1instcachesize; 390 uint ci_l1instcacheline; 391 uint ci_l1instcacheset; 392 uint ci_l1datacachesize; 393 uint ci_l1datacacheline; 394 uint ci_l1datacacheset; 395 uint ci_l2size; 396 uint ci_l3size; 397 398 struct schedstate_percpu 399 ci_schedstate; 400 int ci_want_resched; /* need_resched() invoked */ 401 cpuid_t ci_cpuid; /* our CPU ID */ 402 uint32_t ci_randseed; /* per cpu random seed */ 403 int ci_ipl; /* software IPL */ 404 uint32_t ci_softpending; /* pending soft interrupts */ 405 int ci_clock_started; 406 u_int32_t ci_cpu_counter_last; 407 u_int32_t ci_cpu_counter_interval; 408 u_int32_t ci_pendingticks; 409 struct pmap *ci_curpmap; 410 uint ci_intrdepth; /* interrupt depth */ 411#ifdef MULTIPROCESSOR 412 u_long ci_flags; /* flags; see below */ 413 struct intrhand ci_ipiih; 414#endif 415 volatile int ci_ddb; 416#define CI_DDB_RUNNING 0 417#define CI_DDB_SHOULDSTOP 1 418#define CI_DDB_STOPPED 2 419#define CI_DDB_ENTERDDB 3 420#define CI_DDB_INDDB 4 421}; 422 423#define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 424#define CPUF_PRESENT 0x02 /* CPU is present */ 425#define CPUF_RUNNING 0x04 /* CPU is running */ 426 427extern struct cpu_info cpu_info_primary; 428extern struct cpu_info *cpu_info_list; 429#define CPU_INFO_ITERATOR int 430#define CPU_INFO_FOREACH(cii, ci) for (cii = 0, ci = cpu_info_list; \ 431 ci != NULL; ci = ci->ci_next) 432 433#define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0) 434 435#ifdef MULTIPROCESSOR 436#define MAXCPUS 4 437extern struct cpu_info *getcurcpu(void); 438extern void setcurcpu(struct cpu_info *); 439extern struct cpu_info *get_cpu_info(int); 440#define curcpu() getcurcpu() 441#define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 442#define cpu_number() (curcpu()->ci_cpuid) 443 444extern struct cpuset cpus_running; 445void cpu_unidle(struct cpu_info *); 446void cpu_boot_secondary_processors(void); 447#define cpu_boot_secondary(ci) hw_cpu_boot_secondary(ci) 448#define cpu_hatch(ci) hw_cpu_hatch(ci) 449 450vaddr_t alloc_contiguous_pages(size_t); 451 452#define MIPS64_IPI_NOP 0x00000001 453#define MIPS64_IPI_RENDEZVOUS 0x00000002 454#define MIPS64_IPI_DDB 0x00000004 455#define MIPS64_NIPIS 3 /* must not exceed 32 */ 456 457void mips64_ipi_init(void); 458void mips64_send_ipi(unsigned int, unsigned int); 459void smp_rendezvous_cpus(unsigned long, void (*)(void *), void *arg); 460 461#include <sys/mplock.h> 462#else 463#define MAXCPUS 1 464#define curcpu() (&cpu_info_primary) 465#define CPU_IS_PRIMARY(ci) 1 466#define cpu_number() 0 467#define cpu_unidle(ci) 468#define get_cpu_info(i) (&cpu_info_primary) 469#endif 470 471void cpu_startclock(struct cpu_info *); 472 473#include <machine/frame.h> 474 475#endif /* _LOCORE */ 476 477#ifndef _LOCORE 478 479/* 480 * Arguments to hardclock encapsulate the previous machine state in 481 * an opaque clockframe. 482 */ 483#define clockframe trap_frame /* Use normal trap frame */ 484 485#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 486#define CLKF_PC(framep) ((framep)->pc) 487#define CLKF_INTR(framep) (curcpu()->ci_intrdepth > 1) /* XXX */ 488 489/* 490 * This is used during profiling to integrate system time. 491 */ 492#define PROC_PC(p) ((p)->p_md.md_regs->pc) 493 494/* 495 * Preempt the current process if in interrupt from user mode, 496 * or after the current trap/syscall if in system mode. 497 */ 498#define need_resched(ci) \ 499 do { \ 500 (ci)->ci_want_resched = 1; \ 501 if ((ci)->ci_curproc != NULL) \ 502 aston((ci)->ci_curproc); \ 503 } while(0) 504#define clear_resched(ci) (ci)->ci_want_resched = 0 505 506/* 507 * Give a profiling tick to the current process when the user profiling 508 * buffer pages are invalid. On the PICA, request an ast to send us 509 * through trap, marking the proc as needing a profiling tick. 510 */ 511#define need_proftick(p) aston(p) 512 513/* 514 * Notify the current process (p) that it has a signal pending, 515 * process as soon as possible. 516 */ 517#ifdef MULTIPROCESSOR 518#define signotify(p) (aston(p), cpu_unidle(p->p_cpu)) 519#else 520#define signotify(p) aston(p) 521#endif 522 523#define aston(p) p->p_md.md_astpending = 1 524 525#endif /* !_LOCORE */ 526#endif /* _KERNEL */ 527 528/* 529 * CTL_MACHDEP definitions. 530 */ 531#define CPU_ALLOWAPERTURE 1 /* allow mmap of /dev/xf86 */ 532#define CPU_KBDRESET 2 /* keyboard reset */ 533#define CPU_MAXID 3 /* number of valid machdep ids */ 534 535#define CTL_MACHDEP_NAMES { \ 536 { 0, 0 }, \ 537 { "allowaperture", CTLTYPE_INT }, \ 538 { "kbdreset", CTLTYPE_INT }, \ 539} 540 541/* 542 * MIPS CPU types (cp_imp). 543 */ 544#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 545#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 546#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 547#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 548#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 549#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 550#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 551#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 552#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 553#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 554#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ 555#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 556#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 557#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 558#define MIPS_R4600 0x20 /* PMCS R4600 Orion ISA III */ 559#define MIPS_R4700 0x21 /* PMCS R4700 Orion ISA III */ 560#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 561#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 562#define MIPS_RM7000 0x27 /* PMCS RM7000 CPU ISA IV */ 563#define MIPS_RM52X0 0x28 /* PMCS RM52X0 CPU ISA IV */ 564#define MIPS_RM9000 0x34 /* PMCS RM9000 CPU ISA IV */ 565#define MIPS_LOONGSON 0x42 /* STC LoongSon CPU ISA III */ 566#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ 567#define MIPS_LOONGSON2 0x63 /* STC LoongSon2 CPU ISA III */ 568 569/* 570 * MIPS FPU types. Only soft, rest is the same as cpu type. 571 */ 572#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 573 574 575#if defined(_KERNEL) && !defined(_LOCORE) 576 577extern vaddr_t CpuCacheAliasMask; 578 579struct tlb_entry; 580struct user; 581 582u_int cp0_get_count(void); 583uint32_t cp0_get_config(void); 584uint32_t cp0_get_prid(void); 585void cp0_set_compare(u_int); 586u_int cp1_get_prid(void); 587void tlb_set_page_mask(uint32_t); 588void tlb_set_pid(int); 589void tlb_set_wired(int); 590 591/* 592 * Available cache operation routines. See <machine/cpu.h> for more. 593 */ 594 595int Loongson2_ConfigCache(struct cpu_info *); 596void Loongson2_SyncCache(struct cpu_info *); 597void Loongson2_InvalidateICache(struct cpu_info *, vaddr_t, size_t); 598void Loongson2_SyncDCachePage(struct cpu_info *, paddr_t); 599void Loongson2_HitSyncDCache(struct cpu_info *, paddr_t, size_t); 600void Loongson2_HitInvalidateDCache(struct cpu_info *, paddr_t, size_t); 601void Loongson2_IOSyncDCache(struct cpu_info *, paddr_t, size_t, int); 602 603int Mips5k_ConfigCache(struct cpu_info *); 604void Mips5k_SyncCache(struct cpu_info *); 605void Mips5k_InvalidateICache(struct cpu_info *, vaddr_t, size_t); 606void Mips5k_SyncDCachePage(struct cpu_info *, vaddr_t); 607void Mips5k_HitSyncDCache(struct cpu_info *, vaddr_t, size_t); 608void Mips5k_HitInvalidateDCache(struct cpu_info *, vaddr_t, size_t); 609void Mips5k_IOSyncDCache(struct cpu_info *, vaddr_t, size_t, int); 610 611int Mips10k_ConfigCache(struct cpu_info *); 612void Mips10k_SyncCache(struct cpu_info *); 613void Mips10k_InvalidateICache(struct cpu_info *, vaddr_t, size_t); 614void Mips10k_SyncDCachePage(struct cpu_info *, vaddr_t); 615void Mips10k_HitSyncDCache(struct cpu_info *, vaddr_t, size_t); 616void Mips10k_HitInvalidateDCache(struct cpu_info *, vaddr_t, size_t); 617void Mips10k_IOSyncDCache(struct cpu_info *, vaddr_t, size_t, int); 618 619void tlb_flush(int); 620void tlb_flush_addr(vaddr_t); 621void tlb_write_indexed(int, struct tlb_entry *); 622int tlb_update(vaddr_t, unsigned); 623void tlb_read(int, struct tlb_entry *); 624 625void savectx(struct user *, int); 626 627void enable_fpu(struct proc *); 628void save_fpu(void); 629 630int guarded_read_4(paddr_t, uint32_t *); 631int guarded_write_4(paddr_t, uint32_t); 632 633extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */ 634extern u_int32_t cpu_counter_last; /* Last compare value loaded */ 635 636/* 637 * Low level access routines to CPU registers 638 */ 639 640void setsoftintr0(void); 641void clearsoftintr0(void); 642void setsoftintr1(void); 643void clearsoftintr1(void); 644uint32_t enableintr(void); 645uint32_t disableintr(void); 646uint32_t getsr(void); 647uint32_t setsr(uint32_t); 648 649#endif /* _KERNEL */ 650#endif /* !_MIPS_CPU_H_ */ 651