cpu.h revision 1.42
1/* $OpenBSD: cpu.h,v 1.42 2009/10/30 08:13:57 syuu Exp $ */ 2 3/*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * Copyright (C) 1989 Digital Equipment Corporation. 35 * Permission to use, copy, modify, and distribute this software and 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 */ 44 45#ifndef _MIPS_CPU_H_ 46#define _MIPS_CPU_H_ 47 48/* 49 * MIPS32-style segment definitions. 50 * They only cover the first 512MB of physical addresses. 51 */ 52#define KSEG0_BASE 0xffffffff80000000 53#define KSEG1_BASE 0xffffffffa0000000 54#define KSSEG_BASE 0xffffffffc0000000 55#define KSEG3_BASE 0xffffffffe0000000 56#define KSEG_SIZE 0x0000000020000000 57 58#define KSEG0_TO_PHYS(x) ((u_long)(x) & (KSEG_SIZE - 1)) 59#define KSEG1_TO_PHYS(x) ((u_long)(x) & (KSEG_SIZE - 1)) 60#define PHYS_TO_KSEG0(x) ((u_long)(x) | KSEG0_BASE) 61#define PHYS_TO_KSEG1(x) ((u_long)(x) | KSEG1_BASE) 62#define PHYS_TO_KSEG3(x) ((u_long)(x) | KSEG3_BASE) 63 64/* 65 * MIPS64-style segment definitions. 66 * These allow for 36 bits of addressable physical memory, thus 64GB. 67 */ 68 69#ifndef _LOCORE 70 71/* 72 * Cache Coherency Attributes. 73 */ 74/* r8k only */ 75#define CCA_NC_COPROCESSOR 0UL /* uncached, coprocessor ordered */ 76/* common to r4, r5k, r8k and r1xk */ 77#define CCA_NC 2UL /* uncached, write-around */ 78#define CCA_NONCOHERENT 3UL /* cached, non-coherent, write-back */ 79/* r8k, r1xk only */ 80#define CCA_COHERENT_EXCL 4UL /* cached, coherent, exclusive */ 81#define CCA_COHERENT_EXCLWRITE 5UL /* cached, coherent, exclusive write */ 82/* r1xk only */ 83#define CCA_NC_ACCELERATED 7UL /* uncached accelerated */ 84/* r4k only */ 85#define CCA_COHERENT_UPDWRITE 6UL /* cached, coherent, update on write */ 86 87#ifdef TGT_COHERENT 88#define CCA_CACHED CCA_COHERENT_EXCLWRITE 89#else 90#define CCA_CACHED CCA_NONCOHERENT 91#endif 92 93/* 94 * Uncached spaces. 95 * R1x000 processors use bits 58:57 of uncached virtual addresses (CCA_NC) 96 * to select different spaces. Unfortunately, other processors need these 97 * bits to be zero, so uncached address have to be decided at runtime. 98 */ 99#define SP_HUB 0UL /* Hub space */ 100#define SP_IO 1UL /* I/O space */ 101#define SP_SPECIAL 2UL /* Memory Special space */ 102#define SP_NC 3UL /* Memory Uncached space */ 103 104extern vaddr_t uncached_base; 105 106#endif /* _LOCORE */ 107 108#define XKPHYS_BASE 0x8000000000000000UL 109#define XKPHYS_TO_PHYS(x) ((paddr_t)(x) & 0x0000000fffffffffUL) 110#define PHYS_TO_XKPHYS(x,c) ((paddr_t)(x) | XKPHYS_BASE | ((c) << 59)) 111#define PHYS_TO_XKPHYS_UNCACHED(x,s) \ 112 (PHYS_TO_XKPHYS(x, CCA_NC) | ((s) << 57)) 113#define PHYS_TO_UNCACHED(x) ((paddr_t)(x) | uncached_base) 114#define IS_XKPHYS(va) (((va) >> 62) == 2) 115#define XKPHYS_TO_CCA(x) (((x) >> 59) & 0x07) 116#define XKPHYS_TO_SP(x) (((x) >> 57) & 0x03) 117 118#ifdef _KERNEL 119 120/* 121 * Status register. 122 */ 123#define SR_XX 0x80000000 124#define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */ 125#define SR_COP_0_BIT 0x10000000 126#define SR_COP_1_BIT 0x20000000 127#define SR_RP 0x08000000 128#define SR_FR_32 0x04000000 129#define SR_RE 0x02000000 130#define SR_DSD 0x01000000 /* Only on R12000 */ 131#define SR_BOOT_EXC_VEC 0x00400000 132#define SR_TLB_SHUTDOWN 0x00200000 133#define SR_SOFT_RESET 0x00100000 134#define SR_DIAG_CH 0x00040000 135#define SR_DIAG_CE 0x00020000 136#define SR_DIAG_DE 0x00010000 137#define SR_KX 0x00000080 138#define SR_SX 0x00000040 139#define SR_UX 0x00000020 140#define SR_KSU_MASK 0x00000018 141#define SR_KSU_USER 0x00000010 142#define SR_KSU_SUPER 0x00000008 143#define SR_KSU_KERNEL 0x00000000 144#define SR_ERL 0x00000004 145#define SR_EXL 0x00000002 146#define SR_INT_ENAB 0x00000001 147 148#define SR_INT_MASK 0x0000ff00 149#define SOFT_INT_MASK_0 0x00000100 150#define SOFT_INT_MASK_1 0x00000200 151#define SR_INT_MASK_0 0x00000400 152#define SR_INT_MASK_1 0x00000800 153#define SR_INT_MASK_2 0x00001000 154#define SR_INT_MASK_3 0x00002000 155#define SR_INT_MASK_4 0x00004000 156#define SR_INT_MASK_5 0x00008000 157/* 158 * Interrupt control register in RM7000. Expansion of interrupts. 159 */ 160#define IC_INT_MASK 0x00003f00 /* Two msb reserved */ 161#define IC_INT_MASK_6 0x00000100 162#define IC_INT_MASK_7 0x00000200 163#define IC_INT_MASK_8 0x00000400 164#define IC_INT_MASK_9 0x00000800 165#define IC_INT_TIMR 0x00001000 /* 12 Timer */ 166#define IC_INT_PERF 0x00002000 /* 13 Performance counter */ 167#define IC_INT_TE 0x00000080 /* Timer on INT11 */ 168 169#define ALL_INT_MASK ((IC_INT_MASK << 8) | SR_INT_MASK) 170#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 171#define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK) 172 173 174/* 175 * The bits in the cause register. 176 * 177 * CR_BR_DELAY Exception happened in branch delay slot. 178 * CR_COP_ERR Coprocessor error. 179 * CR_IP Interrupt pending bits defined below. 180 * CR_EXC_CODE The exception type (see exception codes below). 181 */ 182#define CR_BR_DELAY 0x80000000 183#define CR_COP_ERR 0x30000000 184#define CR_EXC_CODE 0x0000007c 185#define CR_EXC_CODE_SHIFT 2 186#define CR_IPEND 0x003fff00 187#define CR_INT_SOFT0 0x00000100 188#define CR_INT_SOFT1 0x00000200 189#define CR_INT_0 0x00000400 190#define CR_INT_1 0x00000800 191#define CR_INT_2 0x00001000 192#define CR_INT_3 0x00002000 193#define CR_INT_4 0x00004000 194#define CR_INT_5 0x00008000 195/* Following on RM7000 */ 196#define CR_INT_6 0x00010000 197#define CR_INT_7 0x00020000 198#define CR_INT_8 0x00040000 199#define CR_INT_9 0x00080000 200#define CR_INT_HARD 0x000ffc00 201#define CR_INT_TIMR 0x00100000 /* 12 Timer */ 202#define CR_INT_PERF 0x00200000 /* 13 Performance counter */ 203 204/* 205 * The bits in the context register. 206 */ 207#define CNTXT_PTE_BASE 0xff800000 208#define CNTXT_BAD_VPN2 0x007ffff0 209 210/* 211 * Location of exception vectors. 212 */ 213#define RESET_EXC_VEC (KSEG0_BASE + 0x3fc00000) 214#define TLB_MISS_EXC_VEC (KSEG0_BASE + 0x00000000) 215#define XTLB_MISS_EXC_VEC (KSEG0_BASE + 0x00000080) 216#define CACHE_ERR_EXC_VEC (KSEG0_BASE + 0x00000100) 217#define GEN_EXC_VEC (KSEG0_BASE + 0x00000180) 218 219/* 220 * Coprocessor 0 registers: 221 */ 222#define COP_0_TLB_INDEX $0 223#define COP_0_TLB_RANDOM $1 224#define COP_0_TLB_LO0 $2 225#define COP_0_TLB_LO1 $3 226#define COP_0_TLB_CONTEXT $4 227#define COP_0_TLB_PG_MASK $5 228#define COP_0_TLB_WIRED $6 229#define COP_0_BAD_VADDR $8 230#define COP_0_COUNT $9 231#define COP_0_TLB_HI $10 232#define COP_0_COMPARE $11 233#define COP_0_STATUS_REG $12 234#define COP_0_CAUSE_REG $13 235#define COP_0_EXC_PC $14 236#define COP_0_PRID $15 237#define COP_0_CONFIG $16 238#define COP_0_LLADDR $17 239#define COP_0_WATCH_LO $18 240#define COP_0_WATCH_HI $19 241#define COP_0_TLB_XCONTEXT $20 242#define COP_0_TLB_FR_MASK $21 /* R10000 onwards */ 243#define COP_0_DIAG $22 /* Loongson 2F */ 244#define COP_0_ECC $26 245#define COP_0_CACHE_ERR $27 246#define COP_0_TAG_LO $28 247#define COP_0_TAG_HI $29 248#define COP_0_ERROR_PC $30 249 250/* 251 * RM7000 specific 252 */ 253#define COP_0_WATCH_1 $18 254#define COP_0_WATCH_2 $19 255#define COP_0_WATCH_M $24 256#define COP_0_PC_COUNT $25 257#define COP_0_PC_CTRL $22 258 259#define COP_0_ICR $20 /* Use cfc0/ctc0 to access */ 260 261/* 262 * Values for the code field in a break instruction. 263 */ 264#define BREAK_INSTR 0x0000000d 265#define BREAK_VAL_MASK 0x03ff0000 266#define BREAK_VAL_SHIFT 16 267#define BREAK_KDB_VAL 512 268#define BREAK_SSTEP_VAL 513 269#define BREAK_BRKPT_VAL 514 270#define BREAK_SOVER_VAL 515 271#define BREAK_DDB_VAL 516 272#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 273#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 274#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 275#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 276#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) 277 278/* 279 * The floating point version and status registers. 280 */ 281#define FPC_ID $0 282#define FPC_CSR $31 283 284/* 285 * The floating point coprocessor status register bits. 286 */ 287#define FPC_ROUNDING_BITS 0x00000003 288#define FPC_ROUND_RN 0x00000000 289#define FPC_ROUND_RZ 0x00000001 290#define FPC_ROUND_RP 0x00000002 291#define FPC_ROUND_RM 0x00000003 292#define FPC_STICKY_BITS 0x0000007c 293#define FPC_STICKY_INEXACT 0x00000004 294#define FPC_STICKY_UNDERFLOW 0x00000008 295#define FPC_STICKY_OVERFLOW 0x00000010 296#define FPC_STICKY_DIV0 0x00000020 297#define FPC_STICKY_INVALID 0x00000040 298#define FPC_ENABLE_BITS 0x00000f80 299#define FPC_ENABLE_INEXACT 0x00000080 300#define FPC_ENABLE_UNDERFLOW 0x00000100 301#define FPC_ENABLE_OVERFLOW 0x00000200 302#define FPC_ENABLE_DIV0 0x00000400 303#define FPC_ENABLE_INVALID 0x00000800 304#define FPC_EXCEPTION_BITS 0x0003f000 305#define FPC_EXCEPTION_INEXACT 0x00001000 306#define FPC_EXCEPTION_UNDERFLOW 0x00002000 307#define FPC_EXCEPTION_OVERFLOW 0x00004000 308#define FPC_EXCEPTION_DIV0 0x00008000 309#define FPC_EXCEPTION_INVALID 0x00010000 310#define FPC_EXCEPTION_UNIMPL 0x00020000 311#define FPC_COND_BIT 0x00800000 312#define FPC_FLUSH_BIT 0x01000000 313#define FPC_MBZ_BITS 0xfe7c0000 314 315/* 316 * Constants to determine if have a floating point instruction. 317 */ 318#define OPCODE_SHIFT 26 319#define OPCODE_C1 0x11 320 321/* 322 * The low part of the TLB entry. 323 */ 324#define VMTLB_PF_NUM 0x3fffffc0 325#define VMTLB_ATTR_MASK 0x00000038 326#define VMTLB_MOD_BIT 0x00000004 327#define VMTLB_VALID_BIT 0x00000002 328#define VMTLB_GLOBAL_BIT 0x00000001 329 330#define VMTLB_PHYS_PAGE_SHIFT 6 331 332/* 333 * The high part of the TLB entry. 334 */ 335#define VMTLB_VIRT_PAGE_NUM 0xffffe000 336#define VMTLB_PID 0x000000ff 337#define VMTLB_PID_SHIFT 0 338#define VMTLB_VIRT_PAGE_SHIFT 12 339 340/* 341 * The number of process id entries. 342 */ 343#define VMNUM_PIDS 256 344 345/* 346 * TLB probe return codes. 347 */ 348#define VMTLB_NOT_FOUND 0 349#define VMTLB_FOUND 1 350#define VMTLB_FOUND_WITH_PATCH 2 351#define VMTLB_PROBE_ERROR 3 352 353/* 354 * Exported definitions unique to mips cpu support. 355 */ 356 357#ifndef _LOCORE 358 359#include <sys/device.h> 360#include <sys/lock.h> 361#include <sys/sched.h> 362 363#include <machine/intr.h> 364 365struct cpu_info { 366 struct device ci_dev; /* our device */ 367 struct cpu_info *ci_self; /* pointer to this structure */ 368 struct cpu_info *ci_next; /* next cpu */ 369 struct proc *ci_curproc; 370 struct user *ci_curprocpaddr; 371 372 struct schedstate_percpu 373 ci_schedstate; 374 int ci_want_resched; /* need_resched() invoked */ 375 cpuid_t ci_cpuid; /* our CPU ID */ 376 uint32_t ci_randseed; /* per cpu random seed */ 377 int ci_ipl; /* software IPL */ 378 uint32_t ci_softpending; /* pending soft interrupts */ 379#ifdef MULTIPROCESSOR 380 u_long ci_flags; /* flags; see below */ 381#endif 382}; 383 384#define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 385#define CPUF_PRESENT 0x02 /* CPU is present */ 386#define CPUF_RUNNING 0x04 /* CPU is running */ 387 388extern struct cpu_info cpu_info_primary; 389extern struct cpu_info *cpu_info_list; 390#define CPU_INFO_ITERATOR int 391#define CPU_INFO_FOREACH(cii, ci) for (cii = 0, ci = cpu_info_list; \ 392 ci != NULL; ci = ci->ci_next) 393 394#define CPU_INFO_UNIT(ci) ((ci)->ci_dev.dv_unit) 395 396#ifdef MULTIPROCESSOR 397#define MAXCPUS 4 398#define curcpu() (cpu_info[cpu_number()]) 399#define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 400#define cpu_number() hw_cpu_number() 401 402extern struct cpuset cpus_running; 403extern struct cpu_info *cpu_info[]; 404void cpu_unidle(struct cpu_info *); 405void cpu_boot_secondary_processors(void); 406#define cpu_boot_secondary(ci) hw_cpu_boot_secondary(ci) 407#define cpu_hatch(ci) hw_cpu_hatch(ci) 408 409#include <sys/mplock.h> 410#else 411#define MAXCPUS 1 412#define curcpu() (&cpu_info_primary) 413#define CPU_IS_PRIMARY(ci) 1 414#define cpu_number() 0 415#define cpu_unidle(ci) 416#endif 417 418#include <machine/frame.h> 419 420#endif /* _LOCORE */ 421 422#ifndef _LOCORE 423 424/* 425 * Arguments to hardclock encapsulate the previous machine state in 426 * an opaque clockframe. 427 */ 428extern int int_nest_cntr; 429#define clockframe trap_frame /* Use normal trap frame */ 430 431#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 432#define CLKF_PC(framep) ((framep)->pc) 433#define CLKF_INTR(framep) (int_nest_cntr > 0) 434 435/* 436 * This is used during profiling to integrate system time. 437 */ 438#define PROC_PC(p) ((p)->p_md.md_regs->pc) 439 440/* 441 * Preempt the current process if in interrupt from user mode, 442 * or after the current trap/syscall if in system mode. 443 */ 444#define need_resched(ci) \ 445 do { \ 446 (ci)->ci_want_resched = 1; \ 447 if ((ci)->ci_curproc != NULL) \ 448 aston((ci)->ci_curproc); \ 449 } while(0) 450#define clear_resched(ci) (ci)->ci_want_resched = 0 451 452/* 453 * Give a profiling tick to the current process when the user profiling 454 * buffer pages are invalid. On the PICA, request an ast to send us 455 * through trap, marking the proc as needing a profiling tick. 456 */ 457#define need_proftick(p) aston(p) 458 459/* 460 * Notify the current process (p) that it has a signal pending, 461 * process as soon as possible. 462 */ 463#define signotify(p) aston(p) 464 465#define aston(p) p->p_md.md_astpending = 1 466 467#endif /* !_LOCORE */ 468#endif /* _KERNEL */ 469 470/* 471 * CTL_MACHDEP definitions. 472 */ 473#define CPU_ALLOWAPERTURE 1 /* allow mmap of /dev/xf86 */ 474#define CPU_KBDRESET 2 /* keyboard reset */ 475#define CPU_MAXID 3 /* number of valid machdep ids */ 476 477#define CTL_MACHDEP_NAMES { \ 478 { 0, 0 }, \ 479 { "allowaperture", CTLTYPE_INT }, \ 480 { "kbdreset", CTLTYPE_INT }, \ 481} 482 483/* 484 * MIPS CPU types (cp_imp). 485 */ 486#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 487#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 488#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 489#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 490#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 491#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 492#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 493#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 494#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 495#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 496#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ 497#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 498#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 499#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 500#define MIPS_R4600 0x20 /* PMCS R4600 Orion ISA III */ 501#define MIPS_R4700 0x21 /* PMCS R4700 Orion ISA III */ 502#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 503#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 504#define MIPS_RM7000 0x27 /* PMCS RM7000 CPU ISA IV */ 505#define MIPS_RM52X0 0x28 /* PMCS RM52X0 CPU ISA IV */ 506#define MIPS_RM9000 0x34 /* PMCS RM9000 CPU ISA IV */ 507#define MIPS_LOONGSON 0x42 /* STC LoongSon CPU ISA III */ 508#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ 509#define MIPS_LOONGSON2 0x63 /* STC LoongSon2 CPU ISA III */ 510 511/* 512 * MIPS FPU types. Only soft, rest is the same as cpu type. 513 */ 514#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 515 516 517#if defined(_KERNEL) && !defined(_LOCORE) 518 519extern u_int CpuPrimaryInstCacheSize; 520extern u_int CpuPrimaryInstCacheLSize; 521extern u_int CpuPrimaryInstSetSize; 522extern u_int CpuPrimaryDataCacheSize; 523extern u_int CpuPrimaryDataCacheLSize; 524extern u_int CpuPrimaryDataSetSize; 525extern u_int CpuCacheAliasMask; 526extern u_int CpuSecondaryCacheSize; 527extern u_int CpuTertiaryCacheSize; 528extern u_int CpuNWayCache; 529extern u_int CpuCacheType; /* R4K, R5K, RM7K */ 530extern u_int CpuConfigRegister; 531extern u_int CpuStatusRegister; 532extern u_int CpuExternalCacheOn; /* R5K, RM7K */ 533extern u_int CpuOnboardCacheOn; /* RM7K */ 534 535struct tlb_entry; 536struct user; 537 538void tlb_set_wired(int); 539void tlb_set_pid(int); 540u_int cp0_get_prid(void); 541u_int cp1_get_prid(void); 542u_int cp0_get_count(void); 543void cp0_set_compare(u_int); 544 545/* 546 * Define soft selected cache functions. 547 */ 548#define Mips_SyncCache() (*(sys_config._SyncCache))() 549#define Mips_InvalidateICache(a, l) \ 550 (*(sys_config._InvalidateICache))((a), (l)) 551#define Mips_SyncDCachePage(a) \ 552 (*(sys_config._SyncDCachePage))((a)) 553#define Mips_HitSyncDCache(a, l) \ 554 (*(sys_config._HitSyncDCache))((a), (l)) 555#define Mips_IOSyncDCache(a, l, h) \ 556 (*(sys_config._IOSyncDCache))((a), (l), (h)) 557#define Mips_HitInvalidateDCache(a, l) \ 558 (*(sys_config._HitInvalidateDCache))((a), (l)) 559 560int Loongson2_ConfigCache(void); 561void Loongson2_SyncCache(void); 562void Loongson2_InvalidateICache(vaddr_t, int); 563void Loongson2_SyncDCachePage(vaddr_t); 564void Loongson2_HitSyncDCache(vaddr_t, int); 565void Loongson2_IOSyncDCache(vaddr_t, int, int); 566void Loongson2_HitInvalidateDCache(vaddr_t, int); 567 568int Mips5k_ConfigCache(void); 569void Mips5k_SyncCache(void); 570void Mips5k_InvalidateICache(vaddr_t, int); 571void Mips5k_SyncDCachePage(vaddr_t); 572void Mips5k_HitSyncDCache(vaddr_t, int); 573void Mips5k_IOSyncDCache(vaddr_t, int, int); 574void Mips5k_HitInvalidateDCache(vaddr_t, int); 575 576int Mips10k_ConfigCache(void); 577void Mips10k_SyncCache(void); 578void Mips10k_InvalidateICache(vaddr_t, int); 579void Mips10k_SyncDCachePage(vaddr_t); 580void Mips10k_HitSyncDCache(vaddr_t, int); 581void Mips10k_IOSyncDCache(vaddr_t, int, int); 582void Mips10k_HitInvalidateDCache(vaddr_t, int); 583 584void tlb_flush(int); 585void tlb_flush_addr(vaddr_t); 586void tlb_write_indexed(int, struct tlb_entry *); 587int tlb_update(vaddr_t, unsigned); 588void tlb_read(int, struct tlb_entry *); 589 590void savectx(struct user *, int); 591void MipsSaveCurFPState(struct proc *); 592void MipsSaveCurFPState16(struct proc *); 593 594int guarded_read_4(paddr_t, uint32_t *); 595int guarded_write_4(paddr_t, uint32_t); 596 597extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */ 598extern u_int32_t cpu_counter_last; /* Last compare value loaded */ 599 600/* 601 * Low level access routines to CPU registers 602 */ 603 604void setsoftintr0(void); 605void clearsoftintr0(void); 606void setsoftintr1(void); 607void clearsoftintr1(void); 608u_int32_t enableintr(void); 609u_int32_t disableintr(void); 610void setsr(u_int32_t); 611u_int32_t getsr(void); 612 613#endif /* _KERNEL */ 614#endif /* !_MIPS_CPU_H_ */ 615