cpu.h revision 1.31
1/* $OpenBSD: cpu.h,v 1.31 2009/05/22 20:37:53 miod Exp $ */ 2 3/*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * Copyright (C) 1989 Digital Equipment Corporation. 35 * Permission to use, copy, modify, and distribute this software and 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 */ 44 45#ifndef _MIPS_CPU_H_ 46#define _MIPS_CPU_H_ 47 48/* 49 * MIPS32-style segment definitions. 50 * They only cover the first 512MB of physical addresses. 51 */ 52#define KSEG0_BASE 0xffffffff80000000 53#define KSEG1_BASE 0xffffffffa0000000 54#define KSSEG_BASE 0xffffffffc0000000 55#define KSEG3_BASE 0xffffffffe0000000 56#define KSEG_SIZE 0x0000000020000000 57 58#define KSEG0_TO_PHYS(x) ((u_long)(x) & (KSEG_SIZE - 1)) 59#define KSEG1_TO_PHYS(x) ((u_long)(x) & (KSEG_SIZE - 1)) 60#define PHYS_TO_KSEG0(x) ((u_long)(x) | KSEG0_BASE) 61#define PHYS_TO_KSEG1(x) ((u_long)(x) | KSEG1_BASE) 62#define PHYS_TO_KSEG3(x) ((u_long)(x) | KSEG3_BASE) 63 64/* 65 * MIPS64-style segment definitions. 66 * These allow for 36 bits of addressable physical memory, thus 64GB. 67 */ 68 69#ifndef _LOCORE 70 71/* 72 * Cache Coherency Attributes. 73 */ 74/* r8k only */ 75#define CCA_NC_COPROCESSOR 0UL /* uncached, coprocessor ordered */ 76/* common to r4, r5k, r8k and r1xk */ 77#define CCA_NC 2UL /* uncached, write-around */ 78#define CCA_NONCOHERENT 3UL /* cached, non-coherent, write-back */ 79/* r8k, r1xk only */ 80#define CCA_COHERENT_EXCL 4UL /* cached, coherent, exclusive */ 81#define CCA_COHERENT_EXCLWRITE 5UL /* cached, coherent, exclusive write */ 82/* r1xk only */ 83#define CCA_NC_ACCELERATED 7UL /* uncached accelerated */ 84/* r4k only */ 85#define CCA_COHERENT_UPDWRITE 6UL /* cached, coherent, update on write */ 86 87#ifdef TGT_COHERENT 88#define CCA_CACHED CCA_COHERENT_EXCLWRITE 89#else 90#define CCA_CACHED CCA_NONCOHERENT 91#endif 92 93/* 94 * Uncached spaces. 95 * R1x000 processors use bits 58:57 of uncached virtual addresses (CCA_NC) 96 * to select different spaces. Unfortunately, other processors need these 97 * bits to be zero, so uncached address have to be decided at runtime. 98 */ 99#define SP_HUB 0UL /* Hub space */ 100#define SP_IO 1UL /* I/O space */ 101#define SP_SPECIAL 2UL /* Memory Special space */ 102#define SP_NC 3UL /* Memory Uncached space */ 103 104extern vaddr_t uncached_base; 105 106#endif /* _LOCORE */ 107 108#define XKPHYS_BASE 0x8000000000000000UL 109#define XKPHYS_TO_PHYS(x) ((paddr_t)(x) & 0x0000000fffffffffUL) 110#define PHYS_TO_XKPHYS(x,c) ((paddr_t)(x) | XKPHYS_BASE | ((c) << 59)) 111#define PHYS_TO_XKPHYS_UNCACHED(x,s) \ 112 (PHYS_TO_XKPHYS(x, CCA_NC) | ((s) << 57)) 113#define PHYS_TO_UNCACHED(x) ((paddr_t)(x) | uncached_base) 114#define IS_XKPHYS(va) (((va) >> 62) == 2) 115#define XKPHYS_TO_CCA(x) (((x) >> 59) & 0x07) 116#define XKPHYS_TO_SP(x) (((x) >> 57) & 0x03) 117 118#ifdef _KERNEL 119 120/* 121 * Status register. 122 */ 123#define SR_XX 0x80000000 124#define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */ 125#define SR_COP_0_BIT 0x10000000 126#define SR_COP_1_BIT 0x20000000 127#define SR_RP 0x08000000 128#define SR_FR_32 0x04000000 129#define SR_RE 0x02000000 130#define SR_DSD 0x01000000 /* Only on R12000 */ 131#define SR_BOOT_EXC_VEC 0x00400000 132#define SR_TLB_SHUTDOWN 0x00200000 133#define SR_SOFT_RESET 0x00100000 134#define SR_DIAG_CH 0x00040000 135#define SR_DIAG_CE 0x00020000 136#define SR_DIAG_DE 0x00010000 137#define SR_KX 0x00000080 138#define SR_SX 0x00000040 139#define SR_UX 0x00000020 140#define SR_KSU_MASK 0x00000018 141#define SR_KSU_USER 0x00000010 142#define SR_KSU_SUPER 0x00000008 143#define SR_KSU_KERNEL 0x00000000 144#define SR_ERL 0x00000004 145#define SR_EXL 0x00000002 146#define SR_INT_ENAB 0x00000001 147 148#define SR_INT_MASK 0x0000ff00 149#define SOFT_INT_MASK_0 0x00000100 150#define SOFT_INT_MASK_1 0x00000200 151#define SR_INT_MASK_0 0x00000400 152#define SR_INT_MASK_1 0x00000800 153#define SR_INT_MASK_2 0x00001000 154#define SR_INT_MASK_3 0x00002000 155#define SR_INT_MASK_4 0x00004000 156#define SR_INT_MASK_5 0x00008000 157/* 158 * Interrupt control register in RM7000. Expansion of interrupts. 159 */ 160#define IC_INT_MASK 0x00003f00 /* Two msb reserved */ 161#define IC_INT_MASK_6 0x00000100 162#define IC_INT_MASK_7 0x00000200 163#define IC_INT_MASK_8 0x00000400 164#define IC_INT_MASK_9 0x00000800 165#define IC_INT_TIMR 0x00001000 /* 12 Timer */ 166#define IC_INT_PERF 0x00002000 /* 13 Performance counter */ 167#define IC_INT_TE 0x00000080 /* Timer on INT11 */ 168 169#define ALL_INT_MASK ((IC_INT_MASK << 8) | SR_INT_MASK) 170#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 171#define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK) 172 173 174/* 175 * The bits in the cause register. 176 * 177 * CR_BR_DELAY Exception happened in branch delay slot. 178 * CR_COP_ERR Coprocessor error. 179 * CR_IP Interrupt pending bits defined below. 180 * CR_EXC_CODE The exception type (see exception codes below). 181 */ 182#define CR_BR_DELAY 0x80000000 183#define CR_COP_ERR 0x30000000 184#define CR_EXC_CODE 0x0000007c 185#define CR_EXC_CODE_SHIFT 2 186#define CR_IPEND 0x003fff00 187#define CR_INT_SOFT0 0x00000100 188#define CR_INT_SOFT1 0x00000200 189#define CR_INT_0 0x00000400 190#define CR_INT_1 0x00000800 191#define CR_INT_2 0x00001000 192#define CR_INT_3 0x00002000 193#define CR_INT_4 0x00004000 194#define CR_INT_5 0x00008000 195/* Following on RM7000 */ 196#define CR_INT_6 0x00010000 197#define CR_INT_7 0x00020000 198#define CR_INT_8 0x00040000 199#define CR_INT_9 0x00080000 200#define CR_INT_HARD 0x000ffc00 201#define CR_INT_TIMR 0x00100000 /* 12 Timer */ 202#define CR_INT_PERF 0x00200000 /* 13 Performance counter */ 203 204/* 205 * The bits in the context register. 206 */ 207#define CNTXT_PTE_BASE 0xff800000 208#define CNTXT_BAD_VPN2 0x007ffff0 209 210/* 211 * Location of exception vectors. 212 */ 213#define RESET_EXC_VEC (KSEG0_BASE + 0x3fc00000) 214#define TLB_MISS_EXC_VEC (KSEG0_BASE + 0x00000000) 215#define XTLB_MISS_EXC_VEC (KSEG0_BASE + 0x00000080) 216#define CACHE_ERR_EXC_VEC (KSEG0_BASE + 0x00000100) 217#define GEN_EXC_VEC (KSEG0_BASE + 0x00000180) 218 219/* 220 * Coprocessor 0 registers: 221 */ 222#define COP_0_TLB_INDEX $0 223#define COP_0_TLB_RANDOM $1 224#define COP_0_TLB_LO0 $2 225#define COP_0_TLB_LO1 $3 226#define COP_0_TLB_CONTEXT $4 227#define COP_0_TLB_PG_MASK $5 228#define COP_0_TLB_WIRED $6 229#define COP_0_BAD_VADDR $8 230#define COP_0_COUNT $9 231#define COP_0_TLB_HI $10 232#define COP_0_COMPARE $11 233#define COP_0_STATUS_REG $12 234#define COP_0_CAUSE_REG $13 235#define COP_0_EXC_PC $14 236#define COP_0_PRID $15 237#define COP_0_CONFIG $16 238#define COP_0_LLADDR $17 239#define COP_0_WATCH_LO $18 240#define COP_0_WATCH_HI $19 241#define COP_0_TLB_XCONTEXT $20 242#define COP_0_ECC $26 243#define COP_0_CACHE_ERR $27 244#define COP_0_TAG_LO $28 245#define COP_0_TAG_HI $29 246#define COP_0_ERROR_PC $30 247 248/* 249 * RM7000 specific 250 */ 251#define COP_0_WATCH_1 $18 252#define COP_0_WATCH_2 $19 253#define COP_0_WATCH_M $24 254#define COP_0_PC_COUNT $25 255#define COP_0_PC_CTRL $22 256 257#define COP_0_ICR $20 /* Use cfc0/ctc0 to access */ 258 259/* 260 * Values for the code field in a break instruction. 261 */ 262#define BREAK_INSTR 0x0000000d 263#define BREAK_VAL_MASK 0x03ff0000 264#define BREAK_VAL_SHIFT 16 265#define BREAK_KDB_VAL 512 266#define BREAK_SSTEP_VAL 513 267#define BREAK_BRKPT_VAL 514 268#define BREAK_SOVER_VAL 515 269#define BREAK_DDB_VAL 516 270#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 271#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 272#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 273#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 274#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) 275 276/* 277 * Mininum and maximum cache sizes. 278 */ 279#define MIN_CACHE_SIZE (16 * 1024) 280#define MAX_CACHE_SIZE (256 * 1024) 281 282/* 283 * The floating point version and status registers. 284 */ 285#define FPC_ID $0 286#define FPC_CSR $31 287 288/* 289 * The floating point coprocessor status register bits. 290 */ 291#define FPC_ROUNDING_BITS 0x00000003 292#define FPC_ROUND_RN 0x00000000 293#define FPC_ROUND_RZ 0x00000001 294#define FPC_ROUND_RP 0x00000002 295#define FPC_ROUND_RM 0x00000003 296#define FPC_STICKY_BITS 0x0000007c 297#define FPC_STICKY_INEXACT 0x00000004 298#define FPC_STICKY_UNDERFLOW 0x00000008 299#define FPC_STICKY_OVERFLOW 0x00000010 300#define FPC_STICKY_DIV0 0x00000020 301#define FPC_STICKY_INVALID 0x00000040 302#define FPC_ENABLE_BITS 0x00000f80 303#define FPC_ENABLE_INEXACT 0x00000080 304#define FPC_ENABLE_UNDERFLOW 0x00000100 305#define FPC_ENABLE_OVERFLOW 0x00000200 306#define FPC_ENABLE_DIV0 0x00000400 307#define FPC_ENABLE_INVALID 0x00000800 308#define FPC_EXCEPTION_BITS 0x0003f000 309#define FPC_EXCEPTION_INEXACT 0x00001000 310#define FPC_EXCEPTION_UNDERFLOW 0x00002000 311#define FPC_EXCEPTION_OVERFLOW 0x00004000 312#define FPC_EXCEPTION_DIV0 0x00008000 313#define FPC_EXCEPTION_INVALID 0x00010000 314#define FPC_EXCEPTION_UNIMPL 0x00020000 315#define FPC_COND_BIT 0x00800000 316#define FPC_FLUSH_BIT 0x01000000 317#define FPC_MBZ_BITS 0xfe7c0000 318 319/* 320 * Constants to determine if have a floating point instruction. 321 */ 322#define OPCODE_SHIFT 26 323#define OPCODE_C1 0x11 324 325/* 326 * The low part of the TLB entry. 327 */ 328#define VMTLB_PF_NUM 0x3fffffc0 329#define VMTLB_ATTR_MASK 0x00000038 330#define VMTLB_MOD_BIT 0x00000004 331#define VMTLB_VALID_BIT 0x00000002 332#define VMTLB_GLOBAL_BIT 0x00000001 333 334#define VMTLB_PHYS_PAGE_SHIFT 6 335 336/* 337 * The high part of the TLB entry. 338 */ 339#define VMTLB_VIRT_PAGE_NUM 0xffffe000 340#define VMTLB_PID 0x000000ff 341#define VMTLB_PID_SHIFT 0 342#define VMTLB_VIRT_PAGE_SHIFT 12 343 344/* 345 * The number of process id entries. 346 */ 347#define VMNUM_PIDS 256 348 349/* 350 * TLB probe return codes. 351 */ 352#define VMTLB_NOT_FOUND 0 353#define VMTLB_FOUND 1 354#define VMTLB_FOUND_WITH_PATCH 2 355#define VMTLB_PROBE_ERROR 3 356 357/* 358 * Exported definitions unique to mips cpu support. 359 */ 360 361#ifndef _LOCORE 362 363#include <sys/sched.h> 364 365struct cpu_info { 366 struct schedstate_percpu ci_schedstate; 367 368 struct proc *ci_curproc; 369 u_int32_t ci_randseed; 370}; 371 372extern struct cpu_info cpu_info_primary; 373 374#define curcpu() (&cpu_info_primary) 375 376#define CPU_IS_PRIMARY(ci) 1 377#define CPU_INFO_ITERATOR int 378#define CPU_INFO_FOREACH(cii, ci) \ 379 for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL) 380#define CPU_INFO_UNIT(ci) 0 381#define MAXCPUS 1 382#define cpu_unidle(ci) 383 384#define cpu_number() 0 385 386#include <machine/frame.h> 387#include <machine/intr.h> 388 389/* 390 * Arguments to hardclock and gatherstats encapsulate the previous 391 * machine state in an opaque clockframe. 392 */ 393extern int int_nest_cntr; 394#define clockframe trap_frame /* Use normal trap frame */ 395 396#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 397#define CLKF_PC(framep) ((framep)->pc) 398#define CLKF_INTR(framep) (int_nest_cntr > 0) 399 400/* 401 * This is used during profiling to integrate system time. 402 */ 403#define PROC_PC(p) ((p)->p_md.md_regs->pc) 404 405/* 406 * Preempt the current process if in interrupt from user mode, 407 * or after the current trap/syscall if in system mode. 408 */ 409#define need_resched(info) { want_resched = 1; aston(); } 410#define clear_resched(ci) want_resched = 0 411 412/* 413 * Give a profiling tick to the current process when the user profiling 414 * buffer pages are invalid. On the PICA, request an ast to send us 415 * through trap, marking the proc as needing a profiling tick. 416 */ 417#define need_proftick(p) aston() 418 419/* 420 * Notify the current process (p) that it has a signal pending, 421 * process as soon as possible. 422 */ 423#define signotify(p) aston() 424 425#define aston() (astpending = 1) 426 427extern int want_resched; /* resched() was called */ 428 429#endif /* !_LOCORE */ 430#endif /* _KERNEL */ 431 432/* 433 * CTL_MACHDEP definitions. 434 */ 435#define CPU_ALLOWAPERTURE 1 /* allow mmap of /dev/xf86 */ 436#define CPU_KBDRESET 2 /* keyboard reset */ 437#define CPU_MAXID 3 /* number of valid machdep ids */ 438 439#define CTL_MACHDEP_NAMES { \ 440 { 0, 0 }, \ 441 { "allowaperture", CTLTYPE_INT }, \ 442 { "kbdreset", CTLTYPE_INT }, \ 443} 444 445/* 446 * MIPS CPU types (cp_imp). 447 */ 448#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 449#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 450#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 451#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 452#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 453#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 454#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 455#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 456#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 457#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 458#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ 459#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 460#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 461#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 462#define MIPS_R4600 0x20 /* PMCS R4600 Orion ISA III */ 463#define MIPS_R4700 0x21 /* PMCS R4700 Orion ISA III */ 464#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 465#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 466#define MIPS_RM7000 0x27 /* PMCS RM7000 CPU ISA IV */ 467#define MIPS_RM52X0 0x28 /* PMCS RM52X0 CPU ISA IV */ 468#define MIPS_RM9000 0x34 /* PMCS RM9000 CPU ISA IV */ 469#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ 470 471/* 472 * MIPS FPU types. Only soft, rest is the same as cpu type. 473 */ 474#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 475 476 477#if defined(_KERNEL) && !defined(_LOCORE) 478 479extern u_int CpuPrimaryInstCacheSize; 480extern u_int CpuPrimaryInstCacheLSize; 481extern u_int CpuPrimaryInstSetSize; 482extern u_int CpuPrimaryDataCacheSize; 483extern u_int CpuPrimaryDataCacheLSize; 484extern u_int CpuPrimaryDataSetSize; 485extern u_int CpuCacheAliasMask; 486extern u_int CpuSecondaryCacheSize; 487extern u_int CpuTertiaryCacheSize; 488extern u_int CpuNWayCache; 489extern u_int CpuCacheType; /* R4K, R5K, RM7K */ 490extern u_int CpuConfigRegister; 491extern u_int CpuStatusRegister; 492extern u_int CpuExternalCacheOn; /* R5K, RM7K */ 493extern u_int CpuOnboardCacheOn; /* RM7K */ 494 495struct tlb_entry; 496struct user; 497 498void tlb_set_wired(int); 499void tlb_set_pid(int); 500u_int cp0_get_prid(void); 501u_int cp1_get_prid(void); 502u_int cp0_get_count(void); 503void cp0_set_compare(u_int); 504 505/* 506 * Define soft selected cache functions. 507 */ 508#define Mips_SyncCache() (*(sys_config._SyncCache))() 509#define Mips_InvalidateICache(a, l) \ 510 (*(sys_config._InvalidateICache))((a), (l)) 511#define Mips_InvalidateICachePage(a) \ 512 (*(sys_config._InvalidateICachePage))((a)) 513#define Mips_SyncDCachePage(a) \ 514 (*(sys_config._SyncDCachePage))((a)) 515#define Mips_HitSyncDCache(a, l) \ 516 (*(sys_config._HitSyncDCache))((a), (l)) 517#define Mips_IOSyncDCache(a, l, h) \ 518 (*(sys_config._IOSyncDCache))((a), (l), (h)) 519#define Mips_HitInvalidateDCache(a, l) \ 520 (*(sys_config._HitInvalidateDCache))((a), (l)) 521 522int Mips5k_ConfigCache(void); 523void Mips5k_SyncCache(void); 524void Mips5k_InvalidateICache(vaddr_t, int); 525void Mips5k_InvalidateICachePage(vaddr_t); 526void Mips5k_SyncDCachePage(vaddr_t); 527void Mips5k_HitSyncDCache(vaddr_t, int); 528void Mips5k_IOSyncDCache(vaddr_t, int, int); 529void Mips5k_HitInvalidateDCache(vaddr_t, int); 530 531int Mips10k_ConfigCache(void); 532void Mips10k_SyncCache(void); 533void Mips10k_InvalidateICache(vaddr_t, int); 534void Mips10k_InvalidateICachePage(vaddr_t); 535void Mips10k_SyncDCachePage(vaddr_t); 536void Mips10k_HitSyncDCache(vaddr_t, int); 537void Mips10k_IOSyncDCache(vaddr_t, int, int); 538void Mips10k_HitInvalidateDCache(vaddr_t, int); 539 540void tlb_flush(int); 541void tlb_flush_addr(vaddr_t); 542void tlb_write_indexed(int, struct tlb_entry *); 543int tlb_update(vaddr_t, unsigned); 544void tlb_read(int, struct tlb_entry *); 545 546void savectx(struct user *, int); 547void MipsSaveCurFPState(struct proc *); 548void MipsSaveCurFPState16(struct proc *); 549 550int guarded_read_4(paddr_t, uint32_t *); 551int guarded_write_4(paddr_t, uint32_t); 552 553extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */ 554extern u_int32_t cpu_counter_last; /* Last compare value loaded */ 555 556/* 557 * Low level access routines to CPU registers 558 */ 559 560void setsoftintr0(void); 561void clearsoftintr0(void); 562void setsoftintr1(void); 563void clearsoftintr1(void); 564u_int32_t enableintr(void); 565u_int32_t disableintr(void); 566void setsr(u_int32_t); 567u_int32_t getsr(void); 568 569#endif /* _KERNEL */ 570#endif /* !_MIPS_CPU_H_ */ 571