cpu.h revision 1.1
1/* $OpenBSD: cpu.h,v 1.1 2004/08/06 20:56:01 pefo Exp $ */ 2 3/*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * Copyright (C) 1989 Digital Equipment Corporation. 39 * Permission to use, copy, modify, and distribute this software and 40 * its documentation for any purpose and without fee is hereby granted, 41 * provided that the above copyright notice appears in all copies. 42 * Digital Equipment Corporation makes no representations about the 43 * suitability of this software for any purpose. It is provided "as is" 44 * without express or implied warranty. 45 * 46 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 47 */ 48 49#ifndef _MIPS_CPU_H_ 50#define _MIPS_CPU_H_ 51 52#include <machine/psl.h> 53 54#if defined(_LP64) 55#define KSEG0_BASE 0xffffffff80000000 56#define KSEG1_BASE 0xffffffffa0000000 57#define KSSEG_BASE 0xffffffffc0000000 58#define KSEG3_BASE 0xffffffffe0000000 59#else 60#define KSEG0_BASE 0x80000000 61#define KSEG1_BASE 0xa0000000 62#define KSSEG_BASE 0xc0000000 63#define KSEG3_BASE 0xe0000000 64#endif 65#define KSEG_SIZE 0x20000000 66 67#define KSEG0_TO_PHYS(x) ((u_long)(x) & 0x1fffffff) 68#define KSEG1_TO_PHYS(x) ((u_long)(x) & 0x1fffffff) 69#define PHYS_TO_KSEG0(x) ((u_long)(x) | KSEG0_BASE) 70#define PHYS_TO_KSEG1(x) ((u_long)(x) | KSEG1_BASE) 71#define PHYS_TO_KSEG3(x) ((u_long)(x) | KSEG3_BASE) 72 73#ifdef _KERNEL 74 75/* 76 * Status register. 77 */ 78#define SR_XX 0x80000000 79#define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */ 80#define SR_COP_0_BIT 0x10000000 81#define SR_COP_1_BIT 0x20000000 82#define SR_RP 0x08000000 83#define SR_FR_32 0x04000000 84#define SR_RE 0x02000000 85#define SR_BOOT_EXC_VEC 0x00400000 86#define SR_TLB_SHUTDOWN 0x00200000 87#define SR_SOFT_RESET 0x00100000 88#define SR_DIAG_CH 0x00040000 89#define SR_DIAG_CE 0x00020000 90#define SR_DIAG_DE 0x00010000 91#define SR_KX 0x00000080 92#define SR_SX 0x00000040 93#define SR_UX 0x00000020 94#define SR_KSU_MASK 0x00000018 95#define SR_KSU_USER 0x00000010 96#define SR_KSU_SUPER 0x00000008 97#define SR_KSU_KERNEL 0x00000000 98#define SR_ERL 0x00000004 99#define SR_EXL 0x00000002 100#define SR_INT_ENAB 0x00000001 101 102#define SR_INT_MASK 0x0000ff00 103#define SOFT_INT_MASK_0 0x00000100 104#define SOFT_INT_MASK_1 0x00000200 105#define SR_INT_MASK_0 0x00000400 106#define SR_INT_MASK_1 0x00000800 107#define SR_INT_MASK_2 0x00001000 108#define SR_INT_MASK_3 0x00002000 109#define SR_INT_MASK_4 0x00004000 110#define SR_INT_MASK_5 0x00008000 111/* 112 * Interrupt control register in RM7000. Expansion of interrupts. 113 */ 114#define IC_INT_MASK 0x00003f00 /* Two msb reserved */ 115#define IC_INT_MASK_6 0x00000100 116#define IC_INT_MASK_7 0x00000200 117#define IC_INT_MASK_8 0x00000400 118#define IC_INT_MASK_9 0x00000800 119#define IC_INT_TIMR 0x00001000 /* 12 Timer */ 120#define IC_INT_PERF 0x00002000 /* 13 Performance counter */ 121#define IC_INT_TE 0x00000080 /* Timer on INT11 */ 122 123#define ALL_INT_MASK ((IC_INT_MASK << 8) | SR_INT_MASK) 124#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 125#define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK) 126 127 128/* 129 * The bits in the cause register. 130 * 131 * CR_BR_DELAY Exception happened in branch delay slot. 132 * CR_COP_ERR Coprocessor error. 133 * CR_IP Interrupt pending bits defined below. 134 * CR_EXC_CODE The exception type (see exception codes below). 135 */ 136#define CR_BR_DELAY 0x80000000 137#define CR_COP_ERR 0x30000000 138#define CR_EXC_CODE 0x0000007c 139#define CR_EXC_CODE_SHIFT 2 140#define CR_IPEND 0x003fff00 141#define CR_INT_SOFT0 0x00000100 142#define CR_INT_SOFT1 0x00000200 143#define CR_INT_0 0x00000400 144#define CR_INT_1 0x00000800 145#define CR_INT_2 0x00001000 146#define CR_INT_3 0x00002000 147#define CR_INT_4 0x00004000 148#define CR_INT_5 0x00008000 149/* Following on RM7000 */ 150#define CR_INT_6 0x00010000 151#define CR_INT_7 0x00020000 152#define CR_INT_8 0x00040000 153#define CR_INT_9 0x00080000 154#define CR_INT_HARD 0x000ffc00 155#define CR_INT_TIMR 0x00100000 /* 12 Timer */ 156#define CR_INT_PERF 0x00200000 /* 13 Performance counter */ 157 158/* 159 * The bits in the context register. 160 */ 161#define CNTXT_PTE_BASE 0xff800000 162#define CNTXT_BAD_VPN2 0x007ffff0 163 164/* 165 * Location of exception vectors. 166 */ 167#define RESET_EXC_VEC 0xffffffffbfc00000 168#define TLB_MISS_EXC_VEC 0xffffffff80000000 169#define XTLB_MISS_EXC_VEC 0xffffffff80000080 170#define CACHE_ERR_EXC_VEC 0xffffffff80000100 171#define GEN_EXC_VEC 0xffffffff80000180 172 173/* 174 * Coprocessor 0 registers: 175 */ 176#define COP_0_TLB_INDEX $0 177#define COP_0_TLB_RANDOM $1 178#define COP_0_TLB_LO0 $2 179#define COP_0_TLB_LO1 $3 180#define COP_0_TLB_CONTEXT $4 181#define COP_0_TLB_PG_MASK $5 182#define COP_0_TLB_WIRED $6 183#define COP_0_BAD_VADDR $8 184#define COP_0_COUNT $9 185#define COP_0_TLB_HI $10 186#define COP_0_COMPARE $11 187#define COP_0_STATUS_REG $12 188#define COP_0_CAUSE_REG $13 189#define COP_0_EXC_PC $14 190#define COP_0_PRID $15 191#define COP_0_CONFIG $16 192#define COP_0_LLADDR $17 193#define COP_0_WATCH_LO $18 194#define COP_0_WATCH_HI $19 195#define COP_0_TLB_XCONTEXT $20 196#define COP_0_ECC $26 197#define COP_0_CACHE_ERR $27 198#define COP_0_TAG_LO $28 199#define COP_0_TAG_HI $29 200#define COP_0_ERROR_PC $30 201 202/* 203 * RM7000 specific 204 */ 205#define COP_0_WATCH_1 $18 206#define COP_0_WATCH_2 $19 207#define COP_0_WATCH_M $24 208#define COP_0_PC_COUNT $25 209#define COP_0_PC_CTRL $22 210 211#define COP_0_ICR $20 /* Use cfc0/ctc0 to access */ 212 213/* 214 * Values for the code field in a break instruction. 215 */ 216#define BREAK_INSTR 0x0000000d 217#define BREAK_VAL_MASK 0x03ff0000 218#define BREAK_VAL_SHIFT 16 219#define BREAK_KDB_VAL 512 220#define BREAK_SSTEP_VAL 513 221#define BREAK_BRKPT_VAL 514 222#define BREAK_SOVER_VAL 515 223#define BREAK_DDB_VAL 516 224#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 225#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 226#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 227#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 228#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) 229 230/* 231 * Mininum and maximum cache sizes. 232 */ 233#define MIN_CACHE_SIZE (16 * 1024) 234#define MAX_CACHE_SIZE (256 * 1024) 235 236/* 237 * The floating point version and status registers. 238 */ 239#define FPC_ID $0 240#define FPC_CSR $31 241 242/* 243 * The floating point coprocessor status register bits. 244 */ 245#define FPC_ROUNDING_BITS 0x00000003 246#define FPC_ROUND_RN 0x00000000 247#define FPC_ROUND_RZ 0x00000001 248#define FPC_ROUND_RP 0x00000002 249#define FPC_ROUND_RM 0x00000003 250#define FPC_STICKY_BITS 0x0000007c 251#define FPC_STICKY_INEXACT 0x00000004 252#define FPC_STICKY_UNDERFLOW 0x00000008 253#define FPC_STICKY_OVERFLOW 0x00000010 254#define FPC_STICKY_DIV0 0x00000020 255#define FPC_STICKY_INVALID 0x00000040 256#define FPC_ENABLE_BITS 0x00000f80 257#define FPC_ENABLE_INEXACT 0x00000080 258#define FPC_ENABLE_UNDERFLOW 0x00000100 259#define FPC_ENABLE_OVERFLOW 0x00000200 260#define FPC_ENABLE_DIV0 0x00000400 261#define FPC_ENABLE_INVALID 0x00000800 262#define FPC_EXCEPTION_BITS 0x0003f000 263#define FPC_EXCEPTION_INEXACT 0x00001000 264#define FPC_EXCEPTION_UNDERFLOW 0x00002000 265#define FPC_EXCEPTION_OVERFLOW 0x00004000 266#define FPC_EXCEPTION_DIV0 0x00008000 267#define FPC_EXCEPTION_INVALID 0x00010000 268#define FPC_EXCEPTION_UNIMPL 0x00020000 269#define FPC_COND_BIT 0x00800000 270#define FPC_FLUSH_BIT 0x01000000 271#define FPC_MBZ_BITS 0xfe7c0000 272 273/* 274 * Constants to determine if have a floating point instruction. 275 */ 276#define OPCODE_SHIFT 26 277#define OPCODE_C1 0x11 278 279/* 280 * The low part of the TLB entry. 281 */ 282#define VMTLB_PF_NUM 0x3fffffc0 283#define VMTLB_ATTR_MASK 0x00000038 284#define VMTLB_MOD_BIT 0x00000004 285#define VMTLB_VALID_BIT 0x00000002 286#define VMTLB_GLOBAL_BIT 0x00000001 287 288#define VMTLB_PHYS_PAGE_SHIFT 6 289 290/* 291 * The high part of the TLB entry. 292 */ 293#define VMTLB_VIRT_PAGE_NUM 0xffffe000 294#define VMTLB_PID 0x000000ff 295#define VMTLB_PID_SHIFT 0 296#define VMTLB_VIRT_PAGE_SHIFT 12 297 298/* 299 * The number of process id entries. 300 */ 301#define VMNUM_PIDS 256 302 303/* 304 * TLB probe return codes. 305 */ 306#define VMTLB_NOT_FOUND 0 307#define VMTLB_FOUND 1 308#define VMTLB_FOUND_WITH_PATCH 2 309#define VMTLB_PROBE_ERROR 3 310 311/* 312 * Exported definitions unique to mips cpu support. 313 */ 314 315/* 316 * definitions of cpu-dependent requirements 317 * referenced in generic code 318 */ 319#define COPY_SIGCODE /* copy sigcode above user stack in exec */ 320 321#define cpu_wait(p) /* nothing */ 322#define cpu_swapout(p) panic("cpu_swapout: can't get here"); 323 324#ifndef _LOCORE 325#include <machine/frame.h> 326/* 327 * Arguments to hardclock and gatherstats encapsulate the previous 328 * machine state in an opaque clockframe. 329 */ 330#define clockframe trap_frame /* Use normal trap frame */ 331 332#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 333#define CLKF_BASEPRI(framep) ((framep)->cpl == 0) 334#define CLKF_PC(framep) ((framep)->pc) 335#define CLKF_INTR(framep) (0) 336 337/* 338 * Preempt the current process if in interrupt from user mode, 339 * or after the current trap/syscall if in system mode. 340 */ 341#define need_resched(info) { want_resched = 1; aston(); } 342 343/* 344 * Give a profiling tick to the current process when the user profiling 345 * buffer pages are invalid. On the PICA, request an ast to send us 346 * through trap, marking the proc as needing a profiling tick. 347 */ 348#define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); } 349 350/* 351 * Notify the current process (p) that it has a signal pending, 352 * process as soon as possible. 353 */ 354#define signotify(p) aston() 355 356#define aston() (astpending = 1) 357 358int want_resched; /* resched() was called */ 359 360/* 361 * CPU identification, from PRID register. 362 */ 363union cpuprid { 364 int cpuprid; 365 struct { 366#if BYTE_ORDER == BIG_ENDIAN 367 u_int pad1:16; /* reserved */ 368 u_int cp_imp:8; /* implementation identifier */ 369 u_int cp_majrev:4; /* major revision identifier */ 370 u_int cp_minrev:4; /* minor revision identifier */ 371#else 372 u_int cp_minrev:4; /* minor revision identifier */ 373 u_int cp_majrev:4; /* major revision identifier */ 374 u_int cp_imp:8; /* implementation identifier */ 375 u_int pad1:16; /* reserved */ 376#endif 377 } cpu; 378}; 379#endif /* !_LOCORE */ 380#endif /* _KERNEL */ 381 382/* 383 * CTL_MACHDEP definitions. 384 */ 385#define CPU_ALLOWAPERTURE 1 /* allow mmap of /dev/xf86 */ 386#define CPU_MAXID 2 /* number of valid machdep ids */ 387 388#define CTL_MACHDEP_NAMES { \ 389 { 0, 0 }, \ 390 { "allowaperture", CTLTYPE_INT }, \ 391} 392 393/* 394 * MIPS CPU types (cp_imp). 395 */ 396#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 397#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 398#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 399#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 400#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 401#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 402#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 403#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 404#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 405#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 406#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ 407#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 408#define MIPS_R4600 0x20 /* PMCS R4600 Orion ISA III */ 409#define MIPS_R4700 0x21 /* PMCS R4700 Orion ISA III */ 410#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 411#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 412#define MIPS_RM7000 0x27 /* PMCS RM7000 CPU ISA IV */ 413#define MIPS_RM52X0 0x28 /* PMCS RM52X0 CPU ISA IV */ 414#define MIPS_RM9000 0x34 /* PMCS RM9000 CPU ISA IV */ 415#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ 416 417/* 418 * MIPS FPU types 419 */ 420#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 421#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 422#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 423#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 424#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 425#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */ 426#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 427#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ 428#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */ 429#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */ 430#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 431#define MIPS_R4600 0x20 /* PMCS R4600 Orion ISA III */ 432#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */ 433#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 434#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */ 435#define MIPS_RM7000 0x27 /* PMCS RM7000 FPU ISA IV */ 436#define MIPS_RM5230 0x28 /* PMCS RM52X0 based FPU ISA IV */ 437#define MIPS_RM52XX 0x28 /* PMCS RM52X0 based FPU ISA IV */ 438#define MIPS_RM9000 0x34 /* PMCS RM9000 based FPU ISA IV */ 439#define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+ */ 440 441#if defined(_KERNEL) && !defined(_LOCORE) 442union cpuprid cpu_id; 443union cpuprid fpu_id; 444 445u_int CpuPrimaryInstCacheSize; 446u_int CpuPrimaryInstCacheLSize; 447u_int CpuPrimaryInstSetSize; 448u_int CpuPrimaryDataCacheSize; 449u_int CpuPrimaryDataCacheLSize; 450u_int CpuPrimaryDataSetSize; 451u_int CpuCacheAliasMask; 452u_int CpuSecondaryCacheSize; 453u_int CpuTertiaryCacheSize; 454u_int CpuNWayCache; 455u_int CpuCacheType; /* R4K, R5K, RM7K */ 456u_int CpuConfigRegister; 457u_int CpuStatusRegister; 458u_int CpuExternalCacheOn; /* R5K, RM7K */ 459u_int CpuOnboardCacheOn; /* RM7K */ 460 461struct tlb; 462struct user; 463 464void tlb_set_wired(int); 465void tlb_set_pid(int); 466u_int cp0_get_count(void); 467void cp0_set_compare(u_int); 468 469/* 470 * Defines temporary until soft selected cache functions fixed. 471 */ 472#define Mips_ConfigCache Mips5k_ConfigCache 473#define Mips_SyncCache Mips5k_SyncCache 474#define Mips_InvalidateICache Mips5k_InvalidateICache 475#define Mips_InvalidateICachePage Mips5k_InvalidateICachePage 476#define Mips_SyncDCachePage Mips5k_SyncDCachePage 477#define Mips_HitSyncDCache Mips5k_HitSyncDCache 478#define Mips_IOSyncDCache Mips5k_IOSyncDCache 479#define Mips_HitInvalidateDCache Mips5k_HitInvalidateDCache 480 481int Mips5k_ConfigCache(void); 482void Mips5k_SyncCache(void); 483void Mips5k_InvalidateICache(vaddr_t, int); 484void Mips5k_InvalidateICachePage(vaddr_t); 485void Mips5k_SyncDCachePage(vaddr_t); 486void Mips5k_HitSyncDCache(vaddr_t, int); 487void Mips5k_IOSyncDCache(vaddr_t, int, int); 488void Mips5k_HitInvalidateDCache(vaddr_t, int); 489 490void tlb_flush(int); 491void tlb_flush_addr(vaddr_t); 492void tlb_write_indexed(int, struct tlb *); 493int tlb_update(vaddr_t, unsigned); 494void tlb_read(int, struct tlb *); 495 496void wbflush(void); 497void savectx(struct user *, int); 498int copykstack(struct user *); 499void switch_exit(struct proc *); 500void MipsSaveCurFPState(struct proc *); 501void MipsSaveCurFPState16(struct proc *); 502 503extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */ 504extern u_int32_t cpu_counter_last; /* Last compare value loaded */ 505 506/* 507 * Enable realtime clock (always enabled). 508 */ 509#define enablertclock() 510 511/* 512 * Low level access routines to CPU registers 513 */ 514 515void setsoftintr0(void); 516void clearsoftintr0(void); 517void setsoftintr1(void); 518void clearsoftintr1(void); 519u_int32_t enableintr(void); 520u_int32_t disableintr(void); 521u_int32_t updateimask(intrmask_t); 522void setsr(u_int32_t); 523 524#endif /* _KERNEL */ 525#endif /* !_MIPS_CPU_H_ */ 526