machdep.c revision 1.44
1/* $OpenBSD: machdep.c,v 1.44 2016/10/09 11:25:39 tom Exp $ */ 2/* $NetBSD: machdep.c,v 1.1 2006/09/01 21:26:18 uwe Exp $ */ 3 4/*- 5 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 10 * Simulation Facility, NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34/*- 35 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * William Jolitz. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. Neither the name of the University nor the names of its contributors 50 * may be used to endorse or promote products derived from this software 51 * without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * @(#)machdep.c 7.4 (Berkeley) 6/3/91 66 */ 67 68#include "ksyms.h" 69 70#include <sys/param.h> 71#include <sys/systm.h> 72#include <sys/kernel.h> 73#include <sys/proc.h> 74#include <sys/mount.h> 75#include <sys/reboot.h> 76#include <sys/sysctl.h> 77#include <sys/exec.h> 78#include <sys/core.h> 79#include <sys/kcore.h> 80 81#include <net/if.h> 82 83#include <uvm/uvm_extern.h> 84 85#include <dev/cons.h> 86 87#include <sh/bscreg.h> 88#include <sh/cpgreg.h> 89#include <sh/trap.h> 90 91#include <sh/cache.h> 92#include <sh/cache_sh4.h> 93#include <sh/mmu_sh4.h> 94 95#include <machine/cpu.h> 96#include <machine/kcore.h> 97#include <machine/pcb.h> 98 99#include <landisk/landisk/landiskreg.h> 100 101#ifdef DDB 102#include <machine/db_machdep.h> 103#include <ddb/db_extern.h> 104#include <ddb/db_interface.h> 105#endif 106 107/* the following is used externally (sysctl_hw) */ 108char machine[] = MACHINE; /* landisk */ 109 110__dead void landisk_startup(int, char *); 111__dead void main(void); 112void cpu_init_kcore_hdr(void); 113void blink_led(void *); 114 115int led_blink; 116 117extern u_int32_t getramsize(void); 118 119struct uvm_constraint_range dma_constraint = { 0x0, (paddr_t)-1 }; 120struct uvm_constraint_range *uvm_md_constraints[] = { NULL }; 121 122/* 123 * safepri is a safe priority for sleep to set for a spin-wait 124 * during autoconfiguration or after a panic. 125 */ 126int safepri = 0; 127 128void 129cpu_startup(void) 130{ 131 extern char cpu_model[120]; 132 133 strlcpy(cpu_model, "SH4 SH7751R", sizeof cpu_model); 134 135 sh_startup(); 136} 137 138vaddr_t kernend; /* used by /dev/mem too */ 139char *esym; 140 141__dead void 142landisk_startup(int howto, char *_esym) 143{ 144 u_int32_t ramsize; 145 146 /* Start to determine heap area */ 147 esym = _esym; 148 kernend = (vaddr_t)round_page((vaddr_t)esym); 149 150 boothowto = howto; 151 152 ramsize = getramsize(); 153 154 /* Initialize CPU ops. */ 155 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7751R); 156 157 /* Initialize early console */ 158 consinit(); 159 160 /* Load memory to UVM */ 161 if (ramsize == 0 || ramsize > 512 * 1024 * 1024) 162 ramsize = IOM_RAM_SIZE; 163 physmem = atop(ramsize); 164 kernend = atop(round_page(SH3_P1SEG_TO_PHYS(kernend))); 165 uvm_page_physload(atop(IOM_RAM_BEGIN), 166 atop(IOM_RAM_BEGIN + ramsize), kernend, 167 atop(IOM_RAM_BEGIN + ramsize), 0); 168 cpu_init_kcore_hdr(); /* need to be done before pmap_bootstrap */ 169 170 /* Initialize proc0 u-area */ 171 sh_proc0_init(); 172 173 /* Initialize pmap and start to address translation */ 174 pmap_bootstrap(); 175 176#if defined(DDB) 177 db_machine_init(); 178 ddb_init(); 179 if (boothowto & RB_KDB) { 180 Debugger(); 181 } 182#endif 183 184 /* Jump to main */ 185 __asm volatile( 186 "jmp @%0\n\t" 187 " mov %1, sp" 188 :: "r" (main), "r" (proc0.p_md.md_pcb->pcb_sf.sf_r7_bank)); 189 for (;;) 190 continue; 191 /* NOTREACHED */ 192} 193 194__dead void 195boot(int howto) 196{ 197 if (cold) { 198 if ((howto & RB_USERREQ) == 0) 199 howto |= RB_HALT; 200 goto haltsys; 201 } 202 203 boothowto = howto; 204 if ((howto & RB_NOSYNC) == 0) { 205 vfs_shutdown(); 206 207 if ((howto & RB_TIMEBAD) == 0) { 208 resettodr(); 209 } else { 210 printf("WARNING: not updating battery clock\n"); 211 } 212 } 213 if_downall(); 214 215 uvm_shutdown(); 216 splhigh(); 217 cold = 1; 218 219 if ((howto & RB_DUMP) != 0) 220 dumpsys(); 221 222haltsys: 223 config_suspend_all(DVACT_POWERDOWN); 224 225 if ((howto & RB_POWERDOWN) != 0) { 226 _reg_write_1(LANDISK_PWRMNG, PWRMNG_POWEROFF); 227 delay(1 * 1000 * 1000); 228 printf("POWEROFF FAILED!\n"); 229 howto |= RB_HALT; 230 } 231 232 if ((howto & RB_HALT) != 0) { 233 printf("\n"); 234 printf("The operating system has halted.\n"); 235 printf("Please press any key to reboot.\n\n"); 236 cnpollc(1); 237 cngetc(); 238 cnpollc(0); 239 } 240 241 printf("rebooting...\n"); 242 machine_reset(); 243 244 for (;;) 245 continue; 246 /* NOTREACHED */ 247} 248 249void 250machine_reset(void) 251{ 252 _cpu_exception_suspend(); 253 _reg_write_4(SH_(EXPEVT), EXPEVT_RESET_MANUAL); 254 (void)*(volatile uint32_t *)0x80000001; /* CPU shutdown */ 255 256 /*NOTREACHED*/ 257 for (;;) { 258 continue; 259 } 260} 261 262#if !defined(DONT_INIT_BSC) 263/* 264 * InitializeBsc 265 * : BSC(Bus State Controller) 266 */ 267void InitializeBsc(void); 268 269void 270InitializeBsc(void) 271{ 272 273 /* 274 * Drive RAS,CAS in stand by mode and bus release mode 275 * Area0 = Normal memory, Area5,6=Normal(no burst) 276 * Area2 = Normal memory, Area3 = SDRAM, Area5 = Normal memory 277 * Area4 = Normal Memory 278 * Area6 = Normal memory 279 */ 280 _reg_write_4(SH4_BCR1, BSC_BCR1_VAL); 281 282 /* 283 * Bus Width 284 * Area4: Bus width = 16bit 285 * Area6,5 = 16bit 286 * Area1 = 8bit 287 * Area2,3: Bus width = 32bit 288 */ 289 _reg_write_2(SH4_BCR2, BSC_BCR2_VAL); 290 291#if defined(SH4) && defined(SH7751R) 292 if (cpu_product == CPU_PRODUCT_7751R) { 293#ifdef BSC_BCR3_VAL 294 _reg_write_2(SH4_BCR3, BSC_BCR3_VAL); 295#endif 296#ifdef BSC_BCR4_VAL 297 _reg_write_4(SH4_BCR4, BSC_BCR4_VAL); 298#endif 299 } 300#endif /* SH4 && SH7751R */ 301 302 /* 303 * Idle cycle number in transition area and read to write 304 * Area6 = 3, Area5 = 3, Area4 = 3, Area3 = 3, Area2 = 3 305 * Area1 = 3, Area0 = 3 306 */ 307 _reg_write_4(SH4_WCR1, BSC_WCR1_VAL); 308 309 /* 310 * Wait cycle 311 * Area 6 = 6 312 * Area 5 = 2 313 * Area 4 = 10 314 * Area 3 = 3 315 * Area 2,1 = 3 316 * Area 0 = 6 317 */ 318 _reg_write_4(SH4_WCR2, BSC_WCR2_VAL); 319 320#ifdef BSC_WCR3_VAL 321 _reg_write_4(SH4_WCR3, BSC_WCR3_VAL); 322#endif 323 324 /* 325 * RAS pre-charge = 2cycle, RAS-CAS delay = 3 cycle, 326 * write pre-charge=1cycle 327 * CAS before RAS refresh RAS assert time = 3 cycle 328 * Disable burst, Bus size=32bit, Column Address=10bit, Refresh ON 329 * CAS before RAS refresh ON, EDO DRAM 330 */ 331 _reg_write_4(SH4_MCR, BSC_MCR_VAL); 332 333#ifdef BSC_SDMR2_VAL 334 _reg_write_1(BSC_SDMR2_VAL, 0); 335#endif 336 337#ifdef BSC_SDMR3_VAL 338 _reg_write_1(BSC_SDMR3_VAL, 0); 339#endif /* BSC_SDMR3_VAL */ 340 341 /* 342 * PCMCIA Control Register 343 * OE/WE assert delay 3.5 cycle 344 * OE/WE negate-address delay 3.5 cycle 345 */ 346#ifdef BSC_PCR_VAL 347 _reg_write_2(SH4_PCR, BSC_PCR_VAL); 348#endif 349 350 /* 351 * Refresh Timer Control/Status Register 352 * Disable interrupt by CMF, closk 1/16, Disable OVF interrupt 353 * Count Limit = 1024 354 * In following statement, the reason why high byte = 0xa5(a4 in RFCR) 355 * is the rule of SH3 in writing these register. 356 */ 357 _reg_write_2(SH4_RTCSR, BSC_RTCSR_VAL); 358 359 /* 360 * Refresh Timer Counter 361 * Initialize to 0 362 */ 363#ifdef BSC_RTCNT_VAL 364 _reg_write_2(SH4_RTCNT, BSC_RTCNT_VAL); 365#endif 366 367 /* set Refresh Time Constant Register */ 368 _reg_write_2(SH4_RTCOR, BSC_RTCOR_VAL); 369 370 /* init Refresh Count Register */ 371#ifdef BSC_RFCR_VAL 372 _reg_write_2(SH4_RFCR, BSC_RFCR_VAL); 373#endif 374 375 /* 376 * Clock Pulse Generator 377 */ 378 /* Set Clock mode (make internal clock double speed) */ 379 _reg_write_2(SH4_FRQCR, FRQCR_VAL); 380} 381#endif /* !DONT_INIT_BSC */ 382 383/* 384 * Dump the machine-dependent dump header. 385 */ 386u_int 387cpu_dump(int (*dump)(dev_t, daddr_t, caddr_t, size_t), daddr_t *blknop) 388{ 389 extern cpu_kcore_hdr_t cpu_kcore_hdr; 390 char buf[dbtob(1)]; 391 cpu_kcore_hdr_t *h; 392 kcore_seg_t *kseg; 393 int rc; 394 395#ifdef DIAGNOSTIC 396 if (cpu_dumpsize() > btodb(sizeof buf)) { 397 printf("buffer too small in cpu_dump, "); 398 return (EINVAL); /* "aborted" */ 399 } 400#endif 401 402 bzero(buf, sizeof buf); 403 kseg = (kcore_seg_t *)buf; 404 h = (cpu_kcore_hdr_t *)(buf + ALIGN(sizeof(kcore_seg_t))); 405 406 /* Create the segment header */ 407 CORE_SETMAGIC(*kseg, KCORE_MAGIC, MID_MACHINE, CORE_CPU); 408 kseg->c_size = dbtob(1) - ALIGN(sizeof(kcore_seg_t)); 409 410 bcopy(&cpu_kcore_hdr, h, sizeof(*h)); 411 /* We can now fill kptp in the header... */ 412 h->kcore_kptp = SH3_P1SEG_TO_PHYS((vaddr_t)pmap_kernel()->pm_ptp); 413 414 rc = (*dump)(dumpdev, *blknop, buf, sizeof buf); 415 *blknop += btodb(sizeof buf); 416 return (rc); 417} 418 419/* 420 * Return the size of the machine-dependent dump header, in disk blocks. 421 */ 422u_int 423cpu_dumpsize(void) 424{ 425 u_int size; 426 427 size = ALIGN(sizeof(kcore_seg_t)) + ALIGN(sizeof(cpu_kcore_hdr_t)); 428 return (btodb(roundup(size, dbtob(1)))); 429} 430 431/* 432 * Fill the machine-dependent dump header. 433 */ 434void 435cpu_init_kcore_hdr(void) 436{ 437 extern cpu_kcore_hdr_t cpu_kcore_hdr; 438 cpu_kcore_hdr_t *h = &cpu_kcore_hdr; 439 phys_ram_seg_t *seg = cpu_kcore_hdr.kcore_segs; 440 struct vm_physseg *physseg = vm_physmem; 441 u_int i; 442 443 bzero(h, sizeof(*h)); 444 445 h->kcore_nsegs = min(NPHYS_RAM_SEGS, (u_int)vm_nphysseg); 446 for (i = h->kcore_nsegs; i != 0; i--) { 447 seg->start = ptoa(physseg->start); 448 seg->size = (psize_t)ptoa(physseg->end - physseg->start); 449 seg++; 450 physseg++; 451 } 452} 453 454int 455cpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp, 456 size_t newlen, struct proc *p) 457{ 458 int oldval, ret; 459 460 /* all sysctl names at this level are terminal */ 461 if (namelen != 1) 462 return (ENOTDIR); /* overloaded */ 463 464 switch (name[0]) { 465 case CPU_CONSDEV: { 466 dev_t consdev; 467 if (cn_tab != NULL) 468 consdev = cn_tab->cn_dev; 469 else 470 consdev = NODEV; 471 return (sysctl_rdstruct(oldp, oldlenp, newp, &consdev, 472 sizeof consdev)); 473 } 474 475 case CPU_LED_BLINK: 476 oldval = led_blink; 477 ret = sysctl_int(oldp, oldlenp, newp, newlen, &led_blink); 478 if (oldval != led_blink) 479 blink_led(NULL); 480 return (ret); 481 482 default: 483 return (EOPNOTSUPP); 484 } 485 /* NOTREACHED */ 486} 487 488void 489blink_led(void *whatever) 490{ 491 static struct timeout blink_tmo; 492 u_int8_t ledctrl; 493 494 if (led_blink == 0) { 495 _reg_write_1(LANDISK_LEDCTRL, 496 LED_POWER_CHANGE | LED_POWER_VALUE); 497 return; 498 } 499 500 ledctrl = (u_int8_t)_reg_read_1(LANDISK_LEDCTRL) & LED_POWER_VALUE; 501 ledctrl ^= (LED_POWER_CHANGE | LED_POWER_VALUE); 502 _reg_write_1(LANDISK_LEDCTRL, ledctrl); 503 504 timeout_set(&blink_tmo, blink_led, NULL); 505 timeout_add(&blink_tmo, 506 ((averunnable.ldavg[0] + FSCALE) * hz) >> FSHIFT); 507} 508