machdep.c revision 1.39 
1/*	$OpenBSD: machdep.c,v 1.39 2014/07/14 08:36:31 uebayasi Exp $	*/
2/*	$NetBSD: machdep.c,v 1.1 2006/09/01 21:26:18 uwe Exp $	*/
3
4/*-
5 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
10 * Simulation Facility, NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 *    notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 *    notice, this list of conditions and the following disclaimer in the
19 *    documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34/*-
35 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
36 * All rights reserved.
37 *
38 * This code is derived from software contributed to Berkeley by
39 * William Jolitz.
40 *
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
43 * are met:
44 * 1. Redistributions of source code must retain the above copyright
45 *    notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 *    notice, this list of conditions and the following disclaimer in the
48 *    documentation and/or other materials provided with the distribution.
49 * 3. Neither the name of the University nor the names of its contributors
50 *    may be used to endorse or promote products derived from this software
51 *    without specific prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
56 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
63 * SUCH DAMAGE.
64 *
65 *	@(#)machdep.c	7.4 (Berkeley) 6/3/91
66 */
67
68#include "ksyms.h"
69
70#include <sys/param.h>
71#include <sys/systm.h>
72#include <sys/kernel.h>
73#include <sys/proc.h>
74#include <sys/mount.h>
75#include <sys/reboot.h>
76#include <sys/sysctl.h>
77#include <sys/exec.h>
78#include <sys/core.h>
79#include <sys/kcore.h>
80
81#include <net/if.h>
82
83#include <uvm/uvm_extern.h>
84
85#include <dev/cons.h>
86
87#include <sh/bscreg.h>
88#include <sh/cpgreg.h>
89#include <sh/trap.h>
90
91#include <sh/cache.h>
92#include <sh/cache_sh4.h>
93#include <sh/mmu_sh4.h>
94
95#include <machine/cpu.h>
96#include <machine/kcore.h>
97#include <machine/pcb.h>
98
99#include <landisk/landisk/landiskreg.h>
100
101#ifdef DDB
102#include <machine/db_machdep.h>
103#include <ddb/db_extern.h>
104#include <ddb/db_interface.h>
105#endif
106
107/* the following is used externally (sysctl_hw) */
108char machine[] = MACHINE;		/* landisk */
109
110__dead void landisk_startup(int, char *);
111__dead void main(void);
112void	cpu_init_kcore_hdr(void);
113void	blink_led(void *);
114
115int	led_blink;
116
117extern u_int32_t getramsize(void);
118
119struct uvm_constraint_range  dma_constraint = { 0x0, (paddr_t)-1 };
120struct uvm_constraint_range *uvm_md_constraints[] = { NULL };
121
122/*
123 * safepri is a safe priority for sleep to set for a spin-wait
124 * during autoconfiguration or after a panic.
125 */
126int   safepri = 0;
127
128void
129cpu_startup(void)
130{
131	extern char cpu_model[120];
132
133	strlcpy(cpu_model, "SH4 SH7751R", sizeof cpu_model);
134
135        sh_startup();
136}
137
138vaddr_t kernend;	/* used by /dev/mem too */
139char *esym;
140
141__dead void
142landisk_startup(int howto, char *_esym)
143{
144	u_int32_t ramsize;
145
146	/* Start to determine heap area */
147	esym = _esym;
148	kernend = (vaddr_t)round_page((vaddr_t)esym);
149
150	boothowto = howto;
151
152	ramsize = getramsize();
153
154	/* Initialize CPU ops. */
155	sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7751R);
156
157	/* Initialize early console */
158	consinit();
159
160	/* Load memory to UVM */
161	if (ramsize == 0 || ramsize > 512 * 1024 * 1024)
162		ramsize = IOM_RAM_SIZE;
163	physmem = atop(ramsize);
164	kernend = atop(round_page(SH3_P1SEG_TO_PHYS(kernend)));
165	uvm_page_physload(atop(IOM_RAM_BEGIN),
166	    atop(IOM_RAM_BEGIN + ramsize), kernend,
167	    atop(IOM_RAM_BEGIN + ramsize), 0);
168	cpu_init_kcore_hdr();	/* need to be done before pmap_bootstrap */
169
170	/* Initialize proc0 u-area */
171	sh_proc0_init();
172
173	/* Initialize pmap and start to address translation */
174	pmap_bootstrap();
175
176#if defined(DDB)
177	db_machine_init();
178	ddb_init();
179	if (boothowto & RB_KDB) {
180		Debugger();
181	}
182#endif
183
184	/* Jump to main */
185	__asm volatile(
186		"jmp	@%0\n\t"
187		" mov	%1, sp"
188		:: "r" (main), "r" (proc0.p_md.md_pcb->pcb_sf.sf_r7_bank));
189	/* NOTREACHED */
190	for (;;) ;
191}
192
193__dead void
194boot(int howto)
195{
196	struct device *mainbus;
197
198	if (cold) {
199		if ((howto & RB_USERREQ) == 0)
200			howto |= RB_HALT;
201		goto haltsys;
202	}
203
204	boothowto = howto;
205	if ((howto & RB_NOSYNC) == 0) {
206		vfs_shutdown();
207
208		if ((howto & RB_TIMEBAD) == 0) {
209			resettodr();
210		} else {
211			printf("WARNING: not updating battery clock\n");
212		}
213	}
214	if_downall();
215
216	uvm_shutdown();
217	splhigh();
218	cold = 1;
219
220	if (howto & RB_DUMP)
221		dumpsys();
222
223haltsys:
224	doshutdownhooks();
225	mainbus = device_mainbus();
226	if (mainbus != NULL)
227		config_suspend(mainbus, DVACT_POWERDOWN);
228
229	if ((howto & RB_POWERDOWN) == RB_POWERDOWN) {
230		_reg_write_1(LANDISK_PWRMNG, PWRMNG_POWEROFF);
231		delay(1 * 1000 * 1000);
232		printf("POWEROFF FAILED!\n");
233		howto |= RB_HALT;
234	}
235
236	if (howto & RB_HALT) {
237		printf("\n");
238		printf("The operating system has halted.\n");
239		printf("Please press any key to reboot.\n\n");
240		cnpollc(1);
241		cngetc();
242		cnpollc(0);
243	}
244
245	printf("rebooting...\n");
246	machine_reset();
247
248	/* NOTREACHED */
249	for (;;) {
250		continue;
251	}
252}
253
254void
255machine_reset(void)
256{
257	_cpu_exception_suspend();
258	_reg_write_4(SH_(EXPEVT), EXPEVT_RESET_MANUAL);
259	(void)*(volatile uint32_t *)0x80000001;	/* CPU shutdown */
260
261	/*NOTREACHED*/
262	for (;;) {
263		continue;
264	}
265}
266
267#if !defined(DONT_INIT_BSC)
268/*
269 * InitializeBsc
270 * : BSC(Bus State Controller)
271 */
272void InitializeBsc(void);
273
274void
275InitializeBsc(void)
276{
277
278	/*
279	 * Drive RAS,CAS in stand by mode and bus release mode
280	 * Area0 = Normal memory, Area5,6=Normal(no burst)
281	 * Area2 = Normal memory, Area3 = SDRAM, Area5 = Normal memory
282	 * Area4 = Normal Memory
283	 * Area6 = Normal memory
284	 */
285	_reg_write_4(SH4_BCR1, BSC_BCR1_VAL);
286
287	/*
288	 * Bus Width
289	 * Area4: Bus width = 16bit
290	 * Area6,5 = 16bit
291	 * Area1 = 8bit
292	 * Area2,3: Bus width = 32bit
293	 */
294	_reg_write_2(SH4_BCR2, BSC_BCR2_VAL);
295
296#if defined(SH4) && defined(SH7751R)
297	if (cpu_product == CPU_PRODUCT_7751R) {
298#ifdef BSC_BCR3_VAL
299		_reg_write_2(SH4_BCR3, BSC_BCR3_VAL);
300#endif
301#ifdef BSC_BCR4_VAL
302		_reg_write_4(SH4_BCR4, BSC_BCR4_VAL);
303#endif
304	}
305#endif	/* SH4 && SH7751R */
306
307	/*
308	 * Idle cycle number in transition area and read to write
309	 * Area6 = 3, Area5 = 3, Area4 = 3, Area3 = 3, Area2 = 3
310	 * Area1 = 3, Area0 = 3
311	 */
312	_reg_write_4(SH4_WCR1, BSC_WCR1_VAL);
313
314	/*
315	 * Wait cycle
316	 * Area 6 = 6
317	 * Area 5 = 2
318	 * Area 4 = 10
319	 * Area 3 = 3
320	 * Area 2,1 = 3
321	 * Area 0 = 6
322	 */
323	_reg_write_4(SH4_WCR2, BSC_WCR2_VAL);
324
325#ifdef BSC_WCR3_VAL
326	_reg_write_4(SH4_WCR3, BSC_WCR3_VAL);
327#endif
328
329	/*
330	 * RAS pre-charge = 2cycle, RAS-CAS delay = 3 cycle,
331	 * write pre-charge=1cycle
332	 * CAS before RAS refresh RAS assert time = 3 cycle
333	 * Disable burst, Bus size=32bit, Column Address=10bit, Refresh ON
334	 * CAS before RAS refresh ON, EDO DRAM
335	 */
336	_reg_write_4(SH4_MCR, BSC_MCR_VAL);
337
338#ifdef BSC_SDMR2_VAL
339	_reg_write_1(BSC_SDMR2_VAL, 0);
340#endif
341
342#ifdef BSC_SDMR3_VAL
343	_reg_write_1(BSC_SDMR3_VAL, 0);
344#endif /* BSC_SDMR3_VAL */
345
346	/*
347	 * PCMCIA Control Register
348	 * OE/WE assert delay 3.5 cycle
349	 * OE/WE negate-address delay 3.5 cycle
350	 */
351#ifdef BSC_PCR_VAL
352	_reg_write_2(SH4_PCR, BSC_PCR_VAL);
353#endif
354
355	/*
356	 * Refresh Timer Control/Status Register
357	 * Disable interrupt by CMF, closk 1/16, Disable OVF interrupt
358	 * Count Limit = 1024
359	 * In following statement, the reason why high byte = 0xa5(a4 in RFCR)
360	 * is the rule of SH3 in writing these register.
361	 */
362	_reg_write_2(SH4_RTCSR, BSC_RTCSR_VAL);
363
364	/*
365	 * Refresh Timer Counter
366	 * Initialize to 0
367	 */
368#ifdef BSC_RTCNT_VAL
369	_reg_write_2(SH4_RTCNT, BSC_RTCNT_VAL);
370#endif
371
372	/* set Refresh Time Constant Register */
373	_reg_write_2(SH4_RTCOR, BSC_RTCOR_VAL);
374
375	/* init Refresh Count Register */
376#ifdef BSC_RFCR_VAL
377	_reg_write_2(SH4_RFCR, BSC_RFCR_VAL);
378#endif
379
380	/*
381	 * Clock Pulse Generator
382	 */
383	/* Set Clock mode (make internal clock double speed) */
384	_reg_write_2(SH4_FRQCR, FRQCR_VAL);
385}
386#endif /* !DONT_INIT_BSC */
387
388/*
389 * Dump the machine-dependent dump header.
390 */
391u_int
392cpu_dump(int (*dump)(dev_t, daddr_t, caddr_t, size_t), daddr_t *blknop)
393{
394	extern cpu_kcore_hdr_t cpu_kcore_hdr;
395	char buf[dbtob(1)];
396	cpu_kcore_hdr_t *h;
397	kcore_seg_t *kseg;
398	int rc;
399
400#ifdef DIAGNOSTIC
401	if (cpu_dumpsize() > btodb(sizeof buf)) {
402		printf("buffer too small in cpu_dump, ");
403		return (EINVAL);	/* "aborted" */
404	}
405#endif
406
407	bzero(buf, sizeof buf);
408	kseg = (kcore_seg_t *)buf;
409	h = (cpu_kcore_hdr_t *)(buf + ALIGN(sizeof(kcore_seg_t)));
410
411	/* Create the segment header */
412	CORE_SETMAGIC(*kseg, KCORE_MAGIC, MID_MACHINE, CORE_CPU);
413	kseg->c_size = dbtob(1) - ALIGN(sizeof(kcore_seg_t));
414
415	bcopy(&cpu_kcore_hdr, h, sizeof(*h));
416	/* We can now fill kptp in the header... */
417	h->kcore_kptp = SH3_P1SEG_TO_PHYS((vaddr_t)pmap_kernel()->pm_ptp);
418
419	rc = (*dump)(dumpdev, *blknop, buf, sizeof buf);
420	*blknop += btodb(sizeof buf);
421	return (rc);
422}
423
424/*
425 * Return the size of the machine-dependent dump header, in disk blocks.
426 */
427u_int
428cpu_dumpsize()
429{
430	u_int size;
431
432	size = ALIGN(sizeof(kcore_seg_t)) + ALIGN(sizeof(cpu_kcore_hdr_t));
433	return (btodb(roundup(size, dbtob(1))));
434}
435
436/*
437 * Fill the machine-dependent dump header.
438 */
439void
440cpu_init_kcore_hdr()
441{
442	extern cpu_kcore_hdr_t cpu_kcore_hdr;
443	cpu_kcore_hdr_t *h = &cpu_kcore_hdr;
444	phys_ram_seg_t *seg = cpu_kcore_hdr.kcore_segs;
445	struct vm_physseg *physseg = vm_physmem;
446	u_int i;
447
448	bzero(h, sizeof(*h));
449
450	h->kcore_nsegs = min(NPHYS_RAM_SEGS, (u_int)vm_nphysseg);
451	for (i = h->kcore_nsegs; i != 0; i--) {
452		seg->start = ptoa(physseg->start);
453		seg->size = (psize_t)ptoa(physseg->end - physseg->start);
454		seg++;
455		physseg++;
456	}
457}
458
459int
460cpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp,
461    size_t newlen, struct proc *p)
462{
463	int oldval, ret;
464
465	/* all sysctl names at this level are terminal */
466	if (namelen != 1)
467		return (ENOTDIR);		/* overloaded */
468
469	switch (name[0]) {
470	case CPU_CONSDEV: {
471		dev_t consdev;
472		if (cn_tab != NULL)
473			consdev = cn_tab->cn_dev;
474		else
475			consdev = NODEV;
476		return (sysctl_rdstruct(oldp, oldlenp, newp, &consdev,
477		    sizeof consdev));
478	}
479
480	case CPU_LED_BLINK:
481		oldval = led_blink;
482		ret = sysctl_int(oldp, oldlenp, newp, newlen, &led_blink);
483		if (oldval != led_blink)
484			blink_led(NULL);
485		return (ret);
486
487	default:
488		return (EOPNOTSUPP);
489	}
490	/* NOTREACHED */
491}
492
493void
494blink_led(void *whatever)
495{
496	static struct timeout blink_tmo;
497	u_int8_t ledctrl;
498
499	if (led_blink == 0) {
500		_reg_write_1(LANDISK_LEDCTRL,
501		    LED_POWER_CHANGE | LED_POWER_VALUE);
502		return;
503	}
504
505	ledctrl = (u_int8_t)_reg_read_1(LANDISK_LEDCTRL) & LED_POWER_VALUE;
506	ledctrl ^= (LED_POWER_CHANGE | LED_POWER_VALUE);
507	_reg_write_1(LANDISK_LEDCTRL, ledctrl);
508
509	timeout_set(&blink_tmo, blink_led, NULL);
510	timeout_add(&blink_tmo,
511	    ((averunnable.ldavg[0] + FSCALE) * hz) >> FSHIFT);
512}
513