machdep.c revision 1.20
1/* $OpenBSD: machdep.c,v 1.20 2010/06/10 17:54:13 deraadt Exp $ */ 2/* $NetBSD: machdep.c,v 1.1 2006/09/01 21:26:18 uwe Exp $ */ 3 4/*- 5 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 10 * Simulation Facility, NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34/*- 35 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * William Jolitz. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. Neither the name of the University nor the names of its contributors 50 * may be used to endorse or promote products derived from this software 51 * without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 54 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 56 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 59 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 63 * SUCH DAMAGE. 64 * 65 * @(#)machdep.c 7.4 (Berkeley) 6/3/91 66 */ 67 68#include "ksyms.h" 69 70#include <sys/param.h> 71#include <sys/systm.h> 72#include <sys/kernel.h> 73#include <sys/proc.h> 74#include <sys/user.h> 75#include <sys/mount.h> 76#include <sys/reboot.h> 77#include <sys/sysctl.h> 78#include <sys/exec.h> 79#include <sys/core.h> 80#include <sys/kcore.h> 81 82#include <uvm/uvm_extern.h> 83 84#include <dev/cons.h> 85 86#include <sh/bscreg.h> 87#include <sh/cpgreg.h> 88#include <sh/trap.h> 89 90#include <sh/cache.h> 91#include <sh/cache_sh4.h> 92#include <sh/mmu_sh4.h> 93 94#include <machine/cpu.h> 95#include <machine/kcore.h> 96 97#include <landisk/landisk/landiskreg.h> 98 99#ifdef DDB 100#include <machine/db_machdep.h> 101#include <ddb/db_extern.h> 102#include <ddb/db_interface.h> 103#endif 104 105/* the following is used externally (sysctl_hw) */ 106char machine[] = MACHINE; /* landisk */ 107 108__dead void landisk_startup(int, char *); 109__dead void main(void); 110void cpu_init_kcore_hdr(void); 111void blink_led(void *); 112 113int kbd_reset; 114int led_blink; 115 116extern u_int32_t getramsize(void); 117 118/* 119 * safepri is a safe priority for sleep to set for a spin-wait 120 * during autoconfiguration or after a panic. 121 */ 122int safepri = 0; 123 124void 125cpu_startup(void) 126{ 127 extern char cpu_model[120]; 128 129 strlcpy(cpu_model, "SH4 SH7751R", sizeof cpu_model); 130 131 sh_startup(); 132} 133 134vaddr_t kernend; /* used by /dev/mem too */ 135char *esym; 136 137__dead void 138landisk_startup(int howto, char *_esym) 139{ 140 u_int32_t ramsize; 141 142 /* Start to determine heap area */ 143 esym = _esym; 144 kernend = (vaddr_t)round_page((vaddr_t)esym); 145 146 boothowto = howto; 147 148 ramsize = getramsize(); 149 150 /* Initialize CPU ops. */ 151 sh_cpu_init(CPU_ARCH_SH4, CPU_PRODUCT_7751R); 152 153 /* Initialize early console */ 154 consinit(); 155 156 /* Load memory to UVM */ 157 if (ramsize == 0 || ramsize > 512 * 1024 * 1024) 158 ramsize = IOM_RAM_SIZE; 159 physmem = atop(ramsize); 160 kernend = atop(round_page(SH3_P1SEG_TO_PHYS(kernend))); 161 uvm_page_physload(atop(IOM_RAM_BEGIN), 162 atop(IOM_RAM_BEGIN + ramsize), kernend, 163 atop(IOM_RAM_BEGIN + ramsize), VM_FREELIST_DEFAULT); 164 cpu_init_kcore_hdr(); /* need to be done before pmap_bootstrap */ 165 166 /* Initialize proc0 u-area */ 167 sh_proc0_init(); 168 169 /* Initialize pmap and start to address translation */ 170 pmap_bootstrap(); 171 172#if defined(DDB) 173 db_machine_init(); 174 ddb_init(); 175 if (boothowto & RB_KDB) { 176 Debugger(); 177 } 178#endif 179 180 /* Jump to main */ 181 __asm volatile( 182 "jmp @%0\n\t" 183 " mov %1, sp" 184 :: "r" (main), "r" (proc0.p_md.md_pcb->pcb_sf.sf_r7_bank)); 185 /* NOTREACHED */ 186 for (;;) ; 187} 188 189void 190boot(int howto) 191{ 192 193 if (cold) { 194 if ((howto & RB_USERREQ) == 0) 195 howto |= RB_HALT; 196 goto haltsys; 197 } 198 199 boothowto = howto; 200 if ((howto & RB_NOSYNC) == 0) { 201 vfs_shutdown(); 202 /* 203 * If we've been adjusting the clock, the todr 204 * will be out of synch; adjust it now. 205 */ 206 if ((howto & RB_TIMEBAD) == 0) 207 resettodr(); 208 else 209 printf("WARNING: not updating battery clock\n"); 210 } 211 212 uvm_shutdown(); 213 splhigh(); /* Disable interrupts. */ 214 215 /* Do a dump if requested. */ 216 if (howto & RB_DUMP) 217 dumpsys(); 218 219haltsys: 220 doshutdownhooks(); 221 222 if ((howto & RB_POWERDOWN) == RB_POWERDOWN) { 223 _reg_write_1(LANDISK_PWRMNG, PWRMNG_POWEROFF); 224 delay(1 * 1000 * 1000); 225 printf("POWEROFF FAILED!\n"); 226 howto |= RB_HALT; 227 } 228 229 if (howto & RB_HALT) { 230 printf("\n"); 231 printf("The operating system has halted.\n"); 232 printf("Please press any key to reboot.\n\n"); 233 cnpollc(1); 234 cngetc(); 235 cnpollc(0); 236 } 237 238 printf("rebooting...\n"); 239 machine_reset(); 240 241 /*NOTREACHED*/ 242 for (;;) { 243 continue; 244 } 245} 246 247void 248machine_reset(void) 249{ 250 _cpu_exception_suspend(); 251 _reg_write_4(SH_(EXPEVT), EXPEVT_RESET_MANUAL); 252 (void)*(volatile uint32_t *)0x80000001; /* CPU shutdown */ 253 254 /*NOTREACHED*/ 255 for (;;) { 256 continue; 257 } 258} 259 260#if !defined(DONT_INIT_BSC) 261/* 262 * InitializeBsc 263 * : BSC(Bus State Controller) 264 */ 265void InitializeBsc(void); 266 267void 268InitializeBsc(void) 269{ 270 271 /* 272 * Drive RAS,CAS in stand by mode and bus release mode 273 * Area0 = Normal memory, Area5,6=Normal(no burst) 274 * Area2 = Normal memory, Area3 = SDRAM, Area5 = Normal memory 275 * Area4 = Normal Memory 276 * Area6 = Normal memory 277 */ 278 _reg_write_4(SH4_BCR1, BSC_BCR1_VAL); 279 280 /* 281 * Bus Width 282 * Area4: Bus width = 16bit 283 * Area6,5 = 16bit 284 * Area1 = 8bit 285 * Area2,3: Bus width = 32bit 286 */ 287 _reg_write_2(SH4_BCR2, BSC_BCR2_VAL); 288 289#if defined(SH4) && defined(SH7751R) 290 if (cpu_product == CPU_PRODUCT_7751R) { 291#ifdef BSC_BCR3_VAL 292 _reg_write_2(SH4_BCR3, BSC_BCR3_VAL); 293#endif 294#ifdef BSC_BCR4_VAL 295 _reg_write_4(SH4_BCR4, BSC_BCR4_VAL); 296#endif 297 } 298#endif /* SH4 && SH7751R */ 299 300 /* 301 * Idle cycle number in transition area and read to write 302 * Area6 = 3, Area5 = 3, Area4 = 3, Area3 = 3, Area2 = 3 303 * Area1 = 3, Area0 = 3 304 */ 305 _reg_write_4(SH4_WCR1, BSC_WCR1_VAL); 306 307 /* 308 * Wait cycle 309 * Area 6 = 6 310 * Area 5 = 2 311 * Area 4 = 10 312 * Area 3 = 3 313 * Area 2,1 = 3 314 * Area 0 = 6 315 */ 316 _reg_write_4(SH4_WCR2, BSC_WCR2_VAL); 317 318#ifdef BSC_WCR3_VAL 319 _reg_write_4(SH4_WCR3, BSC_WCR3_VAL); 320#endif 321 322 /* 323 * RAS pre-charge = 2cycle, RAS-CAS delay = 3 cycle, 324 * write pre-charge=1cycle 325 * CAS before RAS refresh RAS assert time = 3 cycle 326 * Disable burst, Bus size=32bit, Column Address=10bit, Refresh ON 327 * CAS before RAS refresh ON, EDO DRAM 328 */ 329 _reg_write_4(SH4_MCR, BSC_MCR_VAL); 330 331#ifdef BSC_SDMR2_VAL 332 _reg_write_1(BSC_SDMR2_VAL, 0); 333#endif 334 335#ifdef BSC_SDMR3_VAL 336 _reg_write_1(BSC_SDMR3_VAL, 0); 337#endif /* BSC_SDMR3_VAL */ 338 339 /* 340 * PCMCIA Control Register 341 * OE/WE assert delay 3.5 cycle 342 * OE/WE negate-address delay 3.5 cycle 343 */ 344#ifdef BSC_PCR_VAL 345 _reg_write_2(SH4_PCR, BSC_PCR_VAL); 346#endif 347 348 /* 349 * Refresh Timer Control/Status Register 350 * Disable interrupt by CMF, closk 1/16, Disable OVF interrupt 351 * Count Limit = 1024 352 * In following statement, the reason why high byte = 0xa5(a4 in RFCR) 353 * is the rule of SH3 in writing these register. 354 */ 355 _reg_write_2(SH4_RTCSR, BSC_RTCSR_VAL); 356 357 /* 358 * Refresh Timer Counter 359 * Initialize to 0 360 */ 361#ifdef BSC_RTCNT_VAL 362 _reg_write_2(SH4_RTCNT, BSC_RTCNT_VAL); 363#endif 364 365 /* set Refresh Time Constant Register */ 366 _reg_write_2(SH4_RTCOR, BSC_RTCOR_VAL); 367 368 /* init Refresh Count Register */ 369#ifdef BSC_RFCR_VAL 370 _reg_write_2(SH4_RFCR, BSC_RFCR_VAL); 371#endif 372 373 /* 374 * Clock Pulse Generator 375 */ 376 /* Set Clock mode (make internal clock double speed) */ 377 _reg_write_2(SH4_FRQCR, FRQCR_VAL); 378} 379#endif /* !DONT_INIT_BSC */ 380 381/* 382 * Dump the machine-dependent dump header. 383 */ 384u_int 385cpu_dump(int (*dump)(dev_t, daddr64_t, caddr_t, size_t), daddr64_t *blknop) 386{ 387 extern cpu_kcore_hdr_t cpu_kcore_hdr; 388 char buf[dbtob(1)]; 389 cpu_kcore_hdr_t *h; 390 kcore_seg_t *kseg; 391 int rc; 392 393#ifdef DIAGNOSTIC 394 if (cpu_dumpsize() > btodb(sizeof buf)) { 395 printf("buffer too small in cpu_dump, "); 396 return (EINVAL); /* "aborted" */ 397 } 398#endif 399 400 bzero(buf, sizeof buf); 401 kseg = (kcore_seg_t *)buf; 402 h = (cpu_kcore_hdr_t *)(buf + ALIGN(sizeof(kcore_seg_t))); 403 404 /* Create the segment header */ 405 CORE_SETMAGIC(*kseg, KCORE_MAGIC, MID_MACHINE, CORE_CPU); 406 kseg->c_size = dbtob(1) - ALIGN(sizeof(kcore_seg_t)); 407 408 bcopy(&cpu_kcore_hdr, h, sizeof(*h)); 409 /* We can now fill kptp in the header... */ 410 h->kcore_kptp = SH3_P1SEG_TO_PHYS((vaddr_t)pmap_kernel()->pm_ptp); 411 412 rc = (*dump)(dumpdev, *blknop, buf, sizeof buf); 413 *blknop += btodb(sizeof buf); 414 return (rc); 415} 416 417/* 418 * Return the size of the machine-dependent dump header, in disk blocks. 419 */ 420u_int 421cpu_dumpsize() 422{ 423 u_int size; 424 425 size = ALIGN(sizeof(kcore_seg_t)) + ALIGN(sizeof(cpu_kcore_hdr_t)); 426 return (btodb(roundup(size, dbtob(1)))); 427} 428 429/* 430 * Fill the machine-dependent dump header. 431 */ 432void 433cpu_init_kcore_hdr() 434{ 435 extern cpu_kcore_hdr_t cpu_kcore_hdr; 436 cpu_kcore_hdr_t *h = &cpu_kcore_hdr; 437 phys_ram_seg_t *seg = cpu_kcore_hdr.kcore_segs; 438 struct vm_physseg *physseg = vm_physmem; 439 u_int i; 440 441 bzero(h, sizeof(*h)); 442 443 h->kcore_nsegs = min(NPHYS_RAM_SEGS, (u_int)vm_nphysseg); 444 for (i = h->kcore_nsegs; i != 0; i--) { 445 seg->start = ptoa(physseg->start); 446 seg->size = (psize_t)ptoa(physseg->end - physseg->start); 447 seg++; 448 physseg++; 449 } 450} 451 452int 453cpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp, 454 size_t newlen, struct proc *p) 455{ 456 int oldval, ret; 457 458 /* all sysctl names at this level are terminal */ 459 if (namelen != 1) 460 return (ENOTDIR); /* overloaded */ 461 462 switch (name[0]) { 463 case CPU_CONSDEV: { 464 dev_t consdev; 465 if (cn_tab != NULL) 466 consdev = cn_tab->cn_dev; 467 else 468 consdev = NODEV; 469 return (sysctl_rdstruct(oldp, oldlenp, newp, &consdev, 470 sizeof consdev)); 471 } 472 473 case CPU_KBDRESET: 474 if (securelevel > 0) 475 return (sysctl_rdint(oldp, oldlenp, newp, kbd_reset)); 476 return (sysctl_int(oldp, oldlenp, newp, newlen, &kbd_reset)); 477 478 case CPU_LED_BLINK: 479 oldval = led_blink; 480 ret = sysctl_int(oldp, oldlenp, newp, newlen, &led_blink); 481 if (oldval != led_blink) 482 blink_led(NULL); 483 return (ret); 484 485 default: 486 return (EOPNOTSUPP); 487 } 488 /* NOTREACHED */ 489} 490 491void 492blink_led(void *whatever) 493{ 494 static struct timeout blink_tmo; 495 u_int8_t ledctrl; 496 497 if (led_blink == 0) { 498 _reg_write_1(LANDISK_LEDCTRL, 499 LED_POWER_CHANGE | LED_POWER_VALUE); 500 return; 501 } 502 503 ledctrl = (u_int8_t)_reg_read_1(LANDISK_LEDCTRL) & LED_POWER_VALUE; 504 ledctrl ^= (LED_POWER_CHANGE | LED_POWER_VALUE); 505 _reg_write_1(LANDISK_LEDCTRL, ledctrl); 506 507 timeout_set(&blink_tmo, blink_led, NULL); 508 timeout_add(&blink_tmo, 509 ((averunnable.ldavg[0] + FSCALE) * hz) >> FSHIFT); 510} 511