reg.h revision 1.6
1/* $OpenBSD: reg.h,v 1.6 2000/05/15 17:07:28 mickey Exp $ */ 2 3/* 4 * Copyright (c) 1998 Michael Shalayeff 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Michael Shalayeff. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32/* 33 * Copyright (c) 1990,1994 The University of Utah and 34 * the Computer Systems Laboratory at the University of Utah (CSL). 35 * All rights reserved. 36 * 37 * Permission to use, copy, modify and distribute this software is hereby 38 * granted provided that (1) source code retains these copyright, permission, 39 * and disclaimer notices, and (2) redistributions including binaries 40 * reproduce the notices in supporting documentation, and (3) all advertising 41 * materials mentioning features or use of this software display the following 42 * acknowledgement: ``This product includes software developed by the 43 * Computer Systems Laboratory at the University of Utah.'' 44 * 45 * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS 46 * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF 47 * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * CSL requests users of this software to return to csl-dist@cs.utah.edu any 50 * improvements that they make and grant CSL redistribution rights. 51 * 52 * Utah $Hdr: regs.h 1.6 94/12/14$ 53 * Author: Bob Wheeler, University of Utah CSL 54 */ 55 56#ifndef _MACHINE_REG_H_ 57#define _MACHINE_REG_H_ 58 59/* 60 * constants for registers for use with the following routines: 61 * 62 * void mtctl(reg, value) - move to control register 63 * int mfctl(reg) - move from control register 64 * int mtsp(sreg, value) - move to space register 65 * int mfsr(sreg) - move from space register 66 */ 67 68#define CR_RCTR 0 69#define CR_PIDR1 8 70#define CR_PIDR2 9 71#define CR_CCR 10 72#define CR_SAR 11 73#define CR_PIDR3 12 74#define CR_PIDR4 13 75#define CR_IVA 14 76#define CR_EIEM 15 77#define CR_ITMR 16 78#define CR_PCSQ 17 79#define CR_PCOQ 18 80#define CR_IIR 19 81#define CR_ISR 20 82#define CR_IOR 21 83#define CR_IPSW 22 84#define CR_EIRR 23 85#define CR_HPTMASK 24 86#define CR_VTOP 25 87#define CR_TR2 26 88#define CR_TR3 27 89#define CR_HVTP 28 /* points to a faulted HVT slot on LC cpus */ 90#define CR_TR5 29 91#define CR_UPADDR 30 /* paddr of U-area of curproc */ 92#define CR_TR7 31 93 94/* 95 * Diagnostic registers and bit positions 96 */ 97#define DR_CPUCFG 0 98#define DR0_PCXL_L2IHPMC 6 /* r/c L2 I-cache error flag */ 99#define DR0_PCXL_L2IHPMC_DIS 7 /* r/w L2 I-cache hpmc disable mask */ 100#define DR0_PCXL_L2DHPMC 8 /* r/c L2 D-cache error flag */ 101#define DR0_PCXL_L2DHPMC_DIS 9 /* r/w L2 D-cache hpmc disable mask */ 102#define DR0_PCXL_L1IHPMC 10 /* r/c L1 I-cache error flag */ 103#define DR0_PCXL_L1IHPMC_DIS 11 /* r/w L1 I-cache hpmc disable mask */ 104#define DR0_PCXL_L2PARERR 15 /* r/c L2 Cache parity error (4 bit) */ 105#define DR0_PCXL_STORE0 16 /* r/w scratch space */ 106#define DR0_PCXL_PFMASK 17 /* r/w power-fail trap mask */ 107#define DR0_PCXL_STORE1 18 /* r/w scratch */ 108#define DR0_PCXL_FASTMODE 19 /* r 0-fast, 1-slow */ 109#define DR0_PCXL_ISTRM_EN 20 /* r/w I-cache streaming enable */ 110#define DR0_PCXL_DUAL_DIS 22 /* r/w disable dual-issue (2 bit) */ 111#define DR0_PCXL_ENDIAN 23 /* r/w little endian traps */ 112#define DR0_PCXL_SOU_EN 24 /* r/w stall-on-use on dc misses */ 113#define DR0_PCXL_SHINT_EN 25 /* r/w no-fill on miss store hints */ 114#define DR0_PCXL_IPREF_EN 26 /* r/w L2 to L1 I-cache prefetch */ 115#define DR0_PCXL_L2DHASH_EN 27 /* r/w L2 D-cache hash enable */ 116#define DR0_PCXL_L2IHASH_EN 28 /* r/w L2 I-cache hash enable */ 117#define DR0_PCXL_L1ICACHE_EN 29 /* r/w L1 I-cache enable */ 118#define DR0_PCXL_HIT 30 /* r Diag cache read hit indication */ 119#define DR0_PCXL_PARERR 31 /* r Diag cache read parity error */ 120 121#define DR0_PCXL2_L1DHPMC 8 /* r/c L1 D-cache error flag */ 122#define DR0_PCXL2_L1DHPMC_DIS 9 /* r/w L1 D-cache hpmc disable */ 123#define DR0_PCXL2_L2DHPMC 10 /* r/c L1 I-cache error flag */ 124#define DR0_PCXL2_L2DHPMC_DIS 11 /* r/w L1 I-cache hpmc disable */ 125#define DR0_PCXL2_STORE0 16 /* r/w scratch space */ 126#define DR0_PCXL2_PFMASK 17 /* r/w power-fail trap mask */ 127#define DR0_PCXL2_STORE1 18 /* r/w scratch */ 128#define DR0_PCXL2_DCSAFE 19 /* r/w serialize all data cache hangs */ 129#define DR0_PCXL2_ISTRM_EN 20 /* r/w I-cache streaming enable */ 130#define DR0_PCXL2_DUAL_DIS 22 /* r/w disable dual-issue (2 bit) */ 131#define DR0_PCXL2_ENDIAN 23 /* r/w little endian traps */ 132#define DR0_PCXL2_SOU_EN 24 /* r/w stall-on-use on dc misses */ 133#define DR0_PCXL2_SHINT_EN 25 /* r/w no-fill on miss store hints */ 134#define DR0_PCXL2_IPREF_EN 26 /* r/w L2 to L1 I-cache prefetch */ 135#define DR0_PCXL2_LMIN_EN 27 /* r/w minor ill insn traps on LIH */ 136#define DR0_PCXL2_RMIN_EN 28 /* r/w major ill insn traps on RIH */ 137#define DR0_PCXL2_L1CACHE_EN 29 /* r/w L1 I-cache enable */ 138 139#define CCR_MASK 0xff 140 141#define HPPA_NREGS (32) 142#define HPPA_NFPREGS (33) /* 33rd is used for r0 in fpemul */ 143 144#ifndef _LOCORE 145 146struct reg { 147 u_int32_t r_regs[HPPA_NREGS]; 148 /* p'bably some cr* ? */ 149}; 150 151struct fpreg { 152 u_int64_t fpr_regs[HPPA_NFPREGS]; 153}; 154#endif /* !_LOCORE */ 155 156#endif /* _MACHINE_REG_H_ */ 157