am335x.c revision 1.3 
1/* $OpenBSD: am335x.c,v 1.3 2013/10/10 19:40:02 syl Exp $ */
2
3/*
4 * Copyright (c) 2011 Uwe Stuehler <uwe@openbsd.org>
5 * Copyright (c) 2013 Raphael Graf <r@undefined.ch>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#include <sys/types.h>
21#include <sys/param.h>
22#include <machine/bus.h>
23
24#include <armv7/omap/omapvar.h>
25
26#define PRCM_SIZE	0x2000
27#define PRCM_ADDR	0x44E00000
28
29#define SCM_SIZE	0x2000
30#define SCM_ADDR	0x44E10000
31
32#define INTC_SIZE	0x300
33#define INTC_ADDR	0x48200000
34
35#define DMTIMERx_SIZE	0x80
36#define DMTIMER0_ADDR	0x44E05000
37#define DMTIMER1_ADDR	0x44E31000	/* 1MS */
38#define DMTIMER2_ADDR	0x48040000
39#define DMTIMER3_ADDR	0x48042000
40#define DMTIMER4_ADDR	0x48044000
41#define DMTIMER5_ADDR	0x48046000
42#define DMTIMER6_ADDR	0x48048000
43#define DMTIMER7_ADDR	0x4804A000
44#define DMTIMER0_IRQ	66
45#define DMTIMER1_IRQ	67
46#define DMTIMER2_IRQ	68
47#define DMTIMER3_IRQ	69
48#define DMTIMER4_IRQ	92
49#define DMTIMER5_IRQ	93
50#define DMTIMER6_IRQ	94
51#define DMTIMER7_IRQ	95
52
53#define WD_SIZE		0x80
54#define WD_ADDR		0x44E35000
55#define WD_IRQ		91
56
57#define GPIOx_SIZE	0x200
58#define GPIO0_ADDR	0x44E07000
59#define GPIO1_ADDR	0x4804C000
60#define GPIO2_ADDR	0x481AC000
61#define GPIO3_ADDR	0x481AE000
62#define GPIO0_IRQ	96
63#define GPIO1_IRQ	98
64#define GPIO2_IRQ	32
65#define GPIO3_IRQ	62
66
67#define TPCC_SIZE	0x100000
68#define TPCC_ADDR	0x49000000
69#define TPTC0_ADDR	0x49800000
70#define TPTC1_ADDR	0x49900000
71#define TPTC2_ADDR	0x49a00000
72#define EDMACOMP_IRQ	12
73#define EDMAMPERR_IRQ	13
74#define EDMAERR_IRQ	14
75
76#define UARTx_SIZE	0x90
77#define UART0_ADDR	0x44E09000
78#define UART1_ADDR	0x48022000
79#define UART2_ADDR	0x48024000
80#define UART3_ADDR	0x481A6000
81#define UART4_ADDR	0x481A8000
82#define UART5_ADDR	0x481AA000
83#define UART0_IRQ	72
84#define UART1_IRQ	73
85#define UART2_IRQ	74
86#define UART3_IRQ	44
87#define UART4_IRQ	45
88#define UART5_IRQ	46
89
90#define HSMMCx_SIZE	0x300
91#define HSMMC0_ADDR	0x48060000
92#define HSMMC1_ADDR	0x481d8000
93#define HSMMC0_IRQ	64
94#define HSMMC1_IRQ	28
95
96#define CPSW_SIZE	0x4000
97#define CPSW_ADDR	0x4A100000
98#define CPSW_IRQ	40
99
100struct omap_dev am335x_devs[] = {
101
102	/*
103	 * Power, Reset and Clock Manager
104	 */
105
106	{ .name = "prcm",
107	  .unit = 0,
108	  .mem = { { PRCM_ADDR, PRCM_SIZE } },
109	},
110
111	/*
112	 * System Control Module
113	 */
114
115	{ .name = "sitaracm",
116	  .unit = 0,
117	  .mem = { { SCM_ADDR, SCM_SIZE } },
118	},
119
120	/*
121	 * Interrupt Controller
122	 */
123
124	{ .name = "intc",
125	  .unit = 0,
126	  .mem = { { INTC_ADDR, INTC_SIZE } },
127	},
128
129	/*
130	 * EDMA Controller
131	 */
132	{ .name = "edma",
133	  .unit = 0,
134	  .mem = { { TPCC_ADDR, TPCC_SIZE } },
135	  .irq = { EDMACOMP_IRQ }
136	},
137
138	/*
139	 * General Purpose Timers
140	 */
141
142	{ .name = "dmtimer",
143	  .unit = 0,
144	  .mem = { { DMTIMER2_ADDR, DMTIMERx_SIZE } },
145	  .irq = { DMTIMER2_IRQ }
146	},
147
148	{ .name = "dmtimer",
149	  .unit = 1,
150	  .mem = { { DMTIMER3_ADDR, DMTIMERx_SIZE } },
151	  .irq = { DMTIMER3_IRQ }
152	},
153
154	/*
155	 * Watchdog Timer
156	 */
157
158	{ .name = "omdog",
159	  .unit = 0,
160	  .mem = { { WD_ADDR, WD_SIZE } }
161	},
162
163	/*
164	 * UART
165	 */
166
167	{ .name = "com",
168	  .unit = 0,
169	  .mem = { { UART0_ADDR, UARTx_SIZE } },
170	  .irq = { UART0_IRQ }
171	},
172
173	/*
174	 * MMC
175	 */
176
177	{ .name = "ommmc",
178	  .unit = 0,
179	  .mem = { { HSMMC0_ADDR, HSMMCx_SIZE } },
180	  .irq = { HSMMC0_IRQ }
181	},
182
183	{ .name = "ommmc",
184	  .unit = 1,
185	  .mem = { { HSMMC1_ADDR, HSMMCx_SIZE } },
186	  .irq = { HSMMC1_IRQ }
187	},
188
189	/* cpsw Ethernet */
190	{ .name = "cpsw",
191	  .unit = 0,
192	  .mem = { { CPSW_ADDR, CPSW_SIZE } },
193	  .irq = { CPSW_IRQ }
194	},
195
196	/* Terminator */
197	{ .name = NULL,
198	  .unit = 0
199	}
200};
201
202void
203am335x_init(void)
204{
205	omap_set_devs(am335x_devs);
206}
207