armreg.h revision 1.7
1/* $OpenBSD: armreg.h,v 1.7 2018/08/25 20:45:28 kettenis Exp $ */ 2/*- 3 * Copyright (c) 2013, 2014 Andrew Turner 4 * Copyright (c) 2015 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Andrew Turner under 8 * sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm64/include/armreg.h 309248 2016-11-28 14:24:07Z andrew $ 32 */ 33 34#ifndef _MACHINE_ARMREG_H_ 35#define _MACHINE_ARMREG_H_ 36 37#define INSN_SIZE 4 38 39#define READ_SPECIALREG(reg) \ 40({ uint64_t val; \ 41 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \ 42 val; \ 43}) 44#define WRITE_SPECIALREG(reg, val) \ 45 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val)) 46 47/* CCSIDR_EL1 - Current Cache Size ID Register */ 48#define CCSIDR_SETS_MASK 0x0fffe000 49#define CCSIDR_SETS_SHIFT 13 50#define CCSIDR_SETS(reg) \ 51 ((((reg) & CCSIDR_SETS_MASK) >> CCSIDR_SETS_SHIFT) + 1) 52#define CCSIDR_WAYS_MASK 0x00001ff8 53#define CCSIDR_WAYS_SHIFT 3 54#define CCSIDR_WAYS(reg) \ 55 ((((reg) & CCSIDR_WAYS_MASK) >> CCSIDR_WAYS_SHIFT) + 1) 56#define CCSIDR_LINE_MASK 0x00000007 57#define CCSIDR_LINE_SIZE(reg) (1 << (((reg) & CCSIDR_LINE_MASK) + 4)) 58 59/* CLIDR_EL1 - Cache Level ID Register */ 60#define CLIDR_CTYPE_MASK 0x7 61#define CLIDR_CTYPE_INSN 0x1 62#define CLIDR_CTYPE_DATA 0x2 63#define CLIDR_CTYPE_UNIFIED 0x4 64 65/* CNTHCTL_EL2 - Counter-timer Hypervisor Control Register */ 66#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 67#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 68#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 69#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 70#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 71 72/* CPACR_EL1 */ 73#define CPACR_FPEN_MASK (0x3 << 20) 74#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 75#define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 76#define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 77#define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 78#define CPACR_TTA (0x1 << 28) 79 80/* CSSELR_EL1 - Cache Size Selection Register */ 81#define CSSELR_IND (1 << 0) 82#define CSSELR_LEVEL_SHIFT 1 83 84/* CTR_EL0 - Cache Type Register */ 85#define CTR_DLINE_SHIFT 16 86#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 87#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) 88#define CTR_IL1P_SHIFT 14 89#define CTR_IL1P_MASK (0x3 << CTR_IL1P_SHIFT) 90#define CTR_IL1P_AIVIVT (0x1 << CTR_IL1P_SHIFT) 91#define CTR_IL1P_VIPT (0x2 << CTR_IL1P_SHIFT) 92#define CTR_IL1P_PIPT (0x3 << CTR_IL1P_SHIFT) 93#define CTR_ILINE_SHIFT 0 94#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 95#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) 96 97/* MPIDR_EL1 - Multiprocessor Affinity Register */ 98#define MPIDR_AFF3 (0xFFULL << 32) 99#define MPIDR_AFF2 (0xFFULL << 16) 100#define MPIDR_AFF1 (0xFFULL << 8) 101#define MPIDR_AFF0 (0xFFULL << 0) 102#define MPIDR_AFF (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0) 103 104/* DCZID_EL0 - Data Cache Zero ID register */ 105#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 106#define DCZID_BS_SHIFT 0 107#define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 108#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 109 110/* ESR_ELx */ 111#define ESR_ELx_ISS_MASK 0x00ffffff 112#define ISS_INSN_FnV (0x01 << 10) 113#define ISS_INSN_EA (0x01 << 9) 114#define ISS_INSN_S1PTW (0x01 << 7) 115#define ISS_INSN_IFSC_MASK (0x1f << 0) 116#define ISS_DATA_ISV (0x01 << 24) 117#define ISS_DATA_SAS_MASK (0x03 << 22) 118#define ISS_DATA_SSE (0x01 << 21) 119#define ISS_DATA_SRT_MASK (0x1f << 16) 120#define ISS_DATA_SF (0x01 << 15) 121#define ISS_DATA_AR (0x01 << 14) 122#define ISS_DATA_FnV (0x01 << 10) 123#define ISS_DATa_EA (0x01 << 9) 124#define ISS_DATa_CM (0x01 << 8) 125#define ISS_INSN_S1PTW (0x01 << 7) 126#define ISS_DATa_WnR (0x01 << 6) 127#define ISS_DATA_DFSC_MASK (0x3f << 0) 128#define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 129#define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 130#define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 131#define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 132#define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 133#define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 134#define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 135#define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 136#define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 137#define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 138#define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 139#define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 140#define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 141#define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 142#define ISS_DATA_DFSC_EXT (0x10 << 0) 143#define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 144#define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 145#define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 146#define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 147#define ISS_DATA_DFSC_ECC (0x18 << 0) 148#define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 149#define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 150#define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 151#define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 152#define ISS_DATA_DFSC_ALIGN (0x21 << 0) 153#define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 154#define ESR_ELx_IL (0x01 << 25) 155#define ESR_ELx_EC_SHIFT 26 156#define ESR_ELx_EC_MASK (0x3f << 26) 157#define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 158#define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 159#define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ 160#define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 161#define EXCP_SVC 0x15 /* SVC trap */ 162#define EXCP_MSR 0x18 /* MSR/MRS trap */ 163#define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 164#define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 165#define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 166#define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 167#define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 168#define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ 169#define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 170#define EXCP_SERROR 0x2f /* SError interrupt */ 171#define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 172#define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 173#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 174#define EXCP_BRK 0x3c /* Breakpoint */ 175 176/* ICC_CTLR_EL1 */ 177#define ICC_CTLR_EL1_EOIMODE (1U << 1) 178 179/* ICC_IAR1_EL1 */ 180#define ICC_IAR1_EL1_SPUR (0x03ff) 181 182/* ICC_IGRPEN0_EL1 */ 183#define ICC_IGRPEN0_EL1_EN (1U << 0) 184 185/* ICC_PMR_EL1 */ 186#define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 187 188/* ICC_SGI1R_EL1 */ 189#define ICC_SGI1R_EL1_TL_MASK 0xffffUL 190#define ICC_SGI1R_EL1_AFF1_SHIFT 16 191#define ICC_SGI1R_EL1_SGIID_SHIFT 24 192#define ICC_SGI1R_EL1_AFF2_SHIFT 32 193#define ICC_SGI1R_EL1_AFF3_SHIFT 48 194#define ICC_SGI1R_EL1_SGIID_MASK 0xfUL 195#define ICC_SGI1R_EL1_IRM (0x1UL << 40) 196 197/* ICC_SRE_EL1 */ 198#define ICC_SRE_EL1_SRE (1U << 0) 199 200/* ICC_SRE_EL2 */ 201#define ICC_SRE_EL2_SRE (1U << 0) 202#define ICC_SRE_EL2_EN (1U << 3) 203 204/* ID_AA64DFR0_EL1 */ 205#define ID_AA64DFR0_MASK 0xf0f0ffff 206#define ID_AA64DFR0_DEBUG_VER_SHIFT 0 207#define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT) 208#define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) 209#define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT) 210#define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT) 211#define ID_AA64DFR0_TRACE_VER_SHIFT 4 212#define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT) 213#define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) 214#define ID_AA64DFR0_TRACE_VER_NONE (0x0 << ID_AA64DFR0_TRACE_VER_SHIFT) 215#define ID_AA64DFR0_TRACE_VER_IMPL (0x1 << ID_AA64DFR0_TRACE_VER_SHIFT) 216#define ID_AA64DFR0_PMU_VER_SHIFT 8 217#define ID_AA64DFR0_PMU_VER_MASK (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 218#define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK) 219#define ID_AA64DFR0_PMU_VER_NONE (0x0 << ID_AA64DFR0_PMU_VER_SHIFT) 220#define ID_AA64DFR0_PMU_VER_3 (0x1 << ID_AA64DFR0_PMU_VER_SHIFT) 221#define ID_AA64DFR0_PMU_VER_3_1 (0x4 << ID_AA64DFR0_PMU_VER_SHIFT) 222#define ID_AA64DFR0_PMU_VER_IMPL (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 223#define ID_AA64DFR0_BRPS_SHIFT 12 224#define ID_AA64DFR0_BRPS_MASK (0xf << ID_AA64DFR0_BRPS_SHIFT) 225#define ID_AA64DFR0_BRPS(x) \ 226 ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1) 227#define ID_AA64DFR0_WRPS_SHIFT 20 228#define ID_AA64DFR0_WRPS_MASK (0xf << ID_AA64DFR0_WRPS_SHIFT) 229#define ID_AA64DFR0_WRPS(x) \ 230 ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1) 231#define ID_AA64DFR0_CTX_CMPS_SHIFT 28 232#define ID_AA64DFR0_CTX_CMPS_MASK (0xf << ID_AA64DFR0_CTX_CMPS_SHIFT) 233#define ID_AA64DFR0_CTX_CMPS(x) \ 234 ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) 235 236/* ID_AA64ISAR0_EL1 */ 237#define ID_AA64ISAR0_MASK 0xf0fffff0 238#define ID_AA64ISAR0_AES_SHIFT 4 239#define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT) 240#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) 241#define ID_AA64ISAR0_AES_NONE (0x0 << ID_AA64ISAR0_AES_SHIFT) 242#define ID_AA64ISAR0_AES_BASE (0x1 << ID_AA64ISAR0_AES_SHIFT) 243#define ID_AA64ISAR0_AES_PMULL (0x2 << ID_AA64ISAR0_AES_SHIFT) 244#define ID_AA64ISAR0_SHA1_SHIFT 8 245#define ID_AA64ISAR0_SHA1_MASK (0xf << ID_AA64ISAR0_SHA1_SHIFT) 246#define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 247#define ID_AA64ISAR0_SHA1_NONE (0x0 << ID_AA64ISAR0_SHA1_SHIFT) 248#define ID_AA64ISAR0_SHA1_BASE (0x1 << ID_AA64ISAR0_SHA1_SHIFT) 249#define ID_AA64ISAR0_SHA2_SHIFT 12 250#define ID_AA64ISAR0_SHA2_MASK (0xf << ID_AA64ISAR0_SHA2_SHIFT) 251#define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 252#define ID_AA64ISAR0_SHA2_NONE (0x0 << ID_AA64ISAR0_SHA2_SHIFT) 253#define ID_AA64ISAR0_SHA2_BASE (0x1 << ID_AA64ISAR0_SHA2_SHIFT) 254#define ID_AA64ISAR0_CRC32_SHIFT 16 255#define ID_AA64ISAR0_CRC32_MASK (0xf << ID_AA64ISAR0_CRC32_SHIFT) 256#define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 257#define ID_AA64ISAR0_CRC32_NONE (0x0 << ID_AA64ISAR0_CRC32_SHIFT) 258#define ID_AA64ISAR0_CRC32_BASE (0x1 << ID_AA64ISAR0_CRC32_SHIFT) 259#define ID_AA64ISAR0_ATOMIC_SHIFT 20 260#define ID_AA64ISAR0_ATOMIC_MASK (0xf << ID_AA64ISAR0_ATOMIC_SHIFT) 261#define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK) 262#define ID_AA64ISAR0_ATOMIC_NONE (0x0 << ID_AA64ISAR0_ATOMIC_SHIFT) 263#define ID_AA64ISAR0_ATOMIC_IMPL (0x2 << ID_AA64ISAR0_ATOMIC_SHIFT) 264#define ID_AA64ISAR0_RDM_SHIFT 28 265#define ID_AA64ISAR0_RDM_MASK (0xf << ID_AA64ISAR0_RDM_SHIFT) 266#define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK) 267#define ID_AA64ISAR0_RDM_NONE (0x0 << ID_AA64ISAR0_RDM_SHIFT) 268#define ID_AA64ISAR0_RDM_IMPL (0x1 << ID_AA64ISAR0_RDM_SHIFT) 269 270/* ID_AA64MMFR0_EL1 */ 271#define ID_AA64MMFR0_MASK 0xffffffff 272#define ID_AA64MMFR0_PA_RANGE_SHIFT 0 273#define ID_AA64MMFR0_PA_RANGE_MASK (0xf << ID_AA64MMFR0_PA_RANGE_SHIFT) 274#define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK) 275#define ID_AA64MMFR0_PA_RANGE_4G (0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT) 276#define ID_AA64MMFR0_PA_RANGE_64G (0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT) 277#define ID_AA64MMFR0_PA_RANGE_1T (0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT) 278#define ID_AA64MMFR0_PA_RANGE_4T (0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT) 279#define ID_AA64MMFR0_PA_RANGE_16T (0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT) 280#define ID_AA64MMFR0_PA_RANGE_256T (0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT) 281#define ID_AA64MMFR0_ASID_BITS_SHIFT 4 282#define ID_AA64MMFR0_ASID_BITS_MASK (0xf << ID_AA64MMFR0_ASID_BITS_SHIFT) 283#define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK) 284#define ID_AA64MMFR0_ASID_BITS_8 (0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT) 285#define ID_AA64MMFR0_ASID_BITS_16 (0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT) 286#define ID_AA64MMFR0_BIGEND_SHIFT 8 287#define ID_AA64MMFR0_BIGEND_MASK (0xf << ID_AA64MMFR0_BIGEND_SHIFT) 288#define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK) 289#define ID_AA64MMFR0_BIGEND_FIXED (0x0 << ID_AA64MMFR0_BIGEND_SHIFT) 290#define ID_AA64MMFR0_BIGEND_MIXED (0x1 << ID_AA64MMFR0_BIGEND_SHIFT) 291#define ID_AA64MMFR0_S_NS_MEM_SHIFT 12 292#define ID_AA64MMFR0_S_NS_MEM_MASK (0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT) 293#define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK) 294#define ID_AA64MMFR0_S_NS_MEM_NONE (0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 295#define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 296#define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16 297#define ID_AA64MMFR0_BIGEND_EL0_MASK (0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 298#define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK) 299#define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 300#define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 301#define ID_AA64MMFR0_TGRAN16_SHIFT 20 302#define ID_AA64MMFR0_TGRAN16_MASK (0xf << ID_AA64MMFR0_TGRAN16_SHIFT) 303#define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK) 304#define ID_AA64MMFR0_TGRAN16_NONE (0x0 << ID_AA64MMFR0_TGRAN16_SHIFT) 305#define ID_AA64MMFR0_TGRAN16_IMPL (0x1 << ID_AA64MMFR0_TGRAN16_SHIFT) 306#define ID_AA64MMFR0_TGRAN64_SHIFT 24 307#define ID_AA64MMFR0_TGRAN64_MASK (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 308#define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK) 309#define ID_AA64MMFR0_TGRAN64_IMPL (0x0 << ID_AA64MMFR0_TGRAN64_SHIFT) 310#define ID_AA64MMFR0_TGRAN64_NONE (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 311#define ID_AA64MMFR0_TGRAN4_SHIFT 28 312#define ID_AA64MMFR0_TGRAN4_MASK (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 313#define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK) 314#define ID_AA64MMFR0_TGRAN4_IMPL (0x0 << ID_AA64MMFR0_TGRAN4_SHIFT) 315#define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 316 317/* ID_AA64MMFR1_EL1 */ 318#define ID_AA64MMFR1_MASK 0x00ffffff 319#define ID_AA64MMFR1_HAFDBS_SHIFT 0 320#define ID_AA64MMFR1_HAFDBS_MASK (0xf << ID_AA64MMFR1_HAFDBS_SHIFT) 321#define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 322#define ID_AA64MMFR1_HAFDBS_NONE (0x0 << ID_AA64MMFR1_HAFDBS_SHIFT) 323#define ID_AA64MMFR1_HAFDBS_AF (0x1 << ID_AA64MMFR1_HAFDBS_SHIFT) 324#define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2 << ID_AA64MMFR1_HAFDBS_SHIFT) 325#define ID_AA64MMFR1_VMIDBITS_SHIFT 4 326#define ID_AA64MMFR1_VMIDBITS_MASK (0xf << ID_AA64MMFR1_VMIDBITS_SHIFT) 327#define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK) 328#define ID_AA64MMFR1_VMIDBITS_8 (0x0 << ID_AA64MMFR1_VMIDBITS_SHIFT) 329#define ID_AA64MMFR1_VMIDBITS_16 (0x2 << ID_AA64MMFR1_VMIDBITS_SHIFT) 330#define ID_AA64MMFR1_VH_SHIFT 8 331#define ID_AA64MMFR1_VH_MASK (0xf << ID_AA64MMFR1_VH_SHIFT) 332#define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK) 333#define ID_AA64MMFR1_VH_NONE (0x0 << ID_AA64MMFR1_VH_SHIFT) 334#define ID_AA64MMFR1_VH_IMPL (0x1 << ID_AA64MMFR1_VH_SHIFT) 335#define ID_AA64MMFR1_HPDS_SHIFT 12 336#define ID_AA64MMFR1_HPDS_MASK (0xf << ID_AA64MMFR1_HPDS_SHIFT) 337#define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 338#define ID_AA64MMFR1_HPDS_NONE (0x0 << ID_AA64MMFR1_HPDS_SHIFT) 339#define ID_AA64MMFR1_HPDS_IMPL (0x1 << ID_AA64MMFR1_HPDS_SHIFT) 340#define ID_AA64MMFR1_LO_SHIFT 16 341#define ID_AA64MMFR1_LO_MASK (0xf << ID_AA64MMFR1_LO_SHIFT) 342#define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK) 343#define ID_AA64MMFR1_LO_NONE (0x0 << ID_AA64MMFR1_LO_SHIFT) 344#define ID_AA64MMFR1_LO_IMPL (0x1 << ID_AA64MMFR1_LO_SHIFT) 345#define ID_AA64MMFR1_PAN_SHIFT 20 346#define ID_AA64MMFR1_PAN_MASK (0xf << ID_AA64MMFR1_PAN_SHIFT) 347#define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK) 348#define ID_AA64MMFR1_PAN_NONE (0x0 << ID_AA64MMFR1_PAN_SHIFT) 349#define ID_AA64MMFR1_PAN_IMPL (0x1 << ID_AA64MMFR1_PAN_SHIFT) 350 351/* ID_AA64PFR0_EL1 */ 352#define ID_AA64PFR0_MASK 0x0fffffff 353#define ID_AA64PFR0_EL0_SHIFT 0 354#define ID_AA64PFR0_EL0_MASK (0xf << ID_AA64PFR0_EL0_SHIFT) 355#define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) 356#define ID_AA64PFR0_EL0_64 (1 << ID_AA64PFR0_EL0_SHIFT) 357#define ID_AA64PFR0_EL0_64_32 (2 << ID_AA64PFR0_EL0_SHIFT) 358#define ID_AA64PFR0_EL1_SHIFT 4 359#define ID_AA64PFR0_EL1_MASK (0xf << ID_AA64PFR0_EL1_SHIFT) 360#define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK) 361#define ID_AA64PFR0_EL1_64 (1 << ID_AA64PFR0_EL1_SHIFT) 362#define ID_AA64PFR0_EL1_64_32 (2 << ID_AA64PFR0_EL1_SHIFT) 363#define ID_AA64PFR0_EL2_SHIFT 8 364#define ID_AA64PFR0_EL2_MASK (0xf << ID_AA64PFR0_EL2_SHIFT) 365#define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK) 366#define ID_AA64PFR0_EL2_NONE (0 << ID_AA64PFR0_EL2_SHIFT) 367#define ID_AA64PFR0_EL2_64 (1 << ID_AA64PFR0_EL2_SHIFT) 368#define ID_AA64PFR0_EL2_64_32 (2 << ID_AA64PFR0_EL2_SHIFT) 369#define ID_AA64PFR0_EL3_SHIFT 12 370#define ID_AA64PFR0_EL3_MASK (0xf << ID_AA64PFR0_EL3_SHIFT) 371#define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK) 372#define ID_AA64PFR0_EL3_NONE (0 << ID_AA64PFR0_EL3_SHIFT) 373#define ID_AA64PFR0_EL3_64 (1 << ID_AA64PFR0_EL3_SHIFT) 374#define ID_AA64PFR0_EL3_64_32 (2 << ID_AA64PFR0_EL3_SHIFT) 375#define ID_AA64PFR0_FP_SHIFT 16 376#define ID_AA64PFR0_FP_MASK (0xf << ID_AA64PFR0_FP_SHIFT) 377#define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) 378#define ID_AA64PFR0_FP_IMPL (0x0 << ID_AA64PFR0_FP_SHIFT) 379#define ID_AA64PFR0_FP_NONE (0xf << ID_AA64PFR0_FP_SHIFT) 380#define ID_AA64PFR0_ADV_SIMD_SHIFT 20 381#define ID_AA64PFR0_ADV_SIMD_MASK (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 382#define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK) 383#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT) 384#define ID_AA64PFR0_ADV_SIMD_NONE (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 385#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 386#define ID_AA64PFR0_GIC_SHIFT 24 387#define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT) 388#define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) 389#define ID_AA64PFR0_GIC_CPUIF_NONE (0x0 << ID_AA64PFR0_GIC_SHIFT) 390#define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT) 391 392/* MAIR_EL1 - Memory Attribute Indirection Register */ 393#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 394#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 395#define MAIR_DEVICE_nGnRnE 0x00 396#define MAIR_NORMAL_NC 0x44 397#define MAIR_NORMAL_WT 0x88 398#define MAIR_NORMAL_WB 0xff 399 400/* PAR_EL1 - Physical Address Register */ 401#define PAR_F_SHIFT 0 402#define PAR_F (0x1 << PAR_F_SHIFT) 403#define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 404/* When PAR_F == 0 (success) */ 405#define PAR_SH_SHIFT 7 406#define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 407#define PAR_NS_SHIFT 9 408#define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 409#define PAR_PA_SHIFT 12 410#define PAR_PA_MASK 0x0000fffffffff000 411#define PAR_ATTR_SHIFT 56 412#define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 413/* When PAR_F == 1 (aborted) */ 414#define PAR_FST_SHIFT 1 415#define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 416#define PAR_PTW_SHIFT 8 417#define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 418#define PAR_S_SHIFT 9 419#define PAR_S_MASK (0x1 << PAR_S_SHIFT) 420 421/* SCTLR_EL1 - System Control Register */ 422#define SCTLR_RES0 0xc8222400 /* Reserved, write 0 */ 423#define SCTLR_RES1 0x30d00800 /* Reserved, write 1 */ 424 425#define SCTLR_M 0x00000001 426#define SCTLR_A 0x00000002 427#define SCTLR_C 0x00000004 428#define SCTLR_SA 0x00000008 429#define SCTLR_SA0 0x00000010 430#define SCTLR_CP15BEN 0x00000020 431#define SCTLR_THEE 0x00000040 432#define SCTLR_ITD 0x00000080 433#define SCTLR_SED 0x00000100 434#define SCTLR_UMA 0x00000200 435#define SCTLR_I 0x00001000 436#define SCTLR_DZE 0x00004000 437#define SCTLR_UCT 0x00008000 438#define SCTLR_nTWI 0x00010000 439#define SCTLR_nTWE 0x00040000 440#define SCTLR_WXN 0x00080000 441#define SCTLR_EOE 0x01000000 442#define SCTLR_EE 0x02000000 443#define SCTLR_UCI 0x04000000 444 445/* SPSR_EL1 */ 446/* 447 * When the exception is taken in AArch64: 448 * M[4] is 0 for AArch64 mode 449 * M[3:2] is the exception level 450 * M[1] is unused 451 * M[0] is the SP select: 452 * 0: always SP0 453 * 1: current ELs SP 454 */ 455#define PSR_M_EL0t 0x00000000 456#define PSR_M_EL1t 0x00000004 457#define PSR_M_EL1h 0x00000005 458#define PSR_M_EL2t 0x00000008 459#define PSR_M_EL2h 0x00000009 460#define PSR_M_MASK 0x0000001f 461 462#define PSR_F 0x00000040 463#define PSR_I 0x00000080 464#define PSR_A 0x00000100 465#define PSR_D 0x00000200 466#define PSR_IL 0x00100000 467#define PSR_SS 0x00200000 468#define PSR_V 0x10000000 469#define PSR_C 0x20000000 470#define PSR_Z 0x40000000 471#define PSR_N 0x80000000 472 473/* TCR_EL1 - Translation Control Register */ 474#define TCR_AS (1UL << 36) 475 476#define TCR_IPS_SHIFT 32 477#define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT) 478#define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT) 479#define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT) 480#define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT) 481#define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) 482#define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) 483 484#define TCR_TG1_SHIFT 30 485#define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) 486#define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) 487#define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) 488 489#define TCR_SH1_SHIFT 28 490#define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) 491#define TCR_ORGN1_SHIFT 26 492#define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) 493#define TCR_IRGN1_SHIFT 24 494#define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) 495 496#define TCR_A1 (1UL << 22) 497 498#define TCR_TG0_SHIFT 14 499#define TCR_TG0_16K (1UL << TCR_TG0_SHIFT) 500#define TCR_TG0_4K (2UL << TCR_TG0_SHIFT) 501#define TCR_TG0_64K (3UL << TCR_TG0_SHIFT) 502 503#define TCR_SH0_SHIFT 12 504#define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) 505#define TCR_ORGN0_SHIFT 10 506#define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) 507#define TCR_IRGN0_SHIFT 8 508#define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) 509 510#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 511 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 512#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 513 514#define TCR_T1SZ_SHIFT 16 515#define TCR_T0SZ_SHIFT 0 516#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 517#define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 518#define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 519 520/* Monitor Debug System Control Register */ 521#define DBG_MDSCR_SS (0x1 << 0) 522#define DBG_MDSCR_TDCC (0x1 << 12) 523#define DBG_MDSCR_KDE (0x1 << 13) 524#define DBG_MDSCR_MDE (0x1 << 15) 525 526/* Perfomance Monitoring Counters */ 527#define PMCR_E (1 << 0) /* Enable all counters */ 528#define PMCR_P (1 << 1) /* Reset all counters */ 529#define PMCR_C (1 << 2) /* Clock counter reset */ 530#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 531#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 532#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 533#define PMCR_LC (1 << 6) /* Long cycle count enable */ 534#define PMCR_IMP_SHIFT 24 /* Implementer code */ 535#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 536#define PMCR_IDCODE_SHIFT 16 /* Identification code */ 537#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 538#define PMCR_IDCODE_CORTEX_A57 0x01 539#define PMCR_IDCODE_CORTEX_A72 0x02 540#define PMCR_IDCODE_CORTEX_A53 0x03 541#define PMCR_N_SHIFT 11 /* Number of counters implemented */ 542#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 543 544/* Individual CPUs are probably best IDed by everything but the revision. */ 545#define CPU_ID_CPU_MASK 0xfffffff0 546 547/* ARM64 CPUs */ 548#define CPU_ID_CORTEX_A53 0x410fd030 549#define CPU_ID_CORTEX_A53_R1 0x411fd030 550#define CPU_ID_CORTEX_A53_MASK 0xff0ffff0 551#define CPU_ID_CORTEX_A57 0x410fd070 552#define CPU_ID_CORTEX_A57_R1 0x411fd070 553#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 554#define CPU_ID_CORTEX_A72 0x410fd080 555#define CPU_ID_CORTEX_A72_R1 0x411fd080 556#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 557 558#define I_bit (1 << 7) /* IRQ disable */ 559#define F_bit 0 /* FIQ disable - not actually used */ 560 561#endif /* !_MACHINE_ARMREG_H_ */ 562