armreg.h revision 1.4
1/* $OpenBSD: armreg.h,v 1.4 2017/04/27 10:23:19 kettenis Exp $ */ 2/*- 3 * Copyright (c) 2013, 2014 Andrew Turner 4 * Copyright (c) 2015 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Andrew Turner under 8 * sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm64/include/armreg.h 309248 2016-11-28 14:24:07Z andrew $ 32 */ 33 34#ifndef _MACHINE_ARMREG_H_ 35#define _MACHINE_ARMREG_H_ 36 37#define INSN_SIZE 4 38 39#define READ_SPECIALREG(reg) \ 40({ uint64_t val; \ 41 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \ 42 val; \ 43}) 44#define WRITE_SPECIALREG(reg, val) \ 45 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val)) 46 47/* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ 48#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 49#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 50#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 51#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 52#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 53 54/* CPACR_EL1 */ 55#define CPACR_FPEN_MASK (0x3 << 20) 56#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 57#define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 58#define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 59#define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 60#define CPACR_TTA (0x1 << 28) 61 62/* CTR_EL0 - Cache Type Register */ 63#define CTR_DLINE_SHIFT 16 64#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 65#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) 66#define CTR_ILINE_SHIFT 0 67#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 68#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) 69 70/* MPIDR_EL1 - Multiprocessor Affinity Register */ 71#define MPIDR_AFF3 (0xFFULL << 32) 72#define MPIDR_AFF2 (0xFFULL << 16) 73#define MPIDR_AFF1 (0xFFULL << 8) 74#define MPIDR_AFF0 (0xFFULL << 0) 75#define MPIDR_AFF (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0) 76 77/* DCZID_EL0 - Data Cache Zero ID register */ 78#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 79#define DCZID_BS_SHIFT 0 80#define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 81#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 82 83/* ESR_ELx */ 84#define ESR_ELx_ISS_MASK 0x00ffffff 85#define ISS_INSN_FnV (0x01 << 10) 86#define ISS_INSN_EA (0x01 << 9) 87#define ISS_INSN_S1PTW (0x01 << 7) 88#define ISS_INSN_IFSC_MASK (0x1f << 0) 89#define ISS_DATA_ISV (0x01 << 24) 90#define ISS_DATA_SAS_MASK (0x03 << 22) 91#define ISS_DATA_SSE (0x01 << 21) 92#define ISS_DATA_SRT_MASK (0x1f << 16) 93#define ISS_DATA_SF (0x01 << 15) 94#define ISS_DATA_AR (0x01 << 14) 95#define ISS_DATA_FnV (0x01 << 10) 96#define ISS_DATa_EA (0x01 << 9) 97#define ISS_DATa_CM (0x01 << 8) 98#define ISS_INSN_S1PTW (0x01 << 7) 99#define ISS_DATa_WnR (0x01 << 6) 100#define ISS_DATA_DFSC_MASK (0x3f << 0) 101#define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 102#define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 103#define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 104#define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 105#define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 106#define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 107#define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 108#define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 109#define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 110#define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 111#define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 112#define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 113#define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 114#define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 115#define ISS_DATA_DFSC_EXT (0x10 << 0) 116#define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 117#define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 118#define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 119#define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 120#define ISS_DATA_DFSC_ECC (0x18 << 0) 121#define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 122#define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 123#define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 124#define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 125#define ISS_DATA_DFSC_ALIGN (0x21 << 0) 126#define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 127#define ESR_ELx_IL (0x01 << 25) 128#define ESR_ELx_EC_SHIFT 26 129#define ESR_ELx_EC_MASK (0x3f << 26) 130#define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 131#define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 132#define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ 133#define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 134#define EXCP_SVC 0x15 /* SVC trap */ 135#define EXCP_MSR 0x18 /* MSR/MRS trap */ 136#define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 137#define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 138#define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 139#define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 140#define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 141#define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ 142#define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 143#define EXCP_SERROR 0x2f /* SError interrupt */ 144#define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 145#define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 146#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 147#define EXCP_BRK 0x3c /* Breakpoint */ 148 149/* ICC_CTLR_EL1 */ 150#define ICC_CTLR_EL1_EOIMODE (1U << 1) 151 152/* ICC_IAR1_EL1 */ 153#define ICC_IAR1_EL1_SPUR (0x03ff) 154 155/* ICC_IGRPEN0_EL1 */ 156#define ICC_IGRPEN0_EL1_EN (1U << 0) 157 158/* ICC_PMR_EL1 */ 159#define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 160 161/* ICC_SGI1R_EL1 */ 162#define ICC_SGI1R_EL1_TL_MASK 0xffffUL 163#define ICC_SGI1R_EL1_AFF1_SHIFT 16 164#define ICC_SGI1R_EL1_SGIID_SHIFT 24 165#define ICC_SGI1R_EL1_AFF2_SHIFT 32 166#define ICC_SGI1R_EL1_AFF3_SHIFT 48 167#define ICC_SGI1R_EL1_SGIID_MASK 0xfUL 168#define ICC_SGI1R_EL1_IRM (0x1UL << 40) 169 170/* ICC_SRE_EL1 */ 171#define ICC_SRE_EL1_SRE (1U << 0) 172 173/* ICC_SRE_EL2 */ 174#define ICC_SRE_EL2_SRE (1U << 0) 175#define ICC_SRE_EL2_EN (1U << 3) 176 177/* ID_AA64DFR0_EL1 */ 178#define ID_AA64DFR0_MASK 0xf0f0ffff 179#define ID_AA64DFR0_DEBUG_VER_SHIFT 0 180#define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT) 181#define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) 182#define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT) 183#define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT) 184#define ID_AA64DFR0_TRACE_VER_SHIFT 4 185#define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT) 186#define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) 187#define ID_AA64DFR0_TRACE_VER_NONE (0x0 << ID_AA64DFR0_TRACE_VER_SHIFT) 188#define ID_AA64DFR0_TRACE_VER_IMPL (0x1 << ID_AA64DFR0_TRACE_VER_SHIFT) 189#define ID_AA64DFR0_PMU_VER_SHIFT 8 190#define ID_AA64DFR0_PMU_VER_MASK (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 191#define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK) 192#define ID_AA64DFR0_PMU_VER_NONE (0x0 << ID_AA64DFR0_PMU_VER_SHIFT) 193#define ID_AA64DFR0_PMU_VER_3 (0x1 << ID_AA64DFR0_PMU_VER_SHIFT) 194#define ID_AA64DFR0_PMU_VER_3_1 (0x4 << ID_AA64DFR0_PMU_VER_SHIFT) 195#define ID_AA64DFR0_PMU_VER_IMPL (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 196#define ID_AA64DFR0_BRPS_SHIFT 12 197#define ID_AA64DFR0_BRPS_MASK (0xf << ID_AA64DFR0_BRPS_SHIFT) 198#define ID_AA64DFR0_BRPS(x) \ 199 ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1) 200#define ID_AA64DFR0_WRPS_SHIFT 20 201#define ID_AA64DFR0_WRPS_MASK (0xf << ID_AA64DFR0_WRPS_SHIFT) 202#define ID_AA64DFR0_WRPS(x) \ 203 ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1) 204#define ID_AA64DFR0_CTX_CMPS_SHIFT 28 205#define ID_AA64DFR0_CTX_CMPS_MASK (0xf << ID_AA64DFR0_CTX_CMPS_SHIFT) 206#define ID_AA64DFR0_CTX_CMPS(x) \ 207 ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) 208 209/* ID_AA64ISAR0_EL1 */ 210#define ID_AA64ISAR0_MASK 0xf0fffff0 211#define ID_AA64ISAR0_AES_SHIFT 4 212#define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT) 213#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) 214#define ID_AA64ISAR0_AES_NONE (0x0 << ID_AA64ISAR0_AES_SHIFT) 215#define ID_AA64ISAR0_AES_BASE (0x1 << ID_AA64ISAR0_AES_SHIFT) 216#define ID_AA64ISAR0_AES_PMULL (0x2 << ID_AA64ISAR0_AES_SHIFT) 217#define ID_AA64ISAR0_SHA1_SHIFT 8 218#define ID_AA64ISAR0_SHA1_MASK (0xf << ID_AA64ISAR0_SHA1_SHIFT) 219#define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 220#define ID_AA64ISAR0_SHA1_NONE (0x0 << ID_AA64ISAR0_SHA1_SHIFT) 221#define ID_AA64ISAR0_SHA1_BASE (0x1 << ID_AA64ISAR0_SHA1_SHIFT) 222#define ID_AA64ISAR0_SHA2_SHIFT 12 223#define ID_AA64ISAR0_SHA2_MASK (0xf << ID_AA64ISAR0_SHA2_SHIFT) 224#define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 225#define ID_AA64ISAR0_SHA2_NONE (0x0 << ID_AA64ISAR0_SHA2_SHIFT) 226#define ID_AA64ISAR0_SHA2_BASE (0x1 << ID_AA64ISAR0_SHA2_SHIFT) 227#define ID_AA64ISAR0_CRC32_SHIFT 16 228#define ID_AA64ISAR0_CRC32_MASK (0xf << ID_AA64ISAR0_CRC32_SHIFT) 229#define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 230#define ID_AA64ISAR0_CRC32_NONE (0x0 << ID_AA64ISAR0_CRC32_SHIFT) 231#define ID_AA64ISAR0_CRC32_BASE (0x1 << ID_AA64ISAR0_CRC32_SHIFT) 232#define ID_AA64ISAR0_ATOMIC_SHIFT 20 233#define ID_AA64ISAR0_ATOMIC_MASK (0xf << ID_AA64ISAR0_ATOMIC_SHIFT) 234#define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK) 235#define ID_AA64ISAR0_ATOMIC_NONE (0x0 << ID_AA64ISAR0_ATOMIC_SHIFT) 236#define ID_AA64ISAR0_ATOMIC_IMPL (0x2 << ID_AA64ISAR0_ATOMIC_SHIFT) 237#define ID_AA64ISAR0_RDM_SHIFT 28 238#define ID_AA64ISAR0_RDM_MASK (0xf << ID_AA64ISAR0_RDM_SHIFT) 239#define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK) 240#define ID_AA64ISAR0_RDM_NONE (0x0 << ID_AA64ISAR0_RDM_SHIFT) 241#define ID_AA64ISAR0_RDM_IMPL (0x1 << ID_AA64ISAR0_RDM_SHIFT) 242 243/* ID_AA64MMFR0_EL1 */ 244#define ID_AA64MMFR0_MASK 0xffffffff 245#define ID_AA64MMFR0_PA_RANGE_SHIFT 0 246#define ID_AA64MMFR0_PA_RANGE_MASK (0xf << ID_AA64MMFR0_PA_RANGE_SHIFT) 247#define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK) 248#define ID_AA64MMFR0_PA_RANGE_4G (0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT) 249#define ID_AA64MMFR0_PA_RANGE_64G (0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT) 250#define ID_AA64MMFR0_PA_RANGE_1T (0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT) 251#define ID_AA64MMFR0_PA_RANGE_4T (0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT) 252#define ID_AA64MMFR0_PA_RANGE_16T (0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT) 253#define ID_AA64MMFR0_PA_RANGE_256T (0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT) 254#define ID_AA64MMFR0_ASID_BITS_SHIFT 4 255#define ID_AA64MMFR0_ASID_BITS_MASK (0xf << ID_AA64MMFR0_ASID_BITS_SHIFT) 256#define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK) 257#define ID_AA64MMFR0_ASID_BITS_8 (0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT) 258#define ID_AA64MMFR0_ASID_BITS_16 (0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT) 259#define ID_AA64MMFR0_BIGEND_SHIFT 8 260#define ID_AA64MMFR0_BIGEND_MASK (0xf << ID_AA64MMFR0_BIGEND_SHIFT) 261#define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK) 262#define ID_AA64MMFR0_BIGEND_FIXED (0x0 << ID_AA64MMFR0_BIGEND_SHIFT) 263#define ID_AA64MMFR0_BIGEND_MIXED (0x1 << ID_AA64MMFR0_BIGEND_SHIFT) 264#define ID_AA64MMFR0_S_NS_MEM_SHIFT 12 265#define ID_AA64MMFR0_S_NS_MEM_MASK (0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT) 266#define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK) 267#define ID_AA64MMFR0_S_NS_MEM_NONE (0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 268#define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 269#define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16 270#define ID_AA64MMFR0_BIGEND_EL0_MASK (0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 271#define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK) 272#define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 273#define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 274#define ID_AA64MMFR0_TGRAN16_SHIFT 20 275#define ID_AA64MMFR0_TGRAN16_MASK (0xf << ID_AA64MMFR0_TGRAN16_SHIFT) 276#define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK) 277#define ID_AA64MMFR0_TGRAN16_NONE (0x0 << ID_AA64MMFR0_TGRAN16_SHIFT) 278#define ID_AA64MMFR0_TGRAN16_IMPL (0x1 << ID_AA64MMFR0_TGRAN16_SHIFT) 279#define ID_AA64MMFR0_TGRAN64_SHIFT 24 280#define ID_AA64MMFR0_TGRAN64_MASK (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 281#define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK) 282#define ID_AA64MMFR0_TGRAN64_IMPL (0x0 << ID_AA64MMFR0_TGRAN64_SHIFT) 283#define ID_AA64MMFR0_TGRAN64_NONE (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 284#define ID_AA64MMFR0_TGRAN4_SHIFT 28 285#define ID_AA64MMFR0_TGRAN4_MASK (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 286#define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK) 287#define ID_AA64MMFR0_TGRAN4_IMPL (0x0 << ID_AA64MMFR0_TGRAN4_SHIFT) 288#define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 289 290/* ID_AA64MMFR1_EL1 */ 291#define ID_AA64MMFR1_MASK 0x00ffffff 292#define ID_AA64MMFR1_HAFDBS_SHIFT 0 293#define ID_AA64MMFR1_HAFDBS_MASK (0xf << ID_AA64MMFR1_HAFDBS_SHIFT) 294#define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 295#define ID_AA64MMFR1_HAFDBS_NONE (0x0 << ID_AA64MMFR1_HAFDBS_SHIFT) 296#define ID_AA64MMFR1_HAFDBS_AF (0x1 << ID_AA64MMFR1_HAFDBS_SHIFT) 297#define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2 << ID_AA64MMFR1_HAFDBS_SHIFT) 298#define ID_AA64MMFR1_VMIDBITS_SHIFT 4 299#define ID_AA64MMFR1_VMIDBITS_MASK (0xf << ID_AA64MMFR1_VMIDBITS_SHIFT) 300#define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK) 301#define ID_AA64MMFR1_VMIDBITS_8 (0x0 << ID_AA64MMFR1_VMIDBITS_SHIFT) 302#define ID_AA64MMFR1_VMIDBITS_16 (0x2 << ID_AA64MMFR1_VMIDBITS_SHIFT) 303#define ID_AA64MMFR1_VH_SHIFT 8 304#define ID_AA64MMFR1_VH_MASK (0xf << ID_AA64MMFR1_VH_SHIFT) 305#define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK) 306#define ID_AA64MMFR1_VH_NONE (0x0 << ID_AA64MMFR1_VH_SHIFT) 307#define ID_AA64MMFR1_VH_IMPL (0x1 << ID_AA64MMFR1_VH_SHIFT) 308#define ID_AA64MMFR1_HPDS_SHIFT 12 309#define ID_AA64MMFR1_HPDS_MASK (0xf << ID_AA64MMFR1_HPDS_SHIFT) 310#define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 311#define ID_AA64MMFR1_HPDS_NONE (0x0 << ID_AA64MMFR1_HPDS_SHIFT) 312#define ID_AA64MMFR1_HPDS_IMPL (0x1 << ID_AA64MMFR1_HPDS_SHIFT) 313#define ID_AA64MMFR1_LO_SHIFT 16 314#define ID_AA64MMFR1_LO_MASK (0xf << ID_AA64MMFR1_LO_SHIFT) 315#define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK) 316#define ID_AA64MMFR1_LO_NONE (0x0 << ID_AA64MMFR1_LO_SHIFT) 317#define ID_AA64MMFR1_LO_IMPL (0x1 << ID_AA64MMFR1_LO_SHIFT) 318#define ID_AA64MMFR1_PAN_SHIFT 20 319#define ID_AA64MMFR1_PAN_MASK (0xf << ID_AA64MMFR1_PAN_SHIFT) 320#define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK) 321#define ID_AA64MMFR1_PAN_NONE (0x0 << ID_AA64MMFR1_PAN_SHIFT) 322#define ID_AA64MMFR1_PAN_IMPL (0x1 << ID_AA64MMFR1_PAN_SHIFT) 323 324/* ID_AA64PFR0_EL1 */ 325#define ID_AA64PFR0_MASK 0x0fffffff 326#define ID_AA64PFR0_EL0_SHIFT 0 327#define ID_AA64PFR0_EL0_MASK (0xf << ID_AA64PFR0_EL0_SHIFT) 328#define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) 329#define ID_AA64PFR0_EL0_64 (1 << ID_AA64PFR0_EL0_SHIFT) 330#define ID_AA64PFR0_EL0_64_32 (2 << ID_AA64PFR0_EL0_SHIFT) 331#define ID_AA64PFR0_EL1_SHIFT 4 332#define ID_AA64PFR0_EL1_MASK (0xf << ID_AA64PFR0_EL1_SHIFT) 333#define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK) 334#define ID_AA64PFR0_EL1_64 (1 << ID_AA64PFR0_EL1_SHIFT) 335#define ID_AA64PFR0_EL1_64_32 (2 << ID_AA64PFR0_EL1_SHIFT) 336#define ID_AA64PFR0_EL2_SHIFT 8 337#define ID_AA64PFR0_EL2_MASK (0xf << ID_AA64PFR0_EL2_SHIFT) 338#define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK) 339#define ID_AA64PFR0_EL2_NONE (0 << ID_AA64PFR0_EL2_SHIFT) 340#define ID_AA64PFR0_EL2_64 (1 << ID_AA64PFR0_EL2_SHIFT) 341#define ID_AA64PFR0_EL2_64_32 (2 << ID_AA64PFR0_EL2_SHIFT) 342#define ID_AA64PFR0_EL3_SHIFT 12 343#define ID_AA64PFR0_EL3_MASK (0xf << ID_AA64PFR0_EL3_SHIFT) 344#define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK) 345#define ID_AA64PFR0_EL3_NONE (0 << ID_AA64PFR0_EL3_SHIFT) 346#define ID_AA64PFR0_EL3_64 (1 << ID_AA64PFR0_EL3_SHIFT) 347#define ID_AA64PFR0_EL3_64_32 (2 << ID_AA64PFR0_EL3_SHIFT) 348#define ID_AA64PFR0_FP_SHIFT 16 349#define ID_AA64PFR0_FP_MASK (0xf << ID_AA64PFR0_FP_SHIFT) 350#define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) 351#define ID_AA64PFR0_FP_IMPL (0x0 << ID_AA64PFR0_FP_SHIFT) 352#define ID_AA64PFR0_FP_NONE (0xf << ID_AA64PFR0_FP_SHIFT) 353#define ID_AA64PFR0_ADV_SIMD_SHIFT 20 354#define ID_AA64PFR0_ADV_SIMD_MASK (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 355#define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK) 356#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT) 357#define ID_AA64PFR0_ADV_SIMD_NONE (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 358#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 359#define ID_AA64PFR0_GIC_SHIFT 24 360#define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT) 361#define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) 362#define ID_AA64PFR0_GIC_CPUIF_NONE (0x0 << ID_AA64PFR0_GIC_SHIFT) 363#define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT) 364 365/* MAIR_EL1 - Memory Attribute Indirection Register */ 366#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 367#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 368#define MAIR_DEVICE_nGnRnE 0x00 369#define MAIR_NORMAL_NC 0x44 370#define MAIR_NORMAL_WT 0x88 371#define MAIR_NORMAL_WB 0xff 372 373/* PAR_EL1 - Physical Address Register */ 374#define PAR_F_SHIFT 0 375#define PAR_F (0x1 << PAR_F_SHIFT) 376#define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 377/* When PAR_F == 0 (success) */ 378#define PAR_SH_SHIFT 7 379#define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 380#define PAR_NS_SHIFT 9 381#define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 382#define PAR_PA_SHIFT 12 383#define PAR_PA_MASK 0x0000fffffffff000 384#define PAR_ATTR_SHIFT 56 385#define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 386/* When PAR_F == 1 (aborted) */ 387#define PAR_FST_SHIFT 1 388#define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 389#define PAR_PTW_SHIFT 8 390#define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 391#define PAR_S_SHIFT 9 392#define PAR_S_MASK (0x1 << PAR_S_SHIFT) 393 394/* SCTLR_EL1 - System Control Register */ 395#define SCTLR_RES0 0xc8222400 /* Reserved, write 0 */ 396#define SCTLR_RES1 0x30d00800 /* Reserved, write 1 */ 397 398#define SCTLR_M 0x00000001 399#define SCTLR_A 0x00000002 400#define SCTLR_C 0x00000004 401#define SCTLR_SA 0x00000008 402#define SCTLR_SA0 0x00000010 403#define SCTLR_CP15BEN 0x00000020 404#define SCTLR_THEE 0x00000040 405#define SCTLR_ITD 0x00000080 406#define SCTLR_SED 0x00000100 407#define SCTLR_UMA 0x00000200 408#define SCTLR_I 0x00001000 409#define SCTLR_DZE 0x00004000 410#define SCTLR_UCT 0x00008000 411#define SCTLR_nTWI 0x00010000 412#define SCTLR_nTWE 0x00040000 413#define SCTLR_WXN 0x00080000 414#define SCTLR_EOE 0x01000000 415#define SCTLR_EE 0x02000000 416#define SCTLR_UCI 0x04000000 417 418/* SPSR_EL1 */ 419/* 420 * When the exception is taken in AArch64: 421 * M[4] is 0 for AArch64 mode 422 * M[3:2] is the exception level 423 * M[1] is unused 424 * M[0] is the SP select: 425 * 0: always SP0 426 * 1: current ELs SP 427 */ 428#define PSR_M_EL0t 0x00000000 429#define PSR_M_EL1t 0x00000004 430#define PSR_M_EL1h 0x00000005 431#define PSR_M_EL2t 0x00000008 432#define PSR_M_EL2h 0x00000009 433#define PSR_M_MASK 0x0000001f 434 435#define PSR_F 0x00000040 436#define PSR_I 0x00000080 437#define PSR_A 0x00000100 438#define PSR_D 0x00000200 439#define PSR_IL 0x00100000 440#define PSR_SS 0x00200000 441#define PSR_V 0x10000000 442#define PSR_C 0x20000000 443#define PSR_Z 0x40000000 444#define PSR_N 0x80000000 445 446/* TCR_EL1 - Translation Control Register */ 447#define TCR_ASID_16 (1 << 36) 448 449#define TCR_IPS_SHIFT 32 450#define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT) 451#define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT) 452#define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT) 453#define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT) 454#define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT) 455#define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT) 456 457#define TCR_TG1_SHIFT 30 458#define TCR_TG1_16K (1 << TCR_TG1_SHIFT) 459#define TCR_TG1_4K (2 << TCR_TG1_SHIFT) 460#define TCR_TG1_64K (3 << TCR_TG1_SHIFT) 461 462#define TCR_SH1_SHIFT 28 463#define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) 464#define TCR_ORGN1_SHIFT 26 465#define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) 466#define TCR_IRGN1_SHIFT 24 467#define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) 468#define TCR_SH0_SHIFT 12 469#define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) 470#define TCR_ORGN0_SHIFT 10 471#define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) 472#define TCR_IRGN0_SHIFT 8 473#define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) 474 475#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 476 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 477#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 478 479#define TCR_T1SZ_SHIFT 16 480#define TCR_T0SZ_SHIFT 0 481#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 482#define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 483#define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 484 485/* Saved Program Status Register */ 486#define DBG_SPSR_SS (0x1 << 21) 487 488/* Monitor Debug System Control Register */ 489#define DBG_MDSCR_SS (0x1 << 0) 490#define DBG_MDSCR_KDE (0x1 << 13) 491#define DBG_MDSCR_MDE (0x1 << 15) 492 493/* Perfomance Monitoring Counters */ 494#define PMCR_E (1 << 0) /* Enable all counters */ 495#define PMCR_P (1 << 1) /* Reset all counters */ 496#define PMCR_C (1 << 2) /* Clock counter reset */ 497#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 498#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 499#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 500#define PMCR_LC (1 << 6) /* Long cycle count enable */ 501#define PMCR_IMP_SHIFT 24 /* Implementer code */ 502#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 503#define PMCR_IDCODE_SHIFT 16 /* Identification code */ 504#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 505#define PMCR_IDCODE_CORTEX_A57 0x01 506#define PMCR_IDCODE_CORTEX_A72 0x02 507#define PMCR_IDCODE_CORTEX_A53 0x03 508#define PMCR_N_SHIFT 11 /* Number of counters implemented */ 509#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 510 511/* Individual CPUs are probably best IDed by everything but the revision. */ 512#define CPU_ID_CPU_MASK 0xfffffff0 513 514/* ARM64 CPUs */ 515#define CPU_ID_CORTEX_A53 0x410fd030 516#define CPU_ID_CORTEX_A53_R1 0x411fd030 517#define CPU_ID_CORTEX_A53_MASK 0xff0ffff0 518#define CPU_ID_CORTEX_A57 0x410fd070 519#define CPU_ID_CORTEX_A57_R1 0x411fd070 520#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 521#define CPU_ID_CORTEX_A72 0x410fd080 522#define CPU_ID_CORTEX_A72_R1 0x411fd080 523#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 524 525#define I_bit (1 << 7) /* IRQ disable */ 526#define F_bit 0 /* FIQ disable - not actually used */ 527 528#endif /* !_MACHINE_ARMREG_H_ */ 529