armreg.h revision 1.25
1/* $OpenBSD: armreg.h,v 1.25 2022/12/09 21:23:24 patrick Exp $ */ 2/*- 3 * Copyright (c) 2013, 2014 Andrew Turner 4 * Copyright (c) 2015 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Andrew Turner under 8 * sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm64/include/armreg.h 309248 2016-11-28 14:24:07Z andrew $ 32 */ 33 34#ifndef _MACHINE_ARMREG_H_ 35#define _MACHINE_ARMREG_H_ 36 37#define INSN_SIZE 4 38 39#define READ_SPECIALREG(reg) \ 40({ uint64_t val; \ 41 __asm volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \ 42 val; \ 43}) 44#define WRITE_SPECIALREG(reg, val) \ 45 __asm volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val)) 46 47/* CCSIDR_EL1 - Current Cache Size ID Register */ 48#define CCSIDR_SETS_MASK 0x0fffe000 49#define CCSIDR_SETS_SHIFT 13 50#define CCSIDR_SETS(reg) \ 51 ((((reg) & CCSIDR_SETS_MASK) >> CCSIDR_SETS_SHIFT) + 1) 52#define CCSIDR_WAYS_MASK 0x00001ff8 53#define CCSIDR_WAYS_SHIFT 3 54#define CCSIDR_WAYS(reg) \ 55 ((((reg) & CCSIDR_WAYS_MASK) >> CCSIDR_WAYS_SHIFT) + 1) 56#define CCSIDR_LINE_MASK 0x00000007 57#define CCSIDR_LINE_SIZE(reg) (1 << (((reg) & CCSIDR_LINE_MASK) + 4)) 58 59/* CLIDR_EL1 - Cache Level ID Register */ 60#define CLIDR_CTYPE_MASK 0x7 61#define CLIDR_CTYPE_INSN 0x1 62#define CLIDR_CTYPE_DATA 0x2 63#define CLIDR_CTYPE_UNIFIED 0x4 64 65/* CNTHCTL_EL2 - Counter-timer Hypervisor Control Register */ 66#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 67#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 68#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 69#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 70#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 71 72/* CNTKCTL_EL1 - Counter-timer Kernel Control Register */ 73#define CNTKCTL_EL0VCTEN (1 << 1) /* Allow EL0 virtual counter access */ 74 75/* CNTV_CTL_EL0 */ 76#define CNTV_CTL_ENABLE (1 << 0) 77#define CNTV_CTL_IMASK (1 << 1) 78#define CNTV_CTL_ISTATUS (1 << 2) 79 80/* CPACR_EL1 */ 81#define CPACR_FPEN_MASK (0x3 << 20) 82#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 83#define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 84#define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 85#define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 86#define CPACR_TTA (0x1 << 28) 87 88/* CSSELR_EL1 - Cache Size Selection Register */ 89#define CSSELR_IND (1 << 0) 90#define CSSELR_LEVEL_SHIFT 1 91 92/* CTR_EL0 - Cache Type Register */ 93#define CTR_DLINE_SHIFT 16 94#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 95#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) 96#define CTR_IL1P_SHIFT 14 97#define CTR_IL1P_MASK (0x3 << CTR_IL1P_SHIFT) 98#define CTR_IL1P_AIVIVT (0x1 << CTR_IL1P_SHIFT) 99#define CTR_IL1P_VIPT (0x2 << CTR_IL1P_SHIFT) 100#define CTR_IL1P_PIPT (0x3 << CTR_IL1P_SHIFT) 101#define CTR_ILINE_SHIFT 0 102#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 103#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) 104 105/* MPIDR_EL1 - Multiprocessor Affinity Register */ 106#define MPIDR_AFF3 (0xFFULL << 32) 107#define MPIDR_AFF2 (0xFFULL << 16) 108#define MPIDR_AFF1 (0xFFULL << 8) 109#define MPIDR_AFF0 (0xFFULL << 0) 110#define MPIDR_AFF (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0) 111 112/* DCZID_EL0 - Data Cache Zero ID register */ 113#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 114#define DCZID_BS_SHIFT 0 115#define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 116#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 117 118/* ESR_ELx */ 119#define ESR_ELx_ISS_MASK 0x00ffffff 120#define ISS_INSN_FnV (0x01 << 10) 121#define ISS_INSN_EA (0x01 << 9) 122#define ISS_INSN_S1PTW (0x01 << 7) 123#define ISS_INSN_IFSC_MASK (0x1f << 0) 124#define ISS_DATA_ISV (0x01 << 24) 125#define ISS_DATA_SAS_MASK (0x03 << 22) 126#define ISS_DATA_SSE (0x01 << 21) 127#define ISS_DATA_SRT_MASK (0x1f << 16) 128#define ISS_DATA_SF (0x01 << 15) 129#define ISS_DATA_AR (0x01 << 14) 130#define ISS_DATA_FnV (0x01 << 10) 131#define ISS_DATA_EA (0x01 << 9) 132#define ISS_DATA_CM (0x01 << 8) 133#define ISS_INSN_S1PTW (0x01 << 7) 134#define ISS_DATA_WnR (0x01 << 6) 135#define ISS_DATA_DFSC_MASK (0x3f << 0) 136#define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 137#define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 138#define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 139#define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 140#define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 141#define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 142#define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 143#define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 144#define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 145#define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 146#define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 147#define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 148#define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 149#define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 150#define ISS_DATA_DFSC_EXT (0x10 << 0) 151#define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 152#define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 153#define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 154#define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 155#define ISS_DATA_DFSC_ECC (0x18 << 0) 156#define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 157#define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 158#define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 159#define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 160#define ISS_DATA_DFSC_ALIGN (0x21 << 0) 161#define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 162#define ESR_ELx_IL (0x01 << 25) 163#define ESR_ELx_EC_SHIFT 26 164#define ESR_ELx_EC_MASK (0x3f << 26) 165#define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 166#define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 167#define EXCP_FP_SIMD 0x07 /* FP/SIMD trap */ 168#define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 169#define EXCP_SVC 0x15 /* SVC trap */ 170#define EXCP_MSR 0x18 /* MSR/MRS trap */ 171#define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 172#define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 173#define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 174#define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 175#define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 176#define EXCP_SP_ALIGN 0x26 /* SP alignment fault */ 177#define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 178#define EXCP_SERROR 0x2f /* SError interrupt */ 179#define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 180#define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 181#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 182#define EXCP_BRK 0x3c /* Breakpoint */ 183 184/* ICC_CTLR_EL1 */ 185#define ICC_CTLR_EL1_EOIMODE (1U << 1) 186#define ICC_CTLR_EL1_PRIBITS_SHIFT 8 187#define ICC_CTLR_EL1_PRIBITS_MASK (0x7UL << 8) 188#define ICC_CTLR_EL1_PRIBITS(reg) \ 189 (((reg) & ICC_CTLR_EL1_PRIBITS_MASK) >> ICC_CTLR_EL1_PRIBITS_SHIFT) 190 191/* ICC_IAR1_EL1 */ 192#define ICC_IAR1_EL1_SPUR (0x03ff) 193 194/* ICC_IGRPEN0_EL1 */ 195#define ICC_IGRPEN0_EL1_EN (1U << 0) 196 197/* ICC_PMR_EL1 */ 198#define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 199 200/* ICC_SGI1R_EL1 */ 201#define ICC_SGI1R_EL1_TL_MASK 0xffffUL 202#define ICC_SGI1R_EL1_AFF1_SHIFT 16 203#define ICC_SGI1R_EL1_SGIID_SHIFT 24 204#define ICC_SGI1R_EL1_AFF2_SHIFT 32 205#define ICC_SGI1R_EL1_AFF3_SHIFT 48 206#define ICC_SGI1R_EL1_SGIID_MASK 0xfUL 207#define ICC_SGI1R_EL1_IRM (0x1UL << 40) 208 209/* ICC_SRE_EL1 */ 210#define ICC_SRE_EL1_SRE (1U << 0) 211 212/* ICC_SRE_EL2 */ 213#define ICC_SRE_EL2_SRE (1U << 0) 214#define ICC_SRE_EL2_EN (1U << 3) 215 216/* ID_AA64DFR0_EL1 */ 217#define ID_AA64DFR0_MASK 0x00000000f0f0ffffUL 218#define ID_AA64DFR0_DEBUG_VER_SHIFT 0 219#define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT) 220#define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) 221#define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT) 222#define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT) 223#define ID_AA64DFR0_TRACE_VER_SHIFT 4 224#define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT) 225#define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) 226#define ID_AA64DFR0_TRACE_VER_NONE (0x0 << ID_AA64DFR0_TRACE_VER_SHIFT) 227#define ID_AA64DFR0_TRACE_VER_IMPL (0x1 << ID_AA64DFR0_TRACE_VER_SHIFT) 228#define ID_AA64DFR0_PMU_VER_SHIFT 8 229#define ID_AA64DFR0_PMU_VER_MASK (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 230#define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK) 231#define ID_AA64DFR0_PMU_VER_NONE (0x0 << ID_AA64DFR0_PMU_VER_SHIFT) 232#define ID_AA64DFR0_PMU_VER_3 (0x1 << ID_AA64DFR0_PMU_VER_SHIFT) 233#define ID_AA64DFR0_PMU_VER_3_1 (0x4 << ID_AA64DFR0_PMU_VER_SHIFT) 234#define ID_AA64DFR0_PMU_VER_IMPL (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 235#define ID_AA64DFR0_BRPS_SHIFT 12 236#define ID_AA64DFR0_BRPS_MASK (0xf << ID_AA64DFR0_BRPS_SHIFT) 237#define ID_AA64DFR0_BRPS(x) \ 238 ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1) 239#define ID_AA64DFR0_WRPS_SHIFT 20 240#define ID_AA64DFR0_WRPS_MASK (0xf << ID_AA64DFR0_WRPS_SHIFT) 241#define ID_AA64DFR0_WRPS(x) \ 242 ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1) 243#define ID_AA64DFR0_CTX_CMPS_SHIFT 28 244#define ID_AA64DFR0_CTX_CMPS_MASK (0xf << ID_AA64DFR0_CTX_CMPS_SHIFT) 245#define ID_AA64DFR0_CTX_CMPS(x) \ 246 ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) 247 248/* ID_AA64ISAR0_EL1 */ 249#define ID_AA64ISAR0_MASK 0xfffffffff0fffff0ULL 250#define ID_AA64ISAR0_AES_SHIFT 4 251#define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT) 252#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) 253#define ID_AA64ISAR0_AES_NONE (0x0 << ID_AA64ISAR0_AES_SHIFT) 254#define ID_AA64ISAR0_AES_BASE (0x1 << ID_AA64ISAR0_AES_SHIFT) 255#define ID_AA64ISAR0_AES_PMULL (0x2 << ID_AA64ISAR0_AES_SHIFT) 256#define ID_AA64ISAR0_SHA1_SHIFT 8 257#define ID_AA64ISAR0_SHA1_MASK (0xf << ID_AA64ISAR0_SHA1_SHIFT) 258#define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 259#define ID_AA64ISAR0_SHA1_NONE (0x0 << ID_AA64ISAR0_SHA1_SHIFT) 260#define ID_AA64ISAR0_SHA1_BASE (0x1 << ID_AA64ISAR0_SHA1_SHIFT) 261#define ID_AA64ISAR0_SHA2_SHIFT 12 262#define ID_AA64ISAR0_SHA2_MASK (0xf << ID_AA64ISAR0_SHA2_SHIFT) 263#define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 264#define ID_AA64ISAR0_SHA2_NONE (0x0 << ID_AA64ISAR0_SHA2_SHIFT) 265#define ID_AA64ISAR0_SHA2_BASE (0x1 << ID_AA64ISAR0_SHA2_SHIFT) 266#define ID_AA64ISAR0_SHA2_512 (0x2 << ID_AA64ISAR0_SHA2_SHIFT) 267#define ID_AA64ISAR0_CRC32_SHIFT 16 268#define ID_AA64ISAR0_CRC32_MASK (0xf << ID_AA64ISAR0_CRC32_SHIFT) 269#define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 270#define ID_AA64ISAR0_CRC32_NONE (0x0 << ID_AA64ISAR0_CRC32_SHIFT) 271#define ID_AA64ISAR0_CRC32_BASE (0x1 << ID_AA64ISAR0_CRC32_SHIFT) 272#define ID_AA64ISAR0_ATOMIC_SHIFT 20 273#define ID_AA64ISAR0_ATOMIC_MASK (0xf << ID_AA64ISAR0_ATOMIC_SHIFT) 274#define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK) 275#define ID_AA64ISAR0_ATOMIC_NONE (0x0 << ID_AA64ISAR0_ATOMIC_SHIFT) 276#define ID_AA64ISAR0_ATOMIC_IMPL (0x2 << ID_AA64ISAR0_ATOMIC_SHIFT) 277#define ID_AA64ISAR0_RDM_SHIFT 28 278#define ID_AA64ISAR0_RDM_MASK (0xf << ID_AA64ISAR0_RDM_SHIFT) 279#define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK) 280#define ID_AA64ISAR0_RDM_NONE (0x0 << ID_AA64ISAR0_RDM_SHIFT) 281#define ID_AA64ISAR0_RDM_IMPL (0x1 << ID_AA64ISAR0_RDM_SHIFT) 282#define ID_AA64ISAR0_SHA3_SHIFT 32 283#define ID_AA64ISAR0_SHA3_MASK (0xfULL << ID_AA64ISAR0_SHA3_SHIFT) 284#define ID_AA64ISAR0_SHA3(x) ((x) & ID_AA64ISAR0_SHA3_MASK) 285#define ID_AA64ISAR0_SHA3_NONE (0x0ULL << ID_AA64ISAR0_SHA3_SHIFT) 286#define ID_AA64ISAR0_SHA3_IMPL (0x1ULL << ID_AA64ISAR0_SHA3_SHIFT) 287#define ID_AA64ISAR0_SM3_SHIFT 36 288#define ID_AA64ISAR0_SM3_MASK (0xfULL << ID_AA64ISAR0_SM3_SHIFT) 289#define ID_AA64ISAR0_SM3(x) ((x) & ID_AA64ISAR0_SM3_MASK) 290#define ID_AA64ISAR0_SM3_NONE (0x0ULL << ID_AA64ISAR0_SM3_SHIFT) 291#define ID_AA64ISAR0_SM3_IMPL (0x1ULL << ID_AA64ISAR0_SM3_SHIFT) 292#define ID_AA64ISAR0_SM4_SHIFT 40 293#define ID_AA64ISAR0_SM4_MASK (0xfULL << ID_AA64ISAR0_SM4_SHIFT) 294#define ID_AA64ISAR0_SM4(x) ((x) & ID_AA64ISAR0_SM4_MASK) 295#define ID_AA64ISAR0_SM4_NONE (0x0ULL << ID_AA64ISAR0_SM4_SHIFT) 296#define ID_AA64ISAR0_SM4_IMPL (0x1ULL << ID_AA64ISAR0_SM4_SHIFT) 297#define ID_AA64ISAR0_DP_SHIFT 44 298#define ID_AA64ISAR0_DP_MASK (0xfULL << ID_AA64ISAR0_DP_SHIFT) 299#define ID_AA64ISAR0_DP(x) ((x) & ID_AA64ISAR0_DP_MASK) 300#define ID_AA64ISAR0_DP_NONE (0x0ULL << ID_AA64ISAR0_DP_SHIFT) 301#define ID_AA64ISAR0_DP_IMPL (0x1ULL << ID_AA64ISAR0_DP_SHIFT) 302#define ID_AA64ISAR0_FHM_SHIFT 48 303#define ID_AA64ISAR0_FHM_MASK (0xfULL << ID_AA64ISAR0_FHM_SHIFT) 304#define ID_AA64ISAR0_FHM(x) ((x) & ID_AA64ISAR0_FHM_MASK) 305#define ID_AA64ISAR0_FHM_NONE (0x0ULL << ID_AA64ISAR0_FHM_SHIFT) 306#define ID_AA64ISAR0_FHM_IMPL (0x1ULL << ID_AA64ISAR0_FHM_SHIFT) 307#define ID_AA64ISAR0_TS_SHIFT 52 308#define ID_AA64ISAR0_TS_MASK (0xfULL << ID_AA64ISAR0_TS_SHIFT) 309#define ID_AA64ISAR0_TS(x) ((x) & ID_AA64ISAR0_TS_MASK) 310#define ID_AA64ISAR0_TS_NONE (0x0ULL << ID_AA64ISAR0_TS_SHIFT) 311#define ID_AA64ISAR0_TS_BASE (0x1ULL << ID_AA64ISAR0_TS_SHIFT) 312#define ID_AA64ISAR0_TS_AXFLAG (0x2ULL << ID_AA64ISAR0_TS_SHIFT) 313#define ID_AA64ISAR0_TLB_SHIFT 56 314#define ID_AA64ISAR0_TLB_MASK (0xfULL << ID_AA64ISAR0_TLB_SHIFT) 315#define ID_AA64ISAR0_TLB(x) ((x) & ID_AA64ISAR0_TLB_MASK) 316#define ID_AA64ISAR0_TLB_NONE (0x0ULL << ID_AA64ISAR0_TLB_SHIFT) 317#define ID_AA64ISAR0_TLB_IOS (0x1ULL << ID_AA64ISAR0_TLB_SHIFT) 318#define ID_AA64ISAR0_TLB_IRANGE (0x2ULL << ID_AA64ISAR0_TLB_SHIFT) 319#define ID_AA64ISAR0_RNDR_SHIFT 60 320#define ID_AA64ISAR0_RNDR_MASK (0xfULL << ID_AA64ISAR0_RNDR_SHIFT) 321#define ID_AA64ISAR0_RNDR(x) ((x) & ID_AA64ISAR0_RNDR_MASK) 322#define ID_AA64ISAR0_RNDR_NONE (0x0ULL << ID_AA64ISAR0_RNDR_SHIFT) 323#define ID_AA64ISAR0_RNDR_IMPL (0x1ULL << ID_AA64ISAR0_RNDR_SHIFT) 324 325/* ID_AA64ISAR1_EL1 */ 326#define ID_AA64ISAR1_MASK 0x00000fffffffffffULL 327#define ID_AA64ISAR1_DPB_SHIFT 0 328#define ID_AA64ISAR1_DPB_MASK (0xf << ID_AA64ISAR1_DPB_SHIFT) 329#define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK) 330#define ID_AA64ISAR1_DPB_NONE (0x0 << ID_AA64ISAR1_DPB_SHIFT) 331#define ID_AA64ISAR1_DPB_IMPL (0x1 << ID_AA64ISAR1_DPB_SHIFT) 332#define ID_AA64ISAR1_APA_SHIFT 4 333#define ID_AA64ISAR1_APA_MASK (0xf << ID_AA64ISAR1_APA_SHIFT) 334#define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK) 335#define ID_AA64ISAR1_APA_NONE (0x0 << ID_AA64ISAR1_APA_SHIFT) 336#define ID_AA64ISAR1_APA_BASE (0x1 << ID_AA64ISAR1_APA_SHIFT) 337#define ID_AA64ISAR1_APA_PAC (0x2 << ID_AA64ISAR1_APA_SHIFT) 338#define ID_AA64ISAR1_API_SHIFT 8 339#define ID_AA64ISAR1_API_MASK (0xf << ID_AA64ISAR1_API_SHIFT) 340#define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK) 341#define ID_AA64ISAR1_API_NONE (0x0 << ID_AA64ISAR1_API_SHIFT) 342#define ID_AA64ISAR1_API_BASE (0x1 << ID_AA64ISAR1_API_SHIFT) 343#define ID_AA64ISAR1_API_PAC (0x2 << ID_AA64ISAR1_API_SHIFT) 344#define ID_AA64ISAR1_JSCVT_SHIFT 12 345#define ID_AA64ISAR1_JSCVT_MASK (0xf << ID_AA64ISAR1_JSCVT_SHIFT) 346#define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) 347#define ID_AA64ISAR1_JSCVT_NONE (0x0 << ID_AA64ISAR1_JSCVT_SHIFT) 348#define ID_AA64ISAR1_JSCVT_IMPL (0x1 << ID_AA64ISAR1_JSCVT_SHIFT) 349#define ID_AA64ISAR1_FCMA_SHIFT 16 350#define ID_AA64ISAR1_FCMA_MASK (0xf << ID_AA64ISAR1_FCMA_SHIFT) 351#define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK) 352#define ID_AA64ISAR1_FCMA_NONE (0x0 << ID_AA64ISAR1_FCMA_SHIFT) 353#define ID_AA64ISAR1_FCMA_IMPL (0x1 << ID_AA64ISAR1_FCMA_SHIFT) 354#define ID_AA64ISAR1_LRCPC_SHIFT 20 355#define ID_AA64ISAR1_LRCPC_MASK (0xf << ID_AA64ISAR1_LRCPC_SHIFT) 356#define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) 357#define ID_AA64ISAR1_LRCPC_NONE (0x0 << ID_AA64ISAR1_LRCPC_SHIFT) 358#define ID_AA64ISAR1_LRCPC_BASE (0x1 << ID_AA64ISAR1_LRCPC_SHIFT) 359#define ID_AA64ISAR1_LRCPC_LDAPUR (0x2 << ID_AA64ISAR1_LRCPC_SHIFT) 360#define ID_AA64ISAR1_GPA_SHIFT 24 361#define ID_AA64ISAR1_GPA_MASK (0xf << ID_AA64ISAR1_GPA_SHIFT) 362#define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK) 363#define ID_AA64ISAR1_GPA_NONE (0x0 << ID_AA64ISAR1_GPA_SHIFT) 364#define ID_AA64ISAR1_GPA_IMPL (0x1 << ID_AA64ISAR1_GPA_SHIFT) 365#define ID_AA64ISAR1_GPI_SHIFT 28 366#define ID_AA64ISAR1_GPI_MASK (0xf << ID_AA64ISAR1_GPI_SHIFT) 367#define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK) 368#define ID_AA64ISAR1_GPI_NONE (0x0 << ID_AA64ISAR1_GPI_SHIFT) 369#define ID_AA64ISAR1_GPI_IMPL (0x1 << ID_AA64ISAR1_GPI_SHIFT) 370#define ID_AA64ISAR1_FRINTTS_SHIFT 32 371#define ID_AA64ISAR1_FRINTTS_MASK (0xfULL << ID_AA64ISAR1_FRINTTS_SHIFT) 372#define ID_AA64ISAR1_FRINTTS(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) 373#define ID_AA64ISAR1_FRINTTS_NONE (0x0ULL << ID_AA64ISAR1_FRINTTS_SHIFT) 374#define ID_AA64ISAR1_FRINTTS_IMPL (0x1ULL << ID_AA64ISAR1_FRINTTS_SHIFT) 375#define ID_AA64ISAR1_SB_SHIFT 36 376#define ID_AA64ISAR1_SB_MASK (0xfULL << ID_AA64ISAR1_SB_SHIFT) 377#define ID_AA64ISAR1_SB(x) ((x) & ID_AA64ISAR1_SB_MASK) 378#define ID_AA64ISAR1_SB_NONE (0x0ULL << ID_AA64ISAR1_SB_SHIFT) 379#define ID_AA64ISAR1_SB_IMPL (0x1ULL << ID_AA64ISAR1_SB_SHIFT) 380#define ID_AA64ISAR1_SPECRES_SHIFT 40 381#define ID_AA64ISAR1_SPECRES_MASK (0xfULL << ID_AA64ISAR1_SPECRES_SHIFT) 382#define ID_AA64ISAR1_SPECRES(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) 383#define ID_AA64ISAR1_SPECRES_NONE (0x0ULL << ID_AA64ISAR1_SPECRES_SHIFT) 384#define ID_AA64ISAR1_SPECRES_IMPL (0x1ULL << ID_AA64ISAR1_SPECRES_SHIFT) 385 386/* ID_AA64ISAR2_EL1 */ 387#define ID_AA64ISAR2_MASK 0x00000000f0000000ULL 388#define ID_AA64ISAR2_CLRBHB_SHIFT 28 389#define ID_AA64ISAR2_CLRBHB_MASK (0xfULL << ID_AA64ISAR2_CLRBHB_SHIFT) 390#define ID_AA64ISAR2_CLRBHB(x) ((x) & ID_AA64ISAR2_CLRBHB_MASK) 391#define ID_AA64ISAR2_CLRBHB_NONE (0x0ULL << ID_AA64ISAR2_CLRBHB_SHIFT) 392#define ID_AA64ISAR2_CLRBHB_IMPL (0x1ULL << ID_AA64ISAR2_CLRBHB_SHIFT) 393 394/* ID_AA64MMFR0_EL1 */ 395#define ID_AA64MMFR0_MASK 0x00000000ffffffffULL 396#define ID_AA64MMFR0_PA_RANGE_SHIFT 0 397#define ID_AA64MMFR0_PA_RANGE_MASK (0xf << ID_AA64MMFR0_PA_RANGE_SHIFT) 398#define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK) 399#define ID_AA64MMFR0_PA_RANGE_4G (0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT) 400#define ID_AA64MMFR0_PA_RANGE_64G (0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT) 401#define ID_AA64MMFR0_PA_RANGE_1T (0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT) 402#define ID_AA64MMFR0_PA_RANGE_4T (0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT) 403#define ID_AA64MMFR0_PA_RANGE_16T (0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT) 404#define ID_AA64MMFR0_PA_RANGE_256T (0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT) 405#define ID_AA64MMFR0_ASID_BITS_SHIFT 4 406#define ID_AA64MMFR0_ASID_BITS_MASK (0xf << ID_AA64MMFR0_ASID_BITS_SHIFT) 407#define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK) 408#define ID_AA64MMFR0_ASID_BITS_8 (0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT) 409#define ID_AA64MMFR0_ASID_BITS_16 (0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT) 410#define ID_AA64MMFR0_BIGEND_SHIFT 8 411#define ID_AA64MMFR0_BIGEND_MASK (0xf << ID_AA64MMFR0_BIGEND_SHIFT) 412#define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK) 413#define ID_AA64MMFR0_BIGEND_FIXED (0x0 << ID_AA64MMFR0_BIGEND_SHIFT) 414#define ID_AA64MMFR0_BIGEND_MIXED (0x1 << ID_AA64MMFR0_BIGEND_SHIFT) 415#define ID_AA64MMFR0_S_NS_MEM_SHIFT 12 416#define ID_AA64MMFR0_S_NS_MEM_MASK (0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT) 417#define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK) 418#define ID_AA64MMFR0_S_NS_MEM_NONE (0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 419#define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 420#define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16 421#define ID_AA64MMFR0_BIGEND_EL0_MASK (0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 422#define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK) 423#define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 424#define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 425#define ID_AA64MMFR0_TGRAN16_SHIFT 20 426#define ID_AA64MMFR0_TGRAN16_MASK (0xf << ID_AA64MMFR0_TGRAN16_SHIFT) 427#define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK) 428#define ID_AA64MMFR0_TGRAN16_NONE (0x0 << ID_AA64MMFR0_TGRAN16_SHIFT) 429#define ID_AA64MMFR0_TGRAN16_IMPL (0x1 << ID_AA64MMFR0_TGRAN16_SHIFT) 430#define ID_AA64MMFR0_TGRAN64_SHIFT 24 431#define ID_AA64MMFR0_TGRAN64_MASK (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 432#define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK) 433#define ID_AA64MMFR0_TGRAN64_IMPL (0x0 << ID_AA64MMFR0_TGRAN64_SHIFT) 434#define ID_AA64MMFR0_TGRAN64_NONE (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 435#define ID_AA64MMFR0_TGRAN4_SHIFT 28 436#define ID_AA64MMFR0_TGRAN4_MASK (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 437#define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK) 438#define ID_AA64MMFR0_TGRAN4_IMPL (0x0 << ID_AA64MMFR0_TGRAN4_SHIFT) 439#define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 440 441/* ID_AA64MMFR1_EL1 */ 442#define ID_AA64MMFR1_MASK 0xf0000000ffffffffULL 443#define ID_AA64MMFR1_HAFDBS_SHIFT 0 444#define ID_AA64MMFR1_HAFDBS_MASK (0xf << ID_AA64MMFR1_HAFDBS_SHIFT) 445#define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 446#define ID_AA64MMFR1_HAFDBS_NONE (0x0 << ID_AA64MMFR1_HAFDBS_SHIFT) 447#define ID_AA64MMFR1_HAFDBS_AF (0x1 << ID_AA64MMFR1_HAFDBS_SHIFT) 448#define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2 << ID_AA64MMFR1_HAFDBS_SHIFT) 449#define ID_AA64MMFR1_VMIDBITS_SHIFT 4 450#define ID_AA64MMFR1_VMIDBITS_MASK (0xf << ID_AA64MMFR1_VMIDBITS_SHIFT) 451#define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK) 452#define ID_AA64MMFR1_VMIDBITS_8 (0x0 << ID_AA64MMFR1_VMIDBITS_SHIFT) 453#define ID_AA64MMFR1_VMIDBITS_16 (0x2 << ID_AA64MMFR1_VMIDBITS_SHIFT) 454#define ID_AA64MMFR1_VH_SHIFT 8 455#define ID_AA64MMFR1_VH_MASK (0xf << ID_AA64MMFR1_VH_SHIFT) 456#define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK) 457#define ID_AA64MMFR1_VH_NONE (0x0 << ID_AA64MMFR1_VH_SHIFT) 458#define ID_AA64MMFR1_VH_IMPL (0x1 << ID_AA64MMFR1_VH_SHIFT) 459#define ID_AA64MMFR1_HPDS_SHIFT 12 460#define ID_AA64MMFR1_HPDS_MASK (0xf << ID_AA64MMFR1_HPDS_SHIFT) 461#define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 462#define ID_AA64MMFR1_HPDS_NONE (0x0 << ID_AA64MMFR1_HPDS_SHIFT) 463#define ID_AA64MMFR1_HPDS_IMPL (0x1 << ID_AA64MMFR1_HPDS_SHIFT) 464#define ID_AA64MMFR1_LO_SHIFT 16 465#define ID_AA64MMFR1_LO_MASK (0xf << ID_AA64MMFR1_LO_SHIFT) 466#define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK) 467#define ID_AA64MMFR1_LO_NONE (0x0 << ID_AA64MMFR1_LO_SHIFT) 468#define ID_AA64MMFR1_LO_IMPL (0x1 << ID_AA64MMFR1_LO_SHIFT) 469#define ID_AA64MMFR1_PAN_SHIFT 20 470#define ID_AA64MMFR1_PAN_MASK (0xf << ID_AA64MMFR1_PAN_SHIFT) 471#define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK) 472#define ID_AA64MMFR1_PAN_NONE (0x0 << ID_AA64MMFR1_PAN_SHIFT) 473#define ID_AA64MMFR1_PAN_IMPL (0x1 << ID_AA64MMFR1_PAN_SHIFT) 474#define ID_AA64MMFR1_PAN_ATS1E1 (0x2 << ID_AA64MMFR1_PAN_SHIFT) 475#define ID_AA64MMFR1_SPECSEI_SHIFT 24 476#define ID_AA64MMFR1_SPECSEI_MASK (0xf << ID_AA64MMFR1_SPECSEI_SHIFT) 477#define ID_AA64MMFR1_SPECSEI(x) ((x) & ID_AA64MMFR1_SPECSEI_MASK) 478#define ID_AA64MMFR1_SPECSEI_NONE (0x0 << ID_AA64MMFR1_SPECSEI_SHIFT) 479#define ID_AA64MMFR1_SPECSEI_IMPL (0x1 << ID_AA64MMFR1_SPECSEI_SHIFT) 480#define ID_AA64MMFR1_XNX_SHIFT 28 481#define ID_AA64MMFR1_XNX_MASK (0xf << ID_AA64MMFR1_XNX_SHIFT) 482#define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK) 483#define ID_AA64MMFR1_XNX_NONE (0x0 << ID_AA64MMFR1_XNX_SHIFT) 484#define ID_AA64MMFR1_XNX_IMPL (0x1 << ID_AA64MMFR1_XNX_SHIFT) 485#define ID_AA64MMFR1_ECBHB_SHIFT 60 486#define ID_AA64MMFR1_ECBHB_MASK (0xfULL << ID_AA64MMFR1_ECBHB_SHIFT) 487#define ID_AA64MMFR1_ECBHB(x) ((x) & ID_AA64MMFR1_ECBHB_MASK) 488#define ID_AA64MMFR1_ECBHB_NONE (0x0ULL << ID_AA64MMFR1_ECBHB_SHIFT) 489#define ID_AA64MMFR1_ECBHB_IMPL (0x1ULL << ID_AA64MMFR1_ECBHB_SHIFT) 490 491/* ID_AA64PFR0_EL1 */ 492#define ID_AA64PFR0_MASK 0xff0fffffffffffffULL 493#define ID_AA64PFR0_EL0_SHIFT 0 494#define ID_AA64PFR0_EL0_MASK (0xf << ID_AA64PFR0_EL0_SHIFT) 495#define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) 496#define ID_AA64PFR0_EL0_64 (1 << ID_AA64PFR0_EL0_SHIFT) 497#define ID_AA64PFR0_EL0_64_32 (2 << ID_AA64PFR0_EL0_SHIFT) 498#define ID_AA64PFR0_EL1_SHIFT 4 499#define ID_AA64PFR0_EL1_MASK (0xf << ID_AA64PFR0_EL1_SHIFT) 500#define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK) 501#define ID_AA64PFR0_EL1_64 (1 << ID_AA64PFR0_EL1_SHIFT) 502#define ID_AA64PFR0_EL1_64_32 (2 << ID_AA64PFR0_EL1_SHIFT) 503#define ID_AA64PFR0_EL2_SHIFT 8 504#define ID_AA64PFR0_EL2_MASK (0xf << ID_AA64PFR0_EL2_SHIFT) 505#define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK) 506#define ID_AA64PFR0_EL2_NONE (0 << ID_AA64PFR0_EL2_SHIFT) 507#define ID_AA64PFR0_EL2_64 (1 << ID_AA64PFR0_EL2_SHIFT) 508#define ID_AA64PFR0_EL2_64_32 (2 << ID_AA64PFR0_EL2_SHIFT) 509#define ID_AA64PFR0_EL3_SHIFT 12 510#define ID_AA64PFR0_EL3_MASK (0xf << ID_AA64PFR0_EL3_SHIFT) 511#define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK) 512#define ID_AA64PFR0_EL3_NONE (0 << ID_AA64PFR0_EL3_SHIFT) 513#define ID_AA64PFR0_EL3_64 (1 << ID_AA64PFR0_EL3_SHIFT) 514#define ID_AA64PFR0_EL3_64_32 (2 << ID_AA64PFR0_EL3_SHIFT) 515#define ID_AA64PFR0_FP_SHIFT 16 516#define ID_AA64PFR0_FP_MASK (0xf << ID_AA64PFR0_FP_SHIFT) 517#define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) 518#define ID_AA64PFR0_FP_IMPL (0x0 << ID_AA64PFR0_FP_SHIFT) 519#define ID_AA64PFR0_FP_NONE (0xf << ID_AA64PFR0_FP_SHIFT) 520#define ID_AA64PFR0_ADV_SIMD_SHIFT 20 521#define ID_AA64PFR0_ADV_SIMD_MASK (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 522#define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK) 523#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT) 524#define ID_AA64PFR0_ADV_SIMD_NONE (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 525#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 526#define ID_AA64PFR0_GIC_SHIFT 24 527#define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT) 528#define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) 529#define ID_AA64PFR0_GIC_CPUIF_NONE (0x0 << ID_AA64PFR0_GIC_SHIFT) 530#define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT) 531#define ID_AA64PFR0_RAS_SHIFT 28 532#define ID_AA64PFR0_RAS_MASK (0xfULL << ID_AA64PFR0_RAS_SHIFT) 533#define ID_AA64PFR0_RAS(x) ((x) & ID_AA64PFR0_RAS_MASK) 534#define ID_AA64PFR0_RAS_NONE (0x0ULL << ID_AA64PFR0_RAS_SHIFT) 535#define ID_AA64PFR0_RAS_IMPL (0x1ULL << ID_AA64PFR0_RAS_SHIFT) 536#define ID_AA64PFR0_RAS_IMPL_V1P1 (0x2ULL << ID_AA64PFR0_RAS_SHIFT) 537#define ID_AA64PFR0_SVE_SHIFT 32 538#define ID_AA64PFR0_SVE_MASK (0xfULL << ID_AA64PFR0_SVE_SHIFT) 539#define ID_AA64PFR0_SVE(x) ((x) & ID_AA64PFR0_SVE_MASK) 540#define ID_AA64PFR0_SVE_NONE (0x0ULL << ID_AA64PFR0_SVE_SHIFT) 541#define ID_AA64PFR0_SVE_IMPL (0x1ULL << ID_AA64PFR0_SVE_SHIFT) 542#define ID_AA64PFR0_SEL2_SHIFT 36 543#define ID_AA64PFR0_SEL2_MASK (0xfULL << ID_AA64PFR0_SEL2_SHIFT) 544#define ID_AA64PFR0_SEL2(x) ((x) & ID_AA64PFR0_SEL2_MASK) 545#define ID_AA64PFR0_SEL2_NONE (0x0ULL << ID_AA64PFR0_SEL2_SHIFT) 546#define ID_AA64PFR0_SEL2_IMPL (0x1ULL << ID_AA64PFR0_SEL2_SHIFT) 547#define ID_AA64PFR0_MPAM_SHIFT 40 548#define ID_AA64PFR0_MPAM_MASK (0xfULL << ID_AA64PFR0_MPAM_SHIFT) 549#define ID_AA64PFR0_MPAM(x) ((x) & ID_AA64PFR0_MPAM_MASK) 550#define ID_AA64PFR0_MPAM_NONE (0x0ULL << ID_AA64PFR0_MPAM_SHIFT) 551#define ID_AA64PFR0_MPAM_IMPL (0x1ULL << ID_AA64PFR0_MPAM_SHIFT) 552#define ID_AA64PFR0_AMU_SHIFT 44 553#define ID_AA64PFR0_AMU_MASK (0xfULL << ID_AA64PFR0_AMU_SHIFT) 554#define ID_AA64PFR0_AMU(x) ((x) & ID_AA64PFR0_AMU_MASK) 555#define ID_AA64PFR0_AMU_NONE (0x0ULL << ID_AA64PFR0_AMU_SHIFT) 556#define ID_AA64PFR0_AMU_IMPL (0x1ULL << ID_AA64PFR0_AMU_SHIFT) 557#define ID_AA64PFR0_DIT_SHIFT 48 558#define ID_AA64PFR0_DIT_MASK (0xfULL << ID_AA64PFR0_DIT_SHIFT) 559#define ID_AA64PFR0_DIT(x) ((x) & ID_AA64PFR0_DIT_MASK) 560#define ID_AA64PFR0_DIT_UNKNOWN (0x0ULL << ID_AA64PFR0_DIT_SHIFT) 561#define ID_AA64PFR0_DIT_IMPL (0x1ULL << ID_AA64PFR0_DIT_SHIFT) 562#define ID_AA64PFR0_CSV2_SHIFT 56 563#define ID_AA64PFR0_CSV2_MASK (0xfULL << ID_AA64PFR0_CSV2_SHIFT) 564#define ID_AA64PFR0_CSV2(x) ((x) & ID_AA64PFR0_CSV2_MASK) 565#define ID_AA64PFR0_CSV2_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV2_SHIFT) 566#define ID_AA64PFR0_CSV2_IMPL (0x1ULL << ID_AA64PFR0_CSV2_SHIFT) 567#define ID_AA64PFR0_CSV2_SCXT (0x2ULL << ID_AA64PFR0_CSV2_SHIFT) 568#define ID_AA64PFR0_CSV2_HCXT (0x3ULL << ID_AA64PFR0_CSV2_SHIFT) 569#define ID_AA64PFR0_CSV3_SHIFT 60 570#define ID_AA64PFR0_CSV3_MASK (0xfULL << ID_AA64PFR0_CSV3_SHIFT) 571#define ID_AA64PFR0_CSV3(x) ((x) & ID_AA64PFR0_CSV3_MASK) 572#define ID_AA64PFR0_CSV3_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV3_SHIFT) 573#define ID_AA64PFR0_CSV3_IMPL (0x1ULL << ID_AA64PFR0_CSV3_SHIFT) 574 575/* ID_AA64PFR1_EL1 */ 576#define ID_AA64PFR1_MASK 0x000000000000ffffULL 577#define ID_AA64PFR1_BT_SHIFT 0 578#define ID_AA64PFR1_BT_MASK (0xf << ID_AA64PFR1_BT_SHIFT) 579#define ID_AA64PFR1_BT(x) ((x) & ID_AA64PFR1_BT_MASK) 580#define ID_AA64PFR1_BT_NONE (0 << ID_AA64PFR1_BT_SHIFT) 581#define ID_AA64PFR1_BT_IMPL (1 << ID_AA64PFR1_BT_SHIFT) 582#define ID_AA64PFR1_SBSS_SHIFT 4 583#define ID_AA64PFR1_SBSS_MASK (0xf << ID_AA64PFR1_SBSS_SHIFT) 584#define ID_AA64PFR1_SBSS(x) ((x) & ID_AA64PFR1_SBSS_MASK) 585#define ID_AA64PFR1_SBSS_NONE (0 << ID_AA64PFR1_SBSS_SHIFT) 586#define ID_AA64PFR1_SBSS_PSTATE (1 << ID_AA64PFR1_SBSS_SHIFT) 587#define ID_AA64PFR1_SBSS_PSTATE_MSR (2 << ID_AA64PFR1_SBSS_SHIFT) 588#define ID_AA64PFR1_MTE_SHIFT 8 589#define ID_AA64PFR1_MTE_MASK (0xf << ID_AA64PFR1_MTE_SHIFT) 590#define ID_AA64PFR1_MTE(x) ((x) & ID_AA64PFR1_MTE_MASK) 591#define ID_AA64PFR1_MTE_NONE (0 << ID_AA64PFR1_MTE_SHIFT) 592#define ID_AA64PFR1_MTE_IMPL (1 << ID_AA64PFR1_MTE_SHIFT) 593#define ID_AA64PFR1_RAS_FRAC_SHIFT 12 594#define ID_AA64PFR1_RAS_FRAC_MASK (0xf << ID_AA64PFR1_RAS_FRAC_SHIFT) 595#define ID_AA64PFR1_RAS_FRAC(x) ((x) & ID_AA64PFR1_RAS_FRAC_MASK) 596#define ID_AA64PFR1_RAS_FRAC_NONE (0 << ID_AA64PFR1_RAS_FRAC_SHIFT) 597#define ID_AA64PFR1_RAS_FRAC_IMPL (1 << ID_AA64PFR1_RAS_FRAC_SHIFT) 598 599/* MAIR_EL1 - Memory Attribute Indirection Register */ 600#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 601#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 602#define MAIR_DEVICE_nGnRnE 0x00 603#define MAIR_NORMAL_NC 0x44 604#define MAIR_NORMAL_WT 0x88 605#define MAIR_NORMAL_WB 0xff 606 607/* PAR_EL1 - Physical Address Register */ 608#define PAR_F_SHIFT 0 609#define PAR_F (0x1 << PAR_F_SHIFT) 610#define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 611/* When PAR_F == 0 (success) */ 612#define PAR_SH_SHIFT 7 613#define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 614#define PAR_NS_SHIFT 9 615#define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 616#define PAR_PA_SHIFT 12 617#define PAR_PA_MASK 0x0000fffffffff000 618#define PAR_ATTR_SHIFT 56 619#define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 620/* When PAR_F == 1 (aborted) */ 621#define PAR_FST_SHIFT 1 622#define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 623#define PAR_PTW_SHIFT 8 624#define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 625#define PAR_S_SHIFT 9 626#define PAR_S_MASK (0x1 << PAR_S_SHIFT) 627 628/* SCTLR_EL1 - System Control Register */ 629#define SCTLR_RES0 0xffffffffc8222400 /* Reserved, write 0 */ 630#define SCTLR_RES1 0x0000000030d00800 /* Reserved, write 1 */ 631 632#define SCTLR_M 0x0000000000000001 633#define SCTLR_A 0x0000000000000002 634#define SCTLR_C 0x0000000000000004 635#define SCTLR_SA 0x0000000000000008 636#define SCTLR_SA0 0x0000000000000010 637#define SCTLR_CP15BEN 0x0000000000000020 638#define SCTLR_THEE 0x0000000000000040 639#define SCTLR_ITD 0x0000000000000080 640#define SCTLR_SED 0x0000000000000100 641#define SCTLR_UMA 0x0000000000000200 642#define SCTLR_I 0x0000000000001000 643#define SCTLR_DZE 0x0000000000004000 644#define SCTLR_UCT 0x0000000000008000 645#define SCTLR_nTWI 0x0000000000010000 646#define SCTLR_nTWE 0x0000000000040000 647#define SCTLR_WXN 0x0000000000080000 648#define SCTLR_SPAN 0x0000000000800000 649#define SCTLR_EOE 0x0000000001000000 650#define SCTLR_EE 0x0000000002000000 651#define SCTLR_UCI 0x0000000004000000 652 653/* SPSR_EL1 */ 654/* 655 * When the exception is taken in AArch64: 656 * M[4] is 0 for AArch64 mode 657 * M[3:2] is the exception level 658 * M[1] is unused 659 * M[0] is the SP select: 660 * 0: always SP0 661 * 1: current ELs SP 662 */ 663#define PSR_M_EL0t 0x00000000 664#define PSR_M_EL1t 0x00000004 665#define PSR_M_EL1h 0x00000005 666#define PSR_M_EL2t 0x00000008 667#define PSR_M_EL2h 0x00000009 668#define PSR_M_MASK 0x0000001f 669 670#define PSR_F 0x00000040 671#define PSR_I 0x00000080 672#define PSR_A 0x00000100 673#define PSR_D 0x00000200 674#define PSR_SSBS 0x00001000 675#define PSR_IL 0x00100000 676#define PSR_SS 0x00200000 677#define PSR_PAN 0x00400000 678#define PSR_UAO 0x00800000 679#define PSR_DIT 0x01000000 680#define PSR_TCO 0x02000000 681#define PSR_V 0x10000000 682#define PSR_C 0x20000000 683#define PSR_Z 0x40000000 684#define PSR_N 0x80000000 685 686/* TCR_EL1 - Translation Control Register */ 687#define TCR_AS (1UL << 36) 688 689#define TCR_IPS_SHIFT 32 690#define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT) 691#define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT) 692#define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT) 693#define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT) 694#define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) 695#define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) 696 697#define TCR_TG1_SHIFT 30 698#define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) 699#define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) 700#define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) 701 702#define TCR_SH1_SHIFT 28 703#define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) 704#define TCR_ORGN1_SHIFT 26 705#define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) 706#define TCR_IRGN1_SHIFT 24 707#define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) 708 709#define TCR_A1 (1UL << 22) 710 711#define TCR_TG0_SHIFT 14 712#define TCR_TG0_4K (0UL << TCR_TG0_SHIFT) 713#define TCR_TG0_64K (1UL << TCR_TG0_SHIFT) 714#define TCR_TG0_16K (2UL << TCR_TG0_SHIFT) 715 716#define TCR_SH0_SHIFT 12 717#define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) 718#define TCR_ORGN0_SHIFT 10 719#define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) 720#define TCR_IRGN0_SHIFT 8 721#define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) 722 723#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 724 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 725#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 726 727#define TCR_T1SZ_SHIFT 16 728#define TCR_T0SZ_SHIFT 0 729#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 730#define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 731#define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 732 733/* Monitor Debug System Control Register */ 734#define DBG_MDSCR_SS (0x1 << 0) 735#define DBG_MDSCR_TDCC (0x1 << 12) 736#define DBG_MDSCR_KDE (0x1 << 13) 737#define DBG_MDSCR_MDE (0x1 << 15) 738 739/* Performance Monitoring Counters */ 740#define PMCR_E (1 << 0) /* Enable all counters */ 741#define PMCR_P (1 << 1) /* Reset all counters */ 742#define PMCR_C (1 << 2) /* Clock counter reset */ 743#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 744#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 745#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 746#define PMCR_LC (1 << 6) /* Long cycle count enable */ 747#define PMCR_IMP_SHIFT 24 /* Implementer code */ 748#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 749#define PMCR_IDCODE_SHIFT 16 /* Identification code */ 750#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 751#define PMCR_IDCODE_CORTEX_A57 0x01 752#define PMCR_IDCODE_CORTEX_A72 0x02 753#define PMCR_IDCODE_CORTEX_A53 0x03 754#define PMCR_N_SHIFT 11 /* Number of counters implemented */ 755#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 756 757/* Individual CPUs are probably best IDed by everything but the revision. */ 758#define CPU_ID_CPU_MASK 0xfffffff0 759 760/* ARM64 CPUs */ 761#define CPU_ID_CORTEX_A53 0x410fd030 762#define CPU_ID_CORTEX_A53_R1 0x411fd030 763#define CPU_ID_CORTEX_A53_MASK 0xff0ffff0 764#define CPU_ID_CORTEX_A57 0x410fd070 765#define CPU_ID_CORTEX_A57_R1 0x411fd070 766#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 767#define CPU_ID_CORTEX_A72 0x410fd080 768#define CPU_ID_CORTEX_A72_R1 0x411fd080 769#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 770 771#define I_bit (1 << 7) /* IRQ disable */ 772#define F_bit 0 /* FIQ disable - not actually used */ 773 774#endif /* !_MACHINE_ARMREG_H_ */ 775