armreg.h revision 1.20
1/* $OpenBSD: armreg.h,v 1.20 2022/08/24 22:01:16 kettenis Exp $ */ 2/*- 3 * Copyright (c) 2013, 2014 Andrew Turner 4 * Copyright (c) 2015 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Andrew Turner under 8 * sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm64/include/armreg.h 309248 2016-11-28 14:24:07Z andrew $ 32 */ 33 34#ifndef _MACHINE_ARMREG_H_ 35#define _MACHINE_ARMREG_H_ 36 37#define INSN_SIZE 4 38 39#define READ_SPECIALREG(reg) \ 40({ uint64_t val; \ 41 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \ 42 val; \ 43}) 44#define WRITE_SPECIALREG(reg, val) \ 45 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val)) 46 47/* CCSIDR_EL1 - Current Cache Size ID Register */ 48#define CCSIDR_SETS_MASK 0x0fffe000 49#define CCSIDR_SETS_SHIFT 13 50#define CCSIDR_SETS(reg) \ 51 ((((reg) & CCSIDR_SETS_MASK) >> CCSIDR_SETS_SHIFT) + 1) 52#define CCSIDR_WAYS_MASK 0x00001ff8 53#define CCSIDR_WAYS_SHIFT 3 54#define CCSIDR_WAYS(reg) \ 55 ((((reg) & CCSIDR_WAYS_MASK) >> CCSIDR_WAYS_SHIFT) + 1) 56#define CCSIDR_LINE_MASK 0x00000007 57#define CCSIDR_LINE_SIZE(reg) (1 << (((reg) & CCSIDR_LINE_MASK) + 4)) 58 59/* CLIDR_EL1 - Cache Level ID Register */ 60#define CLIDR_CTYPE_MASK 0x7 61#define CLIDR_CTYPE_INSN 0x1 62#define CLIDR_CTYPE_DATA 0x2 63#define CLIDR_CTYPE_UNIFIED 0x4 64 65/* CNTHCTL_EL2 - Counter-timer Hypervisor Control Register */ 66#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 67#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 68#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 69#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 70#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 71 72/* CNTKCTL_EL1 - Counter-timer Kernel Control Register */ 73#define CNTKCTL_EL0VCTEN (1 << 1) /* Allow EL0 virtual counter access */ 74 75/* CPACR_EL1 */ 76#define CPACR_FPEN_MASK (0x3 << 20) 77#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 78#define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 79#define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 80#define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 81#define CPACR_TTA (0x1 << 28) 82 83/* CSSELR_EL1 - Cache Size Selection Register */ 84#define CSSELR_IND (1 << 0) 85#define CSSELR_LEVEL_SHIFT 1 86 87/* CTR_EL0 - Cache Type Register */ 88#define CTR_DLINE_SHIFT 16 89#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 90#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) 91#define CTR_IL1P_SHIFT 14 92#define CTR_IL1P_MASK (0x3 << CTR_IL1P_SHIFT) 93#define CTR_IL1P_AIVIVT (0x1 << CTR_IL1P_SHIFT) 94#define CTR_IL1P_VIPT (0x2 << CTR_IL1P_SHIFT) 95#define CTR_IL1P_PIPT (0x3 << CTR_IL1P_SHIFT) 96#define CTR_ILINE_SHIFT 0 97#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 98#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) 99 100/* MPIDR_EL1 - Multiprocessor Affinity Register */ 101#define MPIDR_AFF3 (0xFFULL << 32) 102#define MPIDR_AFF2 (0xFFULL << 16) 103#define MPIDR_AFF1 (0xFFULL << 8) 104#define MPIDR_AFF0 (0xFFULL << 0) 105#define MPIDR_AFF (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0) 106 107/* DCZID_EL0 - Data Cache Zero ID register */ 108#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 109#define DCZID_BS_SHIFT 0 110#define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 111#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 112 113/* ESR_ELx */ 114#define ESR_ELx_ISS_MASK 0x00ffffff 115#define ISS_INSN_FnV (0x01 << 10) 116#define ISS_INSN_EA (0x01 << 9) 117#define ISS_INSN_S1PTW (0x01 << 7) 118#define ISS_INSN_IFSC_MASK (0x1f << 0) 119#define ISS_DATA_ISV (0x01 << 24) 120#define ISS_DATA_SAS_MASK (0x03 << 22) 121#define ISS_DATA_SSE (0x01 << 21) 122#define ISS_DATA_SRT_MASK (0x1f << 16) 123#define ISS_DATA_SF (0x01 << 15) 124#define ISS_DATA_AR (0x01 << 14) 125#define ISS_DATA_FnV (0x01 << 10) 126#define ISS_DATA_EA (0x01 << 9) 127#define ISS_DATA_CM (0x01 << 8) 128#define ISS_INSN_S1PTW (0x01 << 7) 129#define ISS_DATA_WnR (0x01 << 6) 130#define ISS_DATA_DFSC_MASK (0x3f << 0) 131#define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 132#define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 133#define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 134#define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 135#define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 136#define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 137#define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 138#define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 139#define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 140#define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 141#define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 142#define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 143#define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 144#define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 145#define ISS_DATA_DFSC_EXT (0x10 << 0) 146#define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 147#define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 148#define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 149#define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 150#define ISS_DATA_DFSC_ECC (0x18 << 0) 151#define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 152#define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 153#define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 154#define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 155#define ISS_DATA_DFSC_ALIGN (0x21 << 0) 156#define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 157#define ESR_ELx_IL (0x01 << 25) 158#define ESR_ELx_EC_SHIFT 26 159#define ESR_ELx_EC_MASK (0x3f << 26) 160#define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 161#define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 162#define EXCP_FP_SIMD 0x07 /* FP/SIMD trap */ 163#define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 164#define EXCP_SVC 0x15 /* SVC trap */ 165#define EXCP_MSR 0x18 /* MSR/MRS trap */ 166#define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 167#define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 168#define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 169#define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 170#define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 171#define EXCP_SP_ALIGN 0x26 /* SP alignment fault */ 172#define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 173#define EXCP_SERROR 0x2f /* SError interrupt */ 174#define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 175#define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 176#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 177#define EXCP_BRK 0x3c /* Breakpoint */ 178 179/* ICC_CTLR_EL1 */ 180#define ICC_CTLR_EL1_EOIMODE (1U << 1) 181#define ICC_CTLR_EL1_PRIBITS_SHIFT 8 182#define ICC_CTLR_EL1_PRIBITS_MASK (0x7UL << 8) 183#define ICC_CTLR_EL1_PRIBITS(reg) \ 184 (((reg) & ICC_CTLR_EL1_PRIBITS_MASK) >> ICC_CTLR_EL1_PRIBITS_SHIFT) 185 186/* ICC_IAR1_EL1 */ 187#define ICC_IAR1_EL1_SPUR (0x03ff) 188 189/* ICC_IGRPEN0_EL1 */ 190#define ICC_IGRPEN0_EL1_EN (1U << 0) 191 192/* ICC_PMR_EL1 */ 193#define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 194 195/* ICC_SGI1R_EL1 */ 196#define ICC_SGI1R_EL1_TL_MASK 0xffffUL 197#define ICC_SGI1R_EL1_AFF1_SHIFT 16 198#define ICC_SGI1R_EL1_SGIID_SHIFT 24 199#define ICC_SGI1R_EL1_AFF2_SHIFT 32 200#define ICC_SGI1R_EL1_AFF3_SHIFT 48 201#define ICC_SGI1R_EL1_SGIID_MASK 0xfUL 202#define ICC_SGI1R_EL1_IRM (0x1UL << 40) 203 204/* ICC_SRE_EL1 */ 205#define ICC_SRE_EL1_SRE (1U << 0) 206 207/* ICC_SRE_EL2 */ 208#define ICC_SRE_EL2_SRE (1U << 0) 209#define ICC_SRE_EL2_EN (1U << 3) 210 211/* ID_AA64DFR0_EL1 */ 212#define ID_AA64DFR0_MASK 0x00000000f0f0ffffUL 213#define ID_AA64DFR0_DEBUG_VER_SHIFT 0 214#define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT) 215#define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) 216#define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT) 217#define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT) 218#define ID_AA64DFR0_TRACE_VER_SHIFT 4 219#define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT) 220#define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) 221#define ID_AA64DFR0_TRACE_VER_NONE (0x0 << ID_AA64DFR0_TRACE_VER_SHIFT) 222#define ID_AA64DFR0_TRACE_VER_IMPL (0x1 << ID_AA64DFR0_TRACE_VER_SHIFT) 223#define ID_AA64DFR0_PMU_VER_SHIFT 8 224#define ID_AA64DFR0_PMU_VER_MASK (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 225#define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK) 226#define ID_AA64DFR0_PMU_VER_NONE (0x0 << ID_AA64DFR0_PMU_VER_SHIFT) 227#define ID_AA64DFR0_PMU_VER_3 (0x1 << ID_AA64DFR0_PMU_VER_SHIFT) 228#define ID_AA64DFR0_PMU_VER_3_1 (0x4 << ID_AA64DFR0_PMU_VER_SHIFT) 229#define ID_AA64DFR0_PMU_VER_IMPL (0xf << ID_AA64DFR0_PMU_VER_SHIFT) 230#define ID_AA64DFR0_BRPS_SHIFT 12 231#define ID_AA64DFR0_BRPS_MASK (0xf << ID_AA64DFR0_BRPS_SHIFT) 232#define ID_AA64DFR0_BRPS(x) \ 233 ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1) 234#define ID_AA64DFR0_WRPS_SHIFT 20 235#define ID_AA64DFR0_WRPS_MASK (0xf << ID_AA64DFR0_WRPS_SHIFT) 236#define ID_AA64DFR0_WRPS(x) \ 237 ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1) 238#define ID_AA64DFR0_CTX_CMPS_SHIFT 28 239#define ID_AA64DFR0_CTX_CMPS_MASK (0xf << ID_AA64DFR0_CTX_CMPS_SHIFT) 240#define ID_AA64DFR0_CTX_CMPS(x) \ 241 ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) 242 243/* ID_AA64ISAR0_EL1 */ 244#define ID_AA64ISAR0_MASK 0xfffffffff0fffff0ULL 245#define ID_AA64ISAR0_AES_SHIFT 4 246#define ID_AA64ISAR0_AES_MASK (0xf << ID_AA64ISAR0_AES_SHIFT) 247#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) 248#define ID_AA64ISAR0_AES_NONE (0x0 << ID_AA64ISAR0_AES_SHIFT) 249#define ID_AA64ISAR0_AES_BASE (0x1 << ID_AA64ISAR0_AES_SHIFT) 250#define ID_AA64ISAR0_AES_PMULL (0x2 << ID_AA64ISAR0_AES_SHIFT) 251#define ID_AA64ISAR0_SHA1_SHIFT 8 252#define ID_AA64ISAR0_SHA1_MASK (0xf << ID_AA64ISAR0_SHA1_SHIFT) 253#define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 254#define ID_AA64ISAR0_SHA1_NONE (0x0 << ID_AA64ISAR0_SHA1_SHIFT) 255#define ID_AA64ISAR0_SHA1_BASE (0x1 << ID_AA64ISAR0_SHA1_SHIFT) 256#define ID_AA64ISAR0_SHA2_SHIFT 12 257#define ID_AA64ISAR0_SHA2_MASK (0xf << ID_AA64ISAR0_SHA2_SHIFT) 258#define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 259#define ID_AA64ISAR0_SHA2_NONE (0x0 << ID_AA64ISAR0_SHA2_SHIFT) 260#define ID_AA64ISAR0_SHA2_BASE (0x1 << ID_AA64ISAR0_SHA2_SHIFT) 261#define ID_AA64ISAR0_SHA2_512 (0x2 << ID_AA64ISAR0_SHA2_SHIFT) 262#define ID_AA64ISAR0_CRC32_SHIFT 16 263#define ID_AA64ISAR0_CRC32_MASK (0xf << ID_AA64ISAR0_CRC32_SHIFT) 264#define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 265#define ID_AA64ISAR0_CRC32_NONE (0x0 << ID_AA64ISAR0_CRC32_SHIFT) 266#define ID_AA64ISAR0_CRC32_BASE (0x1 << ID_AA64ISAR0_CRC32_SHIFT) 267#define ID_AA64ISAR0_ATOMIC_SHIFT 20 268#define ID_AA64ISAR0_ATOMIC_MASK (0xf << ID_AA64ISAR0_ATOMIC_SHIFT) 269#define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK) 270#define ID_AA64ISAR0_ATOMIC_NONE (0x0 << ID_AA64ISAR0_ATOMIC_SHIFT) 271#define ID_AA64ISAR0_ATOMIC_IMPL (0x2 << ID_AA64ISAR0_ATOMIC_SHIFT) 272#define ID_AA64ISAR0_RDM_SHIFT 28 273#define ID_AA64ISAR0_RDM_MASK (0xf << ID_AA64ISAR0_RDM_SHIFT) 274#define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK) 275#define ID_AA64ISAR0_RDM_NONE (0x0 << ID_AA64ISAR0_RDM_SHIFT) 276#define ID_AA64ISAR0_RDM_IMPL (0x1 << ID_AA64ISAR0_RDM_SHIFT) 277#define ID_AA64ISAR0_SHA3_SHIFT 32 278#define ID_AA64ISAR0_SHA3_MASK (0xfULL << ID_AA64ISAR0_SHA3_SHIFT) 279#define ID_AA64ISAR0_SHA3(x) ((x) & ID_AA64ISAR0_SHA3_MASK) 280#define ID_AA64ISAR0_SHA3_NONE (0x0ULL << ID_AA64ISAR0_SHA3_SHIFT) 281#define ID_AA64ISAR0_SHA3_IMPL (0x1ULL << ID_AA64ISAR0_SHA3_SHIFT) 282#define ID_AA64ISAR0_SM3_SHIFT 36 283#define ID_AA64ISAR0_SM3_MASK (0xfULL << ID_AA64ISAR0_SM3_SHIFT) 284#define ID_AA64ISAR0_SM3(x) ((x) & ID_AA64ISAR0_SM3_MASK) 285#define ID_AA64ISAR0_SM3_NONE (0x0ULL << ID_AA64ISAR0_SM3_SHIFT) 286#define ID_AA64ISAR0_SM3_IMPL (0x1ULL << ID_AA64ISAR0_SM3_SHIFT) 287#define ID_AA64ISAR0_SM4_SHIFT 40 288#define ID_AA64ISAR0_SM4_MASK (0xfULL << ID_AA64ISAR0_SM4_SHIFT) 289#define ID_AA64ISAR0_SM4(x) ((x) & ID_AA64ISAR0_SM4_MASK) 290#define ID_AA64ISAR0_SM4_NONE (0x0ULL << ID_AA64ISAR0_SM4_SHIFT) 291#define ID_AA64ISAR0_SM4_IMPL (0x1ULL << ID_AA64ISAR0_SM4_SHIFT) 292#define ID_AA64ISAR0_DP_SHIFT 44 293#define ID_AA64ISAR0_DP_MASK (0xfULL << ID_AA64ISAR0_DP_SHIFT) 294#define ID_AA64ISAR0_DP(x) ((x) & ID_AA64ISAR0_DP_MASK) 295#define ID_AA64ISAR0_DP_NONE (0x0ULL << ID_AA64ISAR0_DP_SHIFT) 296#define ID_AA64ISAR0_DP_IMPL (0x1ULL << ID_AA64ISAR0_DP_SHIFT) 297#define ID_AA64ISAR0_FHM_SHIFT 48 298#define ID_AA64ISAR0_FHM_MASK (0xfULL << ID_AA64ISAR0_FHM_SHIFT) 299#define ID_AA64ISAR0_FHM(x) ((x) & ID_AA64ISAR0_FHM_MASK) 300#define ID_AA64ISAR0_FHM_NONE (0x0ULL << ID_AA64ISAR0_FHM_SHIFT) 301#define ID_AA64ISAR0_FHM_IMPL (0x1ULL << ID_AA64ISAR0_FHM_SHIFT) 302#define ID_AA64ISAR0_TS_SHIFT 52 303#define ID_AA64ISAR0_TS_MASK (0xfULL << ID_AA64ISAR0_TS_SHIFT) 304#define ID_AA64ISAR0_TS(x) ((x) & ID_AA64ISAR0_TS_MASK) 305#define ID_AA64ISAR0_TS_NONE (0x0ULL << ID_AA64ISAR0_TS_SHIFT) 306#define ID_AA64ISAR0_TS_BASE (0x1ULL << ID_AA64ISAR0_TS_SHIFT) 307#define ID_AA64ISAR0_TS_AXFLAG (0x2ULL << ID_AA64ISAR0_TS_SHIFT) 308#define ID_AA64ISAR0_TLB_SHIFT 56 309#define ID_AA64ISAR0_TLB_MASK (0xfULL << ID_AA64ISAR0_TLB_SHIFT) 310#define ID_AA64ISAR0_TLB(x) ((x) & ID_AA64ISAR0_TLB_MASK) 311#define ID_AA64ISAR0_TLB_NONE (0x0ULL << ID_AA64ISAR0_TLB_SHIFT) 312#define ID_AA64ISAR0_TLB_IOS (0x1ULL << ID_AA64ISAR0_TLB_SHIFT) 313#define ID_AA64ISAR0_TLB_IRANGE (0x2ULL << ID_AA64ISAR0_TLB_SHIFT) 314#define ID_AA64ISAR0_RNDR_SHIFT 60 315#define ID_AA64ISAR0_RNDR_MASK (0xfULL << ID_AA64ISAR0_RNDR_SHIFT) 316#define ID_AA64ISAR0_RNDR(x) ((x) & ID_AA64ISAR0_RNDR_MASK) 317#define ID_AA64ISAR0_RNDR_NONE (0x0ULL << ID_AA64ISAR0_RNDR_SHIFT) 318#define ID_AA64ISAR0_RNDR_IMPL (0x1ULL << ID_AA64ISAR0_RNDR_SHIFT) 319 320/* ID_AA64ISAR1_EL1 */ 321#define ID_AA64ISAR1_MASK 0x00000fffffffffffULL 322#define ID_AA64ISAR1_DPB_SHIFT 0 323#define ID_AA64ISAR1_DPB_MASK (0xf << ID_AA64ISAR1_DPB_SHIFT) 324#define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK) 325#define ID_AA64ISAR1_DPB_NONE (0x0 << ID_AA64ISAR1_DPB_SHIFT) 326#define ID_AA64ISAR1_DPB_IMPL (0x1 << ID_AA64ISAR1_DPB_SHIFT) 327#define ID_AA64ISAR1_APA_SHIFT 4 328#define ID_AA64ISAR1_APA_MASK (0xf << ID_AA64ISAR1_APA_SHIFT) 329#define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK) 330#define ID_AA64ISAR1_APA_NONE (0x0 << ID_AA64ISAR1_APA_SHIFT) 331#define ID_AA64ISAR1_APA_BASE (0x1 << ID_AA64ISAR1_APA_SHIFT) 332#define ID_AA64ISAR1_APA_PAC (0x2 << ID_AA64ISAR1_APA_SHIFT) 333#define ID_AA64ISAR1_API_SHIFT 8 334#define ID_AA64ISAR1_API_MASK (0xf << ID_AA64ISAR1_API_SHIFT) 335#define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK) 336#define ID_AA64ISAR1_API_NONE (0x0 << ID_AA64ISAR1_API_SHIFT) 337#define ID_AA64ISAR1_API_BASE (0x1 << ID_AA64ISAR1_API_SHIFT) 338#define ID_AA64ISAR1_API_PAC (0x2 << ID_AA64ISAR1_API_SHIFT) 339#define ID_AA64ISAR1_JSCVT_SHIFT 12 340#define ID_AA64ISAR1_JSCVT_MASK (0xf << ID_AA64ISAR1_JSCVT_SHIFT) 341#define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) 342#define ID_AA64ISAR1_JSCVT_NONE (0x0 << ID_AA64ISAR1_JSCVT_SHIFT) 343#define ID_AA64ISAR1_JSCVT_IMPL (0x1 << ID_AA64ISAR1_JSCVT_SHIFT) 344#define ID_AA64ISAR1_FCMA_SHIFT 16 345#define ID_AA64ISAR1_FCMA_MASK (0xf << ID_AA64ISAR1_FCMA_SHIFT) 346#define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK) 347#define ID_AA64ISAR1_FCMA_NONE (0x0 << ID_AA64ISAR1_FCMA_SHIFT) 348#define ID_AA64ISAR1_FCMA_IMPL (0x1 << ID_AA64ISAR1_FCMA_SHIFT) 349#define ID_AA64ISAR1_LRCPC_SHIFT 20 350#define ID_AA64ISAR1_LRCPC_MASK (0xf << ID_AA64ISAR1_LRCPC_SHIFT) 351#define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) 352#define ID_AA64ISAR1_LRCPC_NONE (0x0 << ID_AA64ISAR1_LRCPC_SHIFT) 353#define ID_AA64ISAR1_LRCPC_BASE (0x1 << ID_AA64ISAR1_LRCPC_SHIFT) 354#define ID_AA64ISAR1_LRCPC_LDAPUR (0x2 << ID_AA64ISAR1_LRCPC_SHIFT) 355#define ID_AA64ISAR1_GPA_SHIFT 24 356#define ID_AA64ISAR1_GPA_MASK (0xf << ID_AA64ISAR1_GPA_SHIFT) 357#define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK) 358#define ID_AA64ISAR1_GPA_NONE (0x0 << ID_AA64ISAR1_GPA_SHIFT) 359#define ID_AA64ISAR1_GPA_IMPL (0x1 << ID_AA64ISAR1_GPA_SHIFT) 360#define ID_AA64ISAR1_GPI_SHIFT 28 361#define ID_AA64ISAR1_GPI_MASK (0xf << ID_AA64ISAR1_GPI_SHIFT) 362#define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK) 363#define ID_AA64ISAR1_GPI_NONE (0x0 << ID_AA64ISAR1_GPI_SHIFT) 364#define ID_AA64ISAR1_GPI_IMPL (0x1 << ID_AA64ISAR1_GPI_SHIFT) 365#define ID_AA64ISAR1_FRINTTS_SHIFT 32 366#define ID_AA64ISAR1_FRINTTS_MASK (0xfULL << ID_AA64ISAR1_FRINTTS_SHIFT) 367#define ID_AA64ISAR1_FRINTTS(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) 368#define ID_AA64ISAR1_FRINTTS_NONE (0x0ULL << ID_AA64ISAR1_FRINTTS_SHIFT) 369#define ID_AA64ISAR1_FRINTTS_IMPL (0x1ULL << ID_AA64ISAR1_FRINTTS_SHIFT) 370#define ID_AA64ISAR1_SB_SHIFT 36 371#define ID_AA64ISAR1_SB_MASK (0xfULL << ID_AA64ISAR1_SB_SHIFT) 372#define ID_AA64ISAR1_SB(x) ((x) & ID_AA64ISAR1_SB_MASK) 373#define ID_AA64ISAR1_SB_NONE (0x0ULL << ID_AA64ISAR1_SB_SHIFT) 374#define ID_AA64ISAR1_SB_IMPL (0x1ULL << ID_AA64ISAR1_SB_SHIFT) 375#define ID_AA64ISAR1_SPECRES_SHIFT 40 376#define ID_AA64ISAR1_SPECRES_MASK (0xfULL << ID_AA64ISAR1_SPECRES_SHIFT) 377#define ID_AA64ISAR1_SPECRES(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) 378#define ID_AA64ISAR1_SPECRES_NONE (0x0ULL << ID_AA64ISAR1_SPECRES_SHIFT) 379#define ID_AA64ISAR1_SPECRES_IMPL (0x1ULL << ID_AA64ISAR1_SPECRES_SHIFT) 380 381/* ID_AA64MMFR0_EL1 */ 382#define ID_AA64MMFR0_MASK 0x00000000ffffffffULL 383#define ID_AA64MMFR0_PA_RANGE_SHIFT 0 384#define ID_AA64MMFR0_PA_RANGE_MASK (0xf << ID_AA64MMFR0_PA_RANGE_SHIFT) 385#define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK) 386#define ID_AA64MMFR0_PA_RANGE_4G (0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT) 387#define ID_AA64MMFR0_PA_RANGE_64G (0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT) 388#define ID_AA64MMFR0_PA_RANGE_1T (0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT) 389#define ID_AA64MMFR0_PA_RANGE_4T (0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT) 390#define ID_AA64MMFR0_PA_RANGE_16T (0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT) 391#define ID_AA64MMFR0_PA_RANGE_256T (0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT) 392#define ID_AA64MMFR0_ASID_BITS_SHIFT 4 393#define ID_AA64MMFR0_ASID_BITS_MASK (0xf << ID_AA64MMFR0_ASID_BITS_SHIFT) 394#define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK) 395#define ID_AA64MMFR0_ASID_BITS_8 (0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT) 396#define ID_AA64MMFR0_ASID_BITS_16 (0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT) 397#define ID_AA64MMFR0_BIGEND_SHIFT 8 398#define ID_AA64MMFR0_BIGEND_MASK (0xf << ID_AA64MMFR0_BIGEND_SHIFT) 399#define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK) 400#define ID_AA64MMFR0_BIGEND_FIXED (0x0 << ID_AA64MMFR0_BIGEND_SHIFT) 401#define ID_AA64MMFR0_BIGEND_MIXED (0x1 << ID_AA64MMFR0_BIGEND_SHIFT) 402#define ID_AA64MMFR0_S_NS_MEM_SHIFT 12 403#define ID_AA64MMFR0_S_NS_MEM_MASK (0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT) 404#define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK) 405#define ID_AA64MMFR0_S_NS_MEM_NONE (0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 406#define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT) 407#define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16 408#define ID_AA64MMFR0_BIGEND_EL0_MASK (0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 409#define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK) 410#define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 411#define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 412#define ID_AA64MMFR0_TGRAN16_SHIFT 20 413#define ID_AA64MMFR0_TGRAN16_MASK (0xf << ID_AA64MMFR0_TGRAN16_SHIFT) 414#define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK) 415#define ID_AA64MMFR0_TGRAN16_NONE (0x0 << ID_AA64MMFR0_TGRAN16_SHIFT) 416#define ID_AA64MMFR0_TGRAN16_IMPL (0x1 << ID_AA64MMFR0_TGRAN16_SHIFT) 417#define ID_AA64MMFR0_TGRAN64_SHIFT 24 418#define ID_AA64MMFR0_TGRAN64_MASK (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 419#define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK) 420#define ID_AA64MMFR0_TGRAN64_IMPL (0x0 << ID_AA64MMFR0_TGRAN64_SHIFT) 421#define ID_AA64MMFR0_TGRAN64_NONE (0xf << ID_AA64MMFR0_TGRAN64_SHIFT) 422#define ID_AA64MMFR0_TGRAN4_SHIFT 28 423#define ID_AA64MMFR0_TGRAN4_MASK (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 424#define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK) 425#define ID_AA64MMFR0_TGRAN4_IMPL (0x0 << ID_AA64MMFR0_TGRAN4_SHIFT) 426#define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) 427 428/* ID_AA64MMFR1_EL1 */ 429#define ID_AA64MMFR1_MASK 0x00000000ffffffffULL 430#define ID_AA64MMFR1_HAFDBS_SHIFT 0 431#define ID_AA64MMFR1_HAFDBS_MASK (0xf << ID_AA64MMFR1_HAFDBS_SHIFT) 432#define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 433#define ID_AA64MMFR1_HAFDBS_NONE (0x0 << ID_AA64MMFR1_HAFDBS_SHIFT) 434#define ID_AA64MMFR1_HAFDBS_AF (0x1 << ID_AA64MMFR1_HAFDBS_SHIFT) 435#define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2 << ID_AA64MMFR1_HAFDBS_SHIFT) 436#define ID_AA64MMFR1_VMIDBITS_SHIFT 4 437#define ID_AA64MMFR1_VMIDBITS_MASK (0xf << ID_AA64MMFR1_VMIDBITS_SHIFT) 438#define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK) 439#define ID_AA64MMFR1_VMIDBITS_8 (0x0 << ID_AA64MMFR1_VMIDBITS_SHIFT) 440#define ID_AA64MMFR1_VMIDBITS_16 (0x2 << ID_AA64MMFR1_VMIDBITS_SHIFT) 441#define ID_AA64MMFR1_VH_SHIFT 8 442#define ID_AA64MMFR1_VH_MASK (0xf << ID_AA64MMFR1_VH_SHIFT) 443#define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK) 444#define ID_AA64MMFR1_VH_NONE (0x0 << ID_AA64MMFR1_VH_SHIFT) 445#define ID_AA64MMFR1_VH_IMPL (0x1 << ID_AA64MMFR1_VH_SHIFT) 446#define ID_AA64MMFR1_HPDS_SHIFT 12 447#define ID_AA64MMFR1_HPDS_MASK (0xf << ID_AA64MMFR1_HPDS_SHIFT) 448#define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 449#define ID_AA64MMFR1_HPDS_NONE (0x0 << ID_AA64MMFR1_HPDS_SHIFT) 450#define ID_AA64MMFR1_HPDS_IMPL (0x1 << ID_AA64MMFR1_HPDS_SHIFT) 451#define ID_AA64MMFR1_LO_SHIFT 16 452#define ID_AA64MMFR1_LO_MASK (0xf << ID_AA64MMFR1_LO_SHIFT) 453#define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK) 454#define ID_AA64MMFR1_LO_NONE (0x0 << ID_AA64MMFR1_LO_SHIFT) 455#define ID_AA64MMFR1_LO_IMPL (0x1 << ID_AA64MMFR1_LO_SHIFT) 456#define ID_AA64MMFR1_PAN_SHIFT 20 457#define ID_AA64MMFR1_PAN_MASK (0xf << ID_AA64MMFR1_PAN_SHIFT) 458#define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK) 459#define ID_AA64MMFR1_PAN_NONE (0x0 << ID_AA64MMFR1_PAN_SHIFT) 460#define ID_AA64MMFR1_PAN_IMPL (0x1 << ID_AA64MMFR1_PAN_SHIFT) 461#define ID_AA64MMFR1_PAN_ATS1E1 (0x2 << ID_AA64MMFR1_PAN_SHIFT) 462#define ID_AA64MMFR1_SPECSEI_SHIFT 24 463#define ID_AA64MMFR1_SPECSEI_MASK (0xf << ID_AA64MMFR1_SPECSEI_SHIFT) 464#define ID_AA64MMFR1_SPECSEI(x) ((x) & ID_AA64MMFR1_SPECSEI_MASK) 465#define ID_AA64MMFR1_SPECSEI_NONE (0x0 << ID_AA64MMFR1_SPECSEI_SHIFT) 466#define ID_AA64MMFR1_SPECSEI_IMPL (0x1 << ID_AA64MMFR1_SPECSEI_SHIFT) 467#define ID_AA64MMFR1_XNX_SHIFT 28 468#define ID_AA64MMFR1_XNX_MASK (0xf << ID_AA64MMFR1_XNX_SHIFT) 469#define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK) 470#define ID_AA64MMFR1_XNX_NONE (0x0 << ID_AA64MMFR1_XNX_SHIFT) 471#define ID_AA64MMFR1_XNX_IMPL (0x1 << ID_AA64MMFR1_XNX_SHIFT) 472 473/* ID_AA64PFR0_EL1 */ 474#define ID_AA64PFR0_MASK 0xff0000000fffffffULL 475#define ID_AA64PFR0_EL0_SHIFT 0 476#define ID_AA64PFR0_EL0_MASK (0xf << ID_AA64PFR0_EL0_SHIFT) 477#define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) 478#define ID_AA64PFR0_EL0_64 (1 << ID_AA64PFR0_EL0_SHIFT) 479#define ID_AA64PFR0_EL0_64_32 (2 << ID_AA64PFR0_EL0_SHIFT) 480#define ID_AA64PFR0_EL1_SHIFT 4 481#define ID_AA64PFR0_EL1_MASK (0xf << ID_AA64PFR0_EL1_SHIFT) 482#define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK) 483#define ID_AA64PFR0_EL1_64 (1 << ID_AA64PFR0_EL1_SHIFT) 484#define ID_AA64PFR0_EL1_64_32 (2 << ID_AA64PFR0_EL1_SHIFT) 485#define ID_AA64PFR0_EL2_SHIFT 8 486#define ID_AA64PFR0_EL2_MASK (0xf << ID_AA64PFR0_EL2_SHIFT) 487#define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK) 488#define ID_AA64PFR0_EL2_NONE (0 << ID_AA64PFR0_EL2_SHIFT) 489#define ID_AA64PFR0_EL2_64 (1 << ID_AA64PFR0_EL2_SHIFT) 490#define ID_AA64PFR0_EL2_64_32 (2 << ID_AA64PFR0_EL2_SHIFT) 491#define ID_AA64PFR0_EL3_SHIFT 12 492#define ID_AA64PFR0_EL3_MASK (0xf << ID_AA64PFR0_EL3_SHIFT) 493#define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK) 494#define ID_AA64PFR0_EL3_NONE (0 << ID_AA64PFR0_EL3_SHIFT) 495#define ID_AA64PFR0_EL3_64 (1 << ID_AA64PFR0_EL3_SHIFT) 496#define ID_AA64PFR0_EL3_64_32 (2 << ID_AA64PFR0_EL3_SHIFT) 497#define ID_AA64PFR0_FP_SHIFT 16 498#define ID_AA64PFR0_FP_MASK (0xf << ID_AA64PFR0_FP_SHIFT) 499#define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) 500#define ID_AA64PFR0_FP_IMPL (0x0 << ID_AA64PFR0_FP_SHIFT) 501#define ID_AA64PFR0_FP_NONE (0xf << ID_AA64PFR0_FP_SHIFT) 502#define ID_AA64PFR0_ADV_SIMD_SHIFT 20 503#define ID_AA64PFR0_ADV_SIMD_MASK (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 504#define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK) 505#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT) 506#define ID_AA64PFR0_ADV_SIMD_NONE (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) 507#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 508#define ID_AA64PFR0_GIC_SHIFT 24 509#define ID_AA64PFR0_GIC_MASK (0xf << ID_AA64PFR0_GIC_SHIFT) 510#define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) 511#define ID_AA64PFR0_GIC_CPUIF_NONE (0x0 << ID_AA64PFR0_GIC_SHIFT) 512#define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT) 513#define ID_AA64PFR0_DIT_SHIFT 48 514#define ID_AA64PFR0_DIT_MASK (0xfULL << ID_AA64PFR0_DIT_SHIFT) 515#define ID_AA64PFR0_DIT(x) ((x) & ID_AA64PFR0_DIT_MASK) 516#define ID_AA64PFR0_DIT_UNKNOWN (0x0ULL << ID_AA64PFR0_DIT_SHIFT) 517#define ID_AA64PFR0_DIT_IMPL (0x1ULL << ID_AA64PFR0_DIT_SHIFT) 518#define ID_AA64PFR0_CSV2_SHIFT 56 519#define ID_AA64PFR0_CSV2_MASK (0xfULL << ID_AA64PFR0_CSV2_SHIFT) 520#define ID_AA64PFR0_CSV2(x) ((x) & ID_AA64PFR0_CSV2_MASK) 521#define ID_AA64PFR0_CSV2_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV2_SHIFT) 522#define ID_AA64PFR0_CSV2_IMPL (0x1ULL << ID_AA64PFR0_CSV2_SHIFT) 523#define ID_AA64PFR0_CSV2_SCXT (0x2ULL << ID_AA64PFR0_CSV2_SHIFT) 524#define ID_AA64PFR0_CSV3_SHIFT 60 525#define ID_AA64PFR0_CSV3_MASK (0xfULL << ID_AA64PFR0_CSV3_SHIFT) 526#define ID_AA64PFR0_CSV3(x) ((x) & ID_AA64PFR0_CSV3_MASK) 527#define ID_AA64PFR0_CSV3_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV3_SHIFT) 528#define ID_AA64PFR0_CSV3_IMPL (0x1ULL << ID_AA64PFR0_CSV3_SHIFT) 529 530/* MAIR_EL1 - Memory Attribute Indirection Register */ 531#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 532#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 533#define MAIR_DEVICE_nGnRnE 0x00 534#define MAIR_NORMAL_NC 0x44 535#define MAIR_NORMAL_WT 0x88 536#define MAIR_NORMAL_WB 0xff 537 538/* PAR_EL1 - Physical Address Register */ 539#define PAR_F_SHIFT 0 540#define PAR_F (0x1 << PAR_F_SHIFT) 541#define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 542/* When PAR_F == 0 (success) */ 543#define PAR_SH_SHIFT 7 544#define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 545#define PAR_NS_SHIFT 9 546#define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 547#define PAR_PA_SHIFT 12 548#define PAR_PA_MASK 0x0000fffffffff000 549#define PAR_ATTR_SHIFT 56 550#define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 551/* When PAR_F == 1 (aborted) */ 552#define PAR_FST_SHIFT 1 553#define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 554#define PAR_PTW_SHIFT 8 555#define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 556#define PAR_S_SHIFT 9 557#define PAR_S_MASK (0x1 << PAR_S_SHIFT) 558 559/* SCTLR_EL1 - System Control Register */ 560#define SCTLR_RES0 0xffffffffc8222400 /* Reserved, write 0 */ 561#define SCTLR_RES1 0x0000000030d00800 /* Reserved, write 1 */ 562 563#define SCTLR_M 0x0000000000000001 564#define SCTLR_A 0x0000000000000002 565#define SCTLR_C 0x0000000000000004 566#define SCTLR_SA 0x0000000000000008 567#define SCTLR_SA0 0x0000000000000010 568#define SCTLR_CP15BEN 0x0000000000000020 569#define SCTLR_THEE 0x0000000000000040 570#define SCTLR_ITD 0x0000000000000080 571#define SCTLR_SED 0x0000000000000100 572#define SCTLR_UMA 0x0000000000000200 573#define SCTLR_I 0x0000000000001000 574#define SCTLR_DZE 0x0000000000004000 575#define SCTLR_UCT 0x0000000000008000 576#define SCTLR_nTWI 0x0000000000010000 577#define SCTLR_nTWE 0x0000000000040000 578#define SCTLR_WXN 0x0000000000080000 579#define SCTLR_SPAN 0x0000000000800000 580#define SCTLR_EOE 0x0000000001000000 581#define SCTLR_EE 0x0000000002000000 582#define SCTLR_UCI 0x0000000004000000 583 584/* SPSR_EL1 */ 585/* 586 * When the exception is taken in AArch64: 587 * M[4] is 0 for AArch64 mode 588 * M[3:2] is the exception level 589 * M[1] is unused 590 * M[0] is the SP select: 591 * 0: always SP0 592 * 1: current ELs SP 593 */ 594#define PSR_M_EL0t 0x00000000 595#define PSR_M_EL1t 0x00000004 596#define PSR_M_EL1h 0x00000005 597#define PSR_M_EL2t 0x00000008 598#define PSR_M_EL2h 0x00000009 599#define PSR_M_MASK 0x0000001f 600 601#define PSR_F 0x00000040 602#define PSR_I 0x00000080 603#define PSR_A 0x00000100 604#define PSR_D 0x00000200 605#define PSR_IL 0x00100000 606#define PSR_SS 0x00200000 607#define PSR_PAN 0x00400000 608#define PSR_V 0x10000000 609#define PSR_C 0x20000000 610#define PSR_Z 0x40000000 611#define PSR_N 0x80000000 612 613/* TCR_EL1 - Translation Control Register */ 614#define TCR_AS (1UL << 36) 615 616#define TCR_IPS_SHIFT 32 617#define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT) 618#define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT) 619#define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT) 620#define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT) 621#define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) 622#define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) 623 624#define TCR_TG1_SHIFT 30 625#define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) 626#define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) 627#define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) 628 629#define TCR_SH1_SHIFT 28 630#define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) 631#define TCR_ORGN1_SHIFT 26 632#define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) 633#define TCR_IRGN1_SHIFT 24 634#define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) 635 636#define TCR_A1 (1UL << 22) 637 638#define TCR_TG0_SHIFT 14 639#define TCR_TG0_4K (0UL << TCR_TG0_SHIFT) 640#define TCR_TG0_64K (1UL << TCR_TG0_SHIFT) 641#define TCR_TG0_16K (2UL << TCR_TG0_SHIFT) 642 643#define TCR_SH0_SHIFT 12 644#define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) 645#define TCR_ORGN0_SHIFT 10 646#define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) 647#define TCR_IRGN0_SHIFT 8 648#define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) 649 650#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 651 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 652#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 653 654#define TCR_T1SZ_SHIFT 16 655#define TCR_T0SZ_SHIFT 0 656#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 657#define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 658#define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 659 660/* Monitor Debug System Control Register */ 661#define DBG_MDSCR_SS (0x1 << 0) 662#define DBG_MDSCR_TDCC (0x1 << 12) 663#define DBG_MDSCR_KDE (0x1 << 13) 664#define DBG_MDSCR_MDE (0x1 << 15) 665 666/* Performance Monitoring Counters */ 667#define PMCR_E (1 << 0) /* Enable all counters */ 668#define PMCR_P (1 << 1) /* Reset all counters */ 669#define PMCR_C (1 << 2) /* Clock counter reset */ 670#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 671#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 672#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 673#define PMCR_LC (1 << 6) /* Long cycle count enable */ 674#define PMCR_IMP_SHIFT 24 /* Implementer code */ 675#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 676#define PMCR_IDCODE_SHIFT 16 /* Identification code */ 677#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 678#define PMCR_IDCODE_CORTEX_A57 0x01 679#define PMCR_IDCODE_CORTEX_A72 0x02 680#define PMCR_IDCODE_CORTEX_A53 0x03 681#define PMCR_N_SHIFT 11 /* Number of counters implemented */ 682#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 683 684/* Individual CPUs are probably best IDed by everything but the revision. */ 685#define CPU_ID_CPU_MASK 0xfffffff0 686 687/* ARM64 CPUs */ 688#define CPU_ID_CORTEX_A53 0x410fd030 689#define CPU_ID_CORTEX_A53_R1 0x411fd030 690#define CPU_ID_CORTEX_A53_MASK 0xff0ffff0 691#define CPU_ID_CORTEX_A57 0x410fd070 692#define CPU_ID_CORTEX_A57_R1 0x411fd070 693#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 694#define CPU_ID_CORTEX_A72 0x410fd080 695#define CPU_ID_CORTEX_A72_R1 0x411fd080 696#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 697 698#define I_bit (1 << 7) /* IRQ disable */ 699#define F_bit 0 /* FIQ disable - not actually used */ 700 701#endif /* !_MACHINE_ARMREG_H_ */ 702