1/* $OpenBSD: armreg.h,v 1.35 2024/06/23 10:17:16 kettenis Exp $ */ 2/*- 3 * Copyright (c) 2013, 2014 Andrew Turner 4 * Copyright (c) 2015 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Andrew Turner under 8 * sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm64/include/armreg.h 309248 2016-11-28 14:24:07Z andrew $ 32 */ 33 34#ifndef _MACHINE_ARMREG_H_ 35#define _MACHINE_ARMREG_H_ 36 37#define INSN_SIZE 4 38 39#define READ_SPECIALREG(reg) \ 40({ uint64_t val; \ 41 __asm volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \ 42 val; \ 43}) 44#define WRITE_SPECIALREG(reg, val) \ 45 __asm volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val)) 46 47/* CCSIDR_EL1 - Current Cache Size ID Register */ 48#define CCSIDR_SETS_MASK 0x0fffe000 49#define CCSIDR_SETS_SHIFT 13 50#define CCSIDR_SETS(reg) \ 51 ((((reg) & CCSIDR_SETS_MASK) >> CCSIDR_SETS_SHIFT) + 1) 52#define CCSIDR_WAYS_MASK 0x00001ff8 53#define CCSIDR_WAYS_SHIFT 3 54#define CCSIDR_WAYS(reg) \ 55 ((((reg) & CCSIDR_WAYS_MASK) >> CCSIDR_WAYS_SHIFT) + 1) 56#define CCSIDR_LINE_MASK 0x00000007 57#define CCSIDR_LINE_SIZE(reg) (1 << (((reg) & CCSIDR_LINE_MASK) + 4)) 58 59#define CCSIDR_CCIDX_SETS_MASK 0x00ffffff00000000ULL 60#define CCSIDR_CCIDX_SETS_SHIFT 32 61#define CCSIDR_CCIDX_SETS(reg) \ 62 ((((reg) & CCSIDR_CCIDX_SETS_MASK) >> CCSIDR_CCIDX_SETS_SHIFT) + 1) 63#define CCSIDR_CCIDX_WAYS_MASK 0x0000000000fffff8ULL 64#define CCSIDR_CCIDX_WAYS_SHIFT 3 65#define CCSIDR_CCIDX_WAYS(reg) \ 66 ((((reg) & CCSIDR_CCIDX_WAYS_MASK) >> CCSIDR_CCIDX_WAYS_SHIFT) + 1) 67#define CCSIDR_CCIDX_LINE_MASK 0x0000000000000007ULL 68#define CCSIDR_CCIDX_LINE_SIZE(reg) \ 69 (1 << (((reg) & CCSIDR_CCIDX_LINE_MASK) + 4)) 70 71/* CLIDR_EL1 - Cache Level ID Register */ 72#define CLIDR_CTYPE_MASK 0x7 73#define CLIDR_CTYPE_INSN 0x1 74#define CLIDR_CTYPE_DATA 0x2 75#define CLIDR_CTYPE_UNIFIED 0x4 76 77/* CNTHCTL_EL2 - Counter-timer Hypervisor Control Register */ 78#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 79#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 80#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 81#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 82#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 83 84/* CNTKCTL_EL1 - Counter-timer Kernel Control Register */ 85#define CNTKCTL_EL0VCTEN (1 << 1) /* Allow EL0 virtual counter access */ 86 87/* CNTV_CTL_EL0 */ 88#define CNTV_CTL_ENABLE (1 << 0) 89#define CNTV_CTL_IMASK (1 << 1) 90#define CNTV_CTL_ISTATUS (1 << 2) 91 92/* CPACR_EL1 */ 93#define CPACR_FPEN_MASK (0x3 << 20) 94#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 95#define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 96#define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 97#define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 98#define CPACR_TTA (0x1 << 28) 99 100/* CSSELR_EL1 - Cache Size Selection Register */ 101#define CSSELR_IND (1 << 0) 102#define CSSELR_LEVEL_SHIFT 1 103 104/* CTR_EL0 - Cache Type Register */ 105#define CTR_DLINE_SHIFT 16 106#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 107#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) 108#define CTR_IL1P_SHIFT 14 109#define CTR_IL1P_MASK (0x3 << CTR_IL1P_SHIFT) 110#define CTR_IL1P_AIVIVT (0x1 << CTR_IL1P_SHIFT) 111#define CTR_IL1P_VIPT (0x2 << CTR_IL1P_SHIFT) 112#define CTR_IL1P_PIPT (0x3 << CTR_IL1P_SHIFT) 113#define CTR_ILINE_SHIFT 0 114#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 115#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) 116 117/* MPIDR_EL1 - Multiprocessor Affinity Register */ 118#define MPIDR_AFF3 (0xFFULL << 32) 119#define MPIDR_AFF2 (0xFFULL << 16) 120#define MPIDR_AFF1 (0xFFULL << 8) 121#define MPIDR_AFF0 (0xFFULL << 0) 122#define MPIDR_AFF (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0) 123 124/* DCZID_EL0 - Data Cache Zero ID register */ 125#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 126#define DCZID_BS_SHIFT 0 127#define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 128#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 129 130/* ESR_ELx */ 131#define ESR_ELx_ISS_MASK 0x00ffffff 132#define ISS_INSN_FnV (0x01 << 10) 133#define ISS_INSN_EA (0x01 << 9) 134#define ISS_INSN_S1PTW (0x01 << 7) 135#define ISS_INSN_IFSC_MASK (0x1f << 0) 136#define ISS_DATA_ISV (0x01 << 24) 137#define ISS_DATA_SAS_MASK (0x03 << 22) 138#define ISS_DATA_SSE (0x01 << 21) 139#define ISS_DATA_SRT_MASK (0x1f << 16) 140#define ISS_DATA_SF (0x01 << 15) 141#define ISS_DATA_AR (0x01 << 14) 142#define ISS_DATA_FnV (0x01 << 10) 143#define ISS_DATA_EA (0x01 << 9) 144#define ISS_DATA_CM (0x01 << 8) 145#define ISS_INSN_S1PTW (0x01 << 7) 146#define ISS_DATA_WnR (0x01 << 6) 147#define ISS_DATA_DFSC_MASK (0x3f << 0) 148#define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 149#define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 150#define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 151#define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 152#define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 153#define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 154#define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 155#define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 156#define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 157#define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 158#define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 159#define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 160#define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 161#define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 162#define ISS_DATA_DFSC_EXT (0x10 << 0) 163#define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 164#define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 165#define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 166#define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 167#define ISS_DATA_DFSC_ECC (0x18 << 0) 168#define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 169#define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 170#define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 171#define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 172#define ISS_DATA_DFSC_ALIGN (0x21 << 0) 173#define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 174#define ESR_ELx_IL (0x01 << 25) 175#define ESR_ELx_EC_SHIFT 26 176#define ESR_ELx_EC_MASK (0x3f << 26) 177#define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 178#define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 179#define EXCP_FP_SIMD 0x07 /* FP/SIMD trap */ 180#define EXCP_BRANCH_TGT 0x0d /* Branch target exception */ 181#define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 182#define EXCP_SVC 0x15 /* SVC trap */ 183#define EXCP_MSR 0x18 /* MSR/MRS trap */ 184#define EXCP_FPAC 0x1c /* Faulting PAC trap */ 185#define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 186#define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 187#define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 188#define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 189#define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 190#define EXCP_SP_ALIGN 0x26 /* SP alignment fault */ 191#define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 192#define EXCP_SERROR 0x2f /* SError interrupt */ 193#define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 194#define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 195#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 196#define EXCP_BRK 0x3c /* Breakpoint */ 197 198/* ICC_CTLR_EL1 */ 199#define ICC_CTLR_EL1_EOIMODE (1U << 1) 200#define ICC_CTLR_EL1_PRIBITS_SHIFT 8 201#define ICC_CTLR_EL1_PRIBITS_MASK (0x7UL << 8) 202#define ICC_CTLR_EL1_PRIBITS(reg) \ 203 (((reg) & ICC_CTLR_EL1_PRIBITS_MASK) >> ICC_CTLR_EL1_PRIBITS_SHIFT) 204 205/* ICC_IAR1_EL1 */ 206#define ICC_IAR1_EL1_SPUR (0x03ff) 207 208/* ICC_IGRPEN0_EL1 */ 209#define ICC_IGRPEN0_EL1_EN (1U << 0) 210 211/* ICC_PMR_EL1 */ 212#define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 213 214/* ICC_SGI1R_EL1 */ 215#define ICC_SGI1R_EL1_TL_MASK 0xffffUL 216#define ICC_SGI1R_EL1_AFF1_SHIFT 16 217#define ICC_SGI1R_EL1_SGIID_SHIFT 24 218#define ICC_SGI1R_EL1_AFF2_SHIFT 32 219#define ICC_SGI1R_EL1_AFF3_SHIFT 48 220#define ICC_SGI1R_EL1_SGIID_MASK 0xfUL 221#define ICC_SGI1R_EL1_IRM (0x1UL << 40) 222 223/* ICC_SRE_EL1 */ 224#define ICC_SRE_EL1_SRE (1U << 0) 225 226/* ICC_SRE_EL2 */ 227#define ICC_SRE_EL2_SRE (1U << 0) 228#define ICC_SRE_EL2_EN (1U << 3) 229 230/* ID_AA64DFR0_EL1 */ 231#define ID_AA64DFR0_MASK 0x00000000f0f0ffffUL 232#define ID_AA64DFR0_DEBUG_VER_SHIFT 0 233#define ID_AA64DFR0_DEBUG_VER_MASK (0xfULL << ID_AA64DFR0_DEBUG_VER_SHIFT) 234#define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) 235#define ID_AA64DFR0_DEBUG_VER_8 (0x6ULL << ID_AA64DFR0_DEBUG_VER_SHIFT) 236#define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7ULL << ID_AA64DFR0_DEBUG_VER_SHIFT) 237#define ID_AA64DFR0_TRACE_VER_SHIFT 4 238#define ID_AA64DFR0_TRACE_VER_MASK (0xfULL << ID_AA64DFR0_TRACE_VER_SHIFT) 239#define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) 240#define ID_AA64DFR0_TRACE_VER_NONE (0x0ULL << ID_AA64DFR0_TRACE_VER_SHIFT) 241#define ID_AA64DFR0_TRACE_VER_IMPL (0x1ULL << ID_AA64DFR0_TRACE_VER_SHIFT) 242#define ID_AA64DFR0_PMU_VER_SHIFT 8 243#define ID_AA64DFR0_PMU_VER_MASK (0xfULL << ID_AA64DFR0_PMU_VER_SHIFT) 244#define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK) 245#define ID_AA64DFR0_PMU_VER_NONE (0x0ULL << ID_AA64DFR0_PMU_VER_SHIFT) 246#define ID_AA64DFR0_PMU_VER_3 (0x1ULL << ID_AA64DFR0_PMU_VER_SHIFT) 247#define ID_AA64DFR0_PMU_VER_3_1 (0x4ULL << ID_AA64DFR0_PMU_VER_SHIFT) 248#define ID_AA64DFR0_PMU_VER_IMPL (0xfULL << ID_AA64DFR0_PMU_VER_SHIFT) 249#define ID_AA64DFR0_BRPS_SHIFT 12 250#define ID_AA64DFR0_BRPS_MASK (0xfULL << ID_AA64DFR0_BRPS_SHIFT) 251#define ID_AA64DFR0_BRPS(x) \ 252 ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1) 253#define ID_AA64DFR0_WRPS_SHIFT 20 254#define ID_AA64DFR0_WRPS_MASK (0xfULL << ID_AA64DFR0_WRPS_SHIFT) 255#define ID_AA64DFR0_WRPS(x) \ 256 ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1) 257#define ID_AA64DFR0_CTX_CMPS_SHIFT 28 258#define ID_AA64DFR0_CTX_CMPS_MASK (0xfULL << ID_AA64DFR0_CTX_CMPS_SHIFT) 259#define ID_AA64DFR0_CTX_CMPS(x) \ 260 ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) 261 262/* ID_AA64ISAR0_EL1 */ 263#define ID_AA64ISAR0_MASK 0xfffffffff0fffff0ULL 264#define ID_AA64ISAR0_AES_SHIFT 4 265#define ID_AA64ISAR0_AES_MASK (0xfULL << ID_AA64ISAR0_AES_SHIFT) 266#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) 267#define ID_AA64ISAR0_AES_NONE (0x0ULL << ID_AA64ISAR0_AES_SHIFT) 268#define ID_AA64ISAR0_AES_BASE (0x1ULL << ID_AA64ISAR0_AES_SHIFT) 269#define ID_AA64ISAR0_AES_PMULL (0x2ULL << ID_AA64ISAR0_AES_SHIFT) 270#define ID_AA64ISAR0_SHA1_SHIFT 8 271#define ID_AA64ISAR0_SHA1_MASK (0xfULL << ID_AA64ISAR0_SHA1_SHIFT) 272#define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 273#define ID_AA64ISAR0_SHA1_NONE (0x0ULL << ID_AA64ISAR0_SHA1_SHIFT) 274#define ID_AA64ISAR0_SHA1_BASE (0x1ULL << ID_AA64ISAR0_SHA1_SHIFT) 275#define ID_AA64ISAR0_SHA2_SHIFT 12 276#define ID_AA64ISAR0_SHA2_MASK (0xfULL << ID_AA64ISAR0_SHA2_SHIFT) 277#define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 278#define ID_AA64ISAR0_SHA2_NONE (0x0ULL << ID_AA64ISAR0_SHA2_SHIFT) 279#define ID_AA64ISAR0_SHA2_BASE (0x1ULL << ID_AA64ISAR0_SHA2_SHIFT) 280#define ID_AA64ISAR0_SHA2_512 (0x2ULL << ID_AA64ISAR0_SHA2_SHIFT) 281#define ID_AA64ISAR0_CRC32_SHIFT 16 282#define ID_AA64ISAR0_CRC32_MASK (0xfULL << ID_AA64ISAR0_CRC32_SHIFT) 283#define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 284#define ID_AA64ISAR0_CRC32_NONE (0x0ULL << ID_AA64ISAR0_CRC32_SHIFT) 285#define ID_AA64ISAR0_CRC32_BASE (0x1ULL << ID_AA64ISAR0_CRC32_SHIFT) 286#define ID_AA64ISAR0_ATOMIC_SHIFT 20 287#define ID_AA64ISAR0_ATOMIC_MASK (0xfULL << ID_AA64ISAR0_ATOMIC_SHIFT) 288#define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK) 289#define ID_AA64ISAR0_ATOMIC_NONE (0x0ULL << ID_AA64ISAR0_ATOMIC_SHIFT) 290#define ID_AA64ISAR0_ATOMIC_IMPL (0x2ULL << ID_AA64ISAR0_ATOMIC_SHIFT) 291#define ID_AA64ISAR0_RDM_SHIFT 28 292#define ID_AA64ISAR0_RDM_MASK (0xfULL << ID_AA64ISAR0_RDM_SHIFT) 293#define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK) 294#define ID_AA64ISAR0_RDM_NONE (0x0ULL << ID_AA64ISAR0_RDM_SHIFT) 295#define ID_AA64ISAR0_RDM_IMPL (0x1ULL << ID_AA64ISAR0_RDM_SHIFT) 296#define ID_AA64ISAR0_SHA3_SHIFT 32 297#define ID_AA64ISAR0_SHA3_MASK (0xfULL << ID_AA64ISAR0_SHA3_SHIFT) 298#define ID_AA64ISAR0_SHA3(x) ((x) & ID_AA64ISAR0_SHA3_MASK) 299#define ID_AA64ISAR0_SHA3_NONE (0x0ULL << ID_AA64ISAR0_SHA3_SHIFT) 300#define ID_AA64ISAR0_SHA3_IMPL (0x1ULL << ID_AA64ISAR0_SHA3_SHIFT) 301#define ID_AA64ISAR0_SM3_SHIFT 36 302#define ID_AA64ISAR0_SM3_MASK (0xfULL << ID_AA64ISAR0_SM3_SHIFT) 303#define ID_AA64ISAR0_SM3(x) ((x) & ID_AA64ISAR0_SM3_MASK) 304#define ID_AA64ISAR0_SM3_NONE (0x0ULL << ID_AA64ISAR0_SM3_SHIFT) 305#define ID_AA64ISAR0_SM3_IMPL (0x1ULL << ID_AA64ISAR0_SM3_SHIFT) 306#define ID_AA64ISAR0_SM4_SHIFT 40 307#define ID_AA64ISAR0_SM4_MASK (0xfULL << ID_AA64ISAR0_SM4_SHIFT) 308#define ID_AA64ISAR0_SM4(x) ((x) & ID_AA64ISAR0_SM4_MASK) 309#define ID_AA64ISAR0_SM4_NONE (0x0ULL << ID_AA64ISAR0_SM4_SHIFT) 310#define ID_AA64ISAR0_SM4_IMPL (0x1ULL << ID_AA64ISAR0_SM4_SHIFT) 311#define ID_AA64ISAR0_DP_SHIFT 44 312#define ID_AA64ISAR0_DP_MASK (0xfULL << ID_AA64ISAR0_DP_SHIFT) 313#define ID_AA64ISAR0_DP(x) ((x) & ID_AA64ISAR0_DP_MASK) 314#define ID_AA64ISAR0_DP_NONE (0x0ULL << ID_AA64ISAR0_DP_SHIFT) 315#define ID_AA64ISAR0_DP_IMPL (0x1ULL << ID_AA64ISAR0_DP_SHIFT) 316#define ID_AA64ISAR0_FHM_SHIFT 48 317#define ID_AA64ISAR0_FHM_MASK (0xfULL << ID_AA64ISAR0_FHM_SHIFT) 318#define ID_AA64ISAR0_FHM(x) ((x) & ID_AA64ISAR0_FHM_MASK) 319#define ID_AA64ISAR0_FHM_NONE (0x0ULL << ID_AA64ISAR0_FHM_SHIFT) 320#define ID_AA64ISAR0_FHM_IMPL (0x1ULL << ID_AA64ISAR0_FHM_SHIFT) 321#define ID_AA64ISAR0_TS_SHIFT 52 322#define ID_AA64ISAR0_TS_MASK (0xfULL << ID_AA64ISAR0_TS_SHIFT) 323#define ID_AA64ISAR0_TS(x) ((x) & ID_AA64ISAR0_TS_MASK) 324#define ID_AA64ISAR0_TS_NONE (0x0ULL << ID_AA64ISAR0_TS_SHIFT) 325#define ID_AA64ISAR0_TS_BASE (0x1ULL << ID_AA64ISAR0_TS_SHIFT) 326#define ID_AA64ISAR0_TS_AXFLAG (0x2ULL << ID_AA64ISAR0_TS_SHIFT) 327#define ID_AA64ISAR0_TLB_SHIFT 56 328#define ID_AA64ISAR0_TLB_MASK (0xfULL << ID_AA64ISAR0_TLB_SHIFT) 329#define ID_AA64ISAR0_TLB(x) ((x) & ID_AA64ISAR0_TLB_MASK) 330#define ID_AA64ISAR0_TLB_NONE (0x0ULL << ID_AA64ISAR0_TLB_SHIFT) 331#define ID_AA64ISAR0_TLB_IOS (0x1ULL << ID_AA64ISAR0_TLB_SHIFT) 332#define ID_AA64ISAR0_TLB_IRANGE (0x2ULL << ID_AA64ISAR0_TLB_SHIFT) 333#define ID_AA64ISAR0_RNDR_SHIFT 60 334#define ID_AA64ISAR0_RNDR_MASK (0xfULL << ID_AA64ISAR0_RNDR_SHIFT) 335#define ID_AA64ISAR0_RNDR(x) ((x) & ID_AA64ISAR0_RNDR_MASK) 336#define ID_AA64ISAR0_RNDR_NONE (0x0ULL << ID_AA64ISAR0_RNDR_SHIFT) 337#define ID_AA64ISAR0_RNDR_IMPL (0x1ULL << ID_AA64ISAR0_RNDR_SHIFT) 338 339/* ID_AA64ISAR1_EL1 */ 340#define ID_AA64ISAR1_MASK 0xffffffffffffffffULL 341#define ID_AA64ISAR1_DPB_SHIFT 0 342#define ID_AA64ISAR1_DPB_MASK (0xfULL << ID_AA64ISAR1_DPB_SHIFT) 343#define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK) 344#define ID_AA64ISAR1_DPB_NONE (0x0ULL << ID_AA64ISAR1_DPB_SHIFT) 345#define ID_AA64ISAR1_DPB_IMPL (0x1ULL << ID_AA64ISAR1_DPB_SHIFT) 346#define ID_AA64ISAR1_APA_SHIFT 4 347#define ID_AA64ISAR1_APA_MASK (0xfULL << ID_AA64ISAR1_APA_SHIFT) 348#define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK) 349#define ID_AA64ISAR1_APA_NONE (0x0ULL << ID_AA64ISAR1_APA_SHIFT) 350#define ID_AA64ISAR1_APA_BASE (0x1ULL << ID_AA64ISAR1_APA_SHIFT) 351#define ID_AA64ISAR1_APA_PAC (0x2ULL << ID_AA64ISAR1_APA_SHIFT) 352#define ID_AA64ISAR1_API_SHIFT 8 353#define ID_AA64ISAR1_API_MASK (0xfULL << ID_AA64ISAR1_API_SHIFT) 354#define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK) 355#define ID_AA64ISAR1_API_NONE (0x0ULL << ID_AA64ISAR1_API_SHIFT) 356#define ID_AA64ISAR1_API_BASE (0x1ULL << ID_AA64ISAR1_API_SHIFT) 357#define ID_AA64ISAR1_API_PAC (0x2ULL << ID_AA64ISAR1_API_SHIFT) 358#define ID_AA64ISAR1_JSCVT_SHIFT 12 359#define ID_AA64ISAR1_JSCVT_MASK (0xfULL << ID_AA64ISAR1_JSCVT_SHIFT) 360#define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) 361#define ID_AA64ISAR1_JSCVT_NONE (0x0ULL << ID_AA64ISAR1_JSCVT_SHIFT) 362#define ID_AA64ISAR1_JSCVT_IMPL (0x1ULL << ID_AA64ISAR1_JSCVT_SHIFT) 363#define ID_AA64ISAR1_FCMA_SHIFT 16 364#define ID_AA64ISAR1_FCMA_MASK (0xfULL << ID_AA64ISAR1_FCMA_SHIFT) 365#define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK) 366#define ID_AA64ISAR1_FCMA_NONE (0x0ULL << ID_AA64ISAR1_FCMA_SHIFT) 367#define ID_AA64ISAR1_FCMA_IMPL (0x1ULL << ID_AA64ISAR1_FCMA_SHIFT) 368#define ID_AA64ISAR1_LRCPC_SHIFT 20 369#define ID_AA64ISAR1_LRCPC_MASK (0xfULL << ID_AA64ISAR1_LRCPC_SHIFT) 370#define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) 371#define ID_AA64ISAR1_LRCPC_NONE (0x0ULL << ID_AA64ISAR1_LRCPC_SHIFT) 372#define ID_AA64ISAR1_LRCPC_BASE (0x1ULL << ID_AA64ISAR1_LRCPC_SHIFT) 373#define ID_AA64ISAR1_LRCPC_LDAPUR (0x2ULL << ID_AA64ISAR1_LRCPC_SHIFT) 374#define ID_AA64ISAR1_GPA_SHIFT 24 375#define ID_AA64ISAR1_GPA_MASK (0xfULL << ID_AA64ISAR1_GPA_SHIFT) 376#define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK) 377#define ID_AA64ISAR1_GPA_NONE (0x0ULL << ID_AA64ISAR1_GPA_SHIFT) 378#define ID_AA64ISAR1_GPA_IMPL (0x1ULL << ID_AA64ISAR1_GPA_SHIFT) 379#define ID_AA64ISAR1_GPI_SHIFT 28 380#define ID_AA64ISAR1_GPI_MASK (0xfULL << ID_AA64ISAR1_GPI_SHIFT) 381#define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK) 382#define ID_AA64ISAR1_GPI_NONE (0x0ULL << ID_AA64ISAR1_GPI_SHIFT) 383#define ID_AA64ISAR1_GPI_IMPL (0x1ULL << ID_AA64ISAR1_GPI_SHIFT) 384#define ID_AA64ISAR1_FRINTTS_SHIFT 32 385#define ID_AA64ISAR1_FRINTTS_MASK (0xfULL << ID_AA64ISAR1_FRINTTS_SHIFT) 386#define ID_AA64ISAR1_FRINTTS(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) 387#define ID_AA64ISAR1_FRINTTS_NONE (0x0ULL << ID_AA64ISAR1_FRINTTS_SHIFT) 388#define ID_AA64ISAR1_FRINTTS_IMPL (0x1ULL << ID_AA64ISAR1_FRINTTS_SHIFT) 389#define ID_AA64ISAR1_SB_SHIFT 36 390#define ID_AA64ISAR1_SB_MASK (0xfULL << ID_AA64ISAR1_SB_SHIFT) 391#define ID_AA64ISAR1_SB(x) ((x) & ID_AA64ISAR1_SB_MASK) 392#define ID_AA64ISAR1_SB_NONE (0x0ULL << ID_AA64ISAR1_SB_SHIFT) 393#define ID_AA64ISAR1_SB_IMPL (0x1ULL << ID_AA64ISAR1_SB_SHIFT) 394#define ID_AA64ISAR1_SPECRES_SHIFT 40 395#define ID_AA64ISAR1_SPECRES_MASK (0xfULL << ID_AA64ISAR1_SPECRES_SHIFT) 396#define ID_AA64ISAR1_SPECRES(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) 397#define ID_AA64ISAR1_SPECRES_NONE (0x0ULL << ID_AA64ISAR1_SPECRES_SHIFT) 398#define ID_AA64ISAR1_SPECRES_IMPL (0x1ULL << ID_AA64ISAR1_SPECRES_SHIFT) 399#define ID_AA64ISAR1_BF16_SHIFT 44 400#define ID_AA64ISAR1_BF16_MASK (0xfULL << ID_AA64ISAR1_BF16_SHIFT) 401#define ID_AA64ISAR1_BF16(x) ((x) & ID_AA64ISAR1_BF16_MASK) 402#define ID_AA64ISAR1_BF16_NONE (0x0ULL << ID_AA64ISAR1_BF16_SHIFT) 403#define ID_AA64ISAR1_BF16_BASE (0x1ULL << ID_AA64ISAR1_BF16_SHIFT) 404#define ID_AA64ISAR1_BF16_EBF (0x2ULL << ID_AA64ISAR1_BF16_SHIFT) 405#define ID_AA64ISAR1_DGH_SHIFT 48 406#define ID_AA64ISAR1_DGH_MASK (0xfULL << ID_AA64ISAR1_DGH_SHIFT) 407#define ID_AA64ISAR1_DGH(x) ((x) & ID_AA64ISAR1_DGH_MASK) 408#define ID_AA64ISAR1_DGH_NONE (0x0ULL << ID_AA64ISAR1_DGH_SHIFT) 409#define ID_AA64ISAR1_DGH_IMPL (0x1ULL << ID_AA64ISAR1_DGH_SHIFT) 410#define ID_AA64ISAR1_I8MM_SHIFT 52 411#define ID_AA64ISAR1_I8MM_MASK (0xfULL << ID_AA64ISAR1_I8MM_SHIFT) 412#define ID_AA64ISAR1_I8MM(x) ((x) & ID_AA64ISAR1_I8MM_MASK) 413#define ID_AA64ISAR1_I8MM_NONE (0x0ULL << ID_AA64ISAR1_I8MM_SHIFT) 414#define ID_AA64ISAR1_I8MM_IMPL (0x1ULL << ID_AA64ISAR1_I8MM_SHIFT) 415#define ID_AA64ISAR1_XS_SHIFT 56 416#define ID_AA64ISAR1_XS_MASK (0xfULL << ID_AA64ISAR1_XS_SHIFT) 417#define ID_AA64ISAR1_XS(x) ((x) & ID_AA64ISAR1_XS_MASK) 418#define ID_AA64ISAR1_XS_NONE (0x0ULL << ID_AA64ISAR1_XS_SHIFT) 419#define ID_AA64ISAR1_XS_IMPL (0x1ULL << ID_AA64ISAR1_XS_SHIFT) 420#define ID_AA64ISAR1_LS64_SHIFT 60 421#define ID_AA64ISAR1_LS64_MASK (0xfULL << ID_AA64ISAR1_LS64_SHIFT) 422#define ID_AA64ISAR1_LS64(x) ((x) & ID_AA64ISAR1_LS64_MASK) 423#define ID_AA64ISAR1_LS64_NONE (0x0ULL << ID_AA64ISAR1_LS64_SHIFT) 424#define ID_AA64ISAR1_LS64_BASE (0x1ULL << ID_AA64ISAR1_LS64_SHIFT) 425#define ID_AA64ISAR1_LS64_V (0x2ULL << ID_AA64ISAR1_LS64_SHIFT) 426#define ID_AA64ISAR1_LS64_ACCDATA (0x3ULL << ID_AA64ISAR1_LS64_SHIFT) 427 428/* ID_AA64ISAR2_EL1 */ 429#define ID_AA64ISAR2_MASK 0x00000000f0000000ULL 430#define ID_AA64ISAR2_CLRBHB_SHIFT 28 431#define ID_AA64ISAR2_CLRBHB_MASK (0xfULL << ID_AA64ISAR2_CLRBHB_SHIFT) 432#define ID_AA64ISAR2_CLRBHB(x) ((x) & ID_AA64ISAR2_CLRBHB_MASK) 433#define ID_AA64ISAR2_CLRBHB_NONE (0x0ULL << ID_AA64ISAR2_CLRBHB_SHIFT) 434#define ID_AA64ISAR2_CLRBHB_IMPL (0x1ULL << ID_AA64ISAR2_CLRBHB_SHIFT) 435 436/* ID_AA64MMFR0_EL1 */ 437#define ID_AA64MMFR0_MASK 0x00000000ffffffffULL 438#define ID_AA64MMFR0_PA_RANGE_SHIFT 0 439#define ID_AA64MMFR0_PA_RANGE_MASK (0xfULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 440#define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK) 441#define ID_AA64MMFR0_PA_RANGE_4G (0x0ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 442#define ID_AA64MMFR0_PA_RANGE_64G (0x1ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 443#define ID_AA64MMFR0_PA_RANGE_1T (0x2ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 444#define ID_AA64MMFR0_PA_RANGE_4T (0x3ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 445#define ID_AA64MMFR0_PA_RANGE_16T (0x4ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 446#define ID_AA64MMFR0_PA_RANGE_256T (0x5ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 447#define ID_AA64MMFR0_ASID_BITS_SHIFT 4 448#define ID_AA64MMFR0_ASID_BITS_MASK (0xfULL << ID_AA64MMFR0_ASID_BITS_SHIFT) 449#define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK) 450#define ID_AA64MMFR0_ASID_BITS_8 (0x0ULL << ID_AA64MMFR0_ASID_BITS_SHIFT) 451#define ID_AA64MMFR0_ASID_BITS_16 (0x2ULL << ID_AA64MMFR0_ASID_BITS_SHIFT) 452#define ID_AA64MMFR0_BIGEND_SHIFT 8 453#define ID_AA64MMFR0_BIGEND_MASK (0xfULL << ID_AA64MMFR0_BIGEND_SHIFT) 454#define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK) 455#define ID_AA64MMFR0_BIGEND_FIXED (0x0ULL << ID_AA64MMFR0_BIGEND_SHIFT) 456#define ID_AA64MMFR0_BIGEND_MIXED (0x1ULL << ID_AA64MMFR0_BIGEND_SHIFT) 457#define ID_AA64MMFR0_S_NS_MEM_SHIFT 12 458#define ID_AA64MMFR0_S_NS_MEM_MASK (0xfULL << ID_AA64MMFR0_S_NS_MEM_SHIFT) 459#define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK) 460#define ID_AA64MMFR0_S_NS_MEM_NONE (0x0ULL << ID_AA64MMFR0_S_NS_MEM_SHIFT) 461#define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1ULL << ID_AA64MMFR0_S_NS_MEM_SHIFT) 462#define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16 463#define ID_AA64MMFR0_BIGEND_EL0_MASK (0xfULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 464#define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK) 465#define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0ULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 466#define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1ULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 467#define ID_AA64MMFR0_TGRAN16_SHIFT 20 468#define ID_AA64MMFR0_TGRAN16_MASK (0xfULL << ID_AA64MMFR0_TGRAN16_SHIFT) 469#define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK) 470#define ID_AA64MMFR0_TGRAN16_NONE (0x0ULL << ID_AA64MMFR0_TGRAN16_SHIFT) 471#define ID_AA64MMFR0_TGRAN16_IMPL (0x1ULL << ID_AA64MMFR0_TGRAN16_SHIFT) 472#define ID_AA64MMFR0_TGRAN64_SHIFT 24 473#define ID_AA64MMFR0_TGRAN64_MASK (0xfULL << ID_AA64MMFR0_TGRAN64_SHIFT) 474#define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK) 475#define ID_AA64MMFR0_TGRAN64_IMPL (0x0ULL << ID_AA64MMFR0_TGRAN64_SHIFT) 476#define ID_AA64MMFR0_TGRAN64_NONE (0xfULL << ID_AA64MMFR0_TGRAN64_SHIFT) 477#define ID_AA64MMFR0_TGRAN4_SHIFT 28 478#define ID_AA64MMFR0_TGRAN4_MASK (0xfULL << ID_AA64MMFR0_TGRAN4_SHIFT) 479#define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK) 480#define ID_AA64MMFR0_TGRAN4_IMPL (0x0ULL << ID_AA64MMFR0_TGRAN4_SHIFT) 481#define ID_AA64MMFR0_TGRAN4_NONE (0xfULL << ID_AA64MMFR0_TGRAN4_SHIFT) 482 483/* ID_AA64MMFR1_EL1 */ 484#define ID_AA64MMFR1_MASK 0xf0000000ffffffffULL 485#define ID_AA64MMFR1_HAFDBS_SHIFT 0 486#define ID_AA64MMFR1_HAFDBS_MASK (0xfULL << ID_AA64MMFR1_HAFDBS_SHIFT) 487#define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 488#define ID_AA64MMFR1_HAFDBS_NONE (0x0ULL << ID_AA64MMFR1_HAFDBS_SHIFT) 489#define ID_AA64MMFR1_HAFDBS_AF (0x1ULL << ID_AA64MMFR1_HAFDBS_SHIFT) 490#define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2ULL << ID_AA64MMFR1_HAFDBS_SHIFT) 491#define ID_AA64MMFR1_VMIDBITS_SHIFT 4 492#define ID_AA64MMFR1_VMIDBITS_MASK (0xfULL << ID_AA64MMFR1_VMIDBITS_SHIFT) 493#define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK) 494#define ID_AA64MMFR1_VMIDBITS_8 (0x0ULL << ID_AA64MMFR1_VMIDBITS_SHIFT) 495#define ID_AA64MMFR1_VMIDBITS_16 (0x2ULL << ID_AA64MMFR1_VMIDBITS_SHIFT) 496#define ID_AA64MMFR1_VH_SHIFT 8 497#define ID_AA64MMFR1_VH_MASK (0xfULL << ID_AA64MMFR1_VH_SHIFT) 498#define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK) 499#define ID_AA64MMFR1_VH_NONE (0x0ULL << ID_AA64MMFR1_VH_SHIFT) 500#define ID_AA64MMFR1_VH_IMPL (0x1ULL << ID_AA64MMFR1_VH_SHIFT) 501#define ID_AA64MMFR1_HPDS_SHIFT 12 502#define ID_AA64MMFR1_HPDS_MASK (0xfULL << ID_AA64MMFR1_HPDS_SHIFT) 503#define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 504#define ID_AA64MMFR1_HPDS_NONE (0x0ULL << ID_AA64MMFR1_HPDS_SHIFT) 505#define ID_AA64MMFR1_HPDS_IMPL (0x1ULL << ID_AA64MMFR1_HPDS_SHIFT) 506#define ID_AA64MMFR1_LO_SHIFT 16 507#define ID_AA64MMFR1_LO_MASK (0xfULL << ID_AA64MMFR1_LO_SHIFT) 508#define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK) 509#define ID_AA64MMFR1_LO_NONE (0x0ULL << ID_AA64MMFR1_LO_SHIFT) 510#define ID_AA64MMFR1_LO_IMPL (0x1ULL << ID_AA64MMFR1_LO_SHIFT) 511#define ID_AA64MMFR1_PAN_SHIFT 20 512#define ID_AA64MMFR1_PAN_MASK (0xfULL << ID_AA64MMFR1_PAN_SHIFT) 513#define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK) 514#define ID_AA64MMFR1_PAN_NONE (0x0ULL << ID_AA64MMFR1_PAN_SHIFT) 515#define ID_AA64MMFR1_PAN_IMPL (0x1ULL << ID_AA64MMFR1_PAN_SHIFT) 516#define ID_AA64MMFR1_PAN_ATS1E1 (0x2ULL << ID_AA64MMFR1_PAN_SHIFT) 517#define ID_AA64MMFR1_PAN_EPAN (0x3ULL << ID_AA64MMFR1_PAN_SHIFT) 518#define ID_AA64MMFR1_SPECSEI_SHIFT 24 519#define ID_AA64MMFR1_SPECSEI_MASK (0xfULL << ID_AA64MMFR1_SPECSEI_SHIFT) 520#define ID_AA64MMFR1_SPECSEI(x) ((x) & ID_AA64MMFR1_SPECSEI_MASK) 521#define ID_AA64MMFR1_SPECSEI_NONE (0x0ULL << ID_AA64MMFR1_SPECSEI_SHIFT) 522#define ID_AA64MMFR1_SPECSEI_IMPL (0x1ULL << ID_AA64MMFR1_SPECSEI_SHIFT) 523#define ID_AA64MMFR1_XNX_SHIFT 28 524#define ID_AA64MMFR1_XNX_MASK (0xfULL << ID_AA64MMFR1_XNX_SHIFT) 525#define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK) 526#define ID_AA64MMFR1_XNX_NONE (0x0ULL << ID_AA64MMFR1_XNX_SHIFT) 527#define ID_AA64MMFR1_XNX_IMPL (0x1ULL << ID_AA64MMFR1_XNX_SHIFT) 528#define ID_AA64MMFR1_ECBHB_SHIFT 60 529#define ID_AA64MMFR1_ECBHB_MASK (0xfULL << ID_AA64MMFR1_ECBHB_SHIFT) 530#define ID_AA64MMFR1_ECBHB(x) ((x) & ID_AA64MMFR1_ECBHB_MASK) 531#define ID_AA64MMFR1_ECBHB_NONE (0x0ULL << ID_AA64MMFR1_ECBHB_SHIFT) 532#define ID_AA64MMFR1_ECBHB_IMPL (0x1ULL << ID_AA64MMFR1_ECBHB_SHIFT) 533 534/* ID_AA64MMFR2_EL1 */ 535#define ID_AA64MMFR2_MASK 0xffff0fffffffffffULL 536#define ID_AA64MMFR2_CCIDX_SHIFT 20 537#define ID_AA64MMFR2_CCIDX_MASK (0xfULL << ID_AA64MMFR2_CCIDX_SHIFT) 538#define ID_AA64MMFR2_CCIDX(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) 539#define ID_AA64MMFR2_CCIDX_IMPL (0x1ULL << ID_AA64MMFR2_CCIDX_SHIFT) 540 541/* ID_AA64PFR0_EL1 */ 542#define ID_AA64PFR0_MASK 0xff0fffffffffffffULL 543#define ID_AA64PFR0_EL0_SHIFT 0 544#define ID_AA64PFR0_EL0_MASK (0xfULL << ID_AA64PFR0_EL0_SHIFT) 545#define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) 546#define ID_AA64PFR0_EL0_64 (0x1ULL << ID_AA64PFR0_EL0_SHIFT) 547#define ID_AA64PFR0_EL0_64_32 (0x2ULL << ID_AA64PFR0_EL0_SHIFT) 548#define ID_AA64PFR0_EL1_SHIFT 4 549#define ID_AA64PFR0_EL1_MASK (0xfULL << ID_AA64PFR0_EL1_SHIFT) 550#define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK) 551#define ID_AA64PFR0_EL1_64 (0x1ULL << ID_AA64PFR0_EL1_SHIFT) 552#define ID_AA64PFR0_EL1_64_32 (0x2ULL << ID_AA64PFR0_EL1_SHIFT) 553#define ID_AA64PFR0_EL2_SHIFT 8 554#define ID_AA64PFR0_EL2_MASK (0xfULL << ID_AA64PFR0_EL2_SHIFT) 555#define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK) 556#define ID_AA64PFR0_EL2_NONE (0x0ULL << ID_AA64PFR0_EL2_SHIFT) 557#define ID_AA64PFR0_EL2_64 (0x1ULL << ID_AA64PFR0_EL2_SHIFT) 558#define ID_AA64PFR0_EL2_64_32 (0x2ULL << ID_AA64PFR0_EL2_SHIFT) 559#define ID_AA64PFR0_EL3_SHIFT 12 560#define ID_AA64PFR0_EL3_MASK (0xfULL << ID_AA64PFR0_EL3_SHIFT) 561#define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK) 562#define ID_AA64PFR0_EL3_NONE (0x0ULL << ID_AA64PFR0_EL3_SHIFT) 563#define ID_AA64PFR0_EL3_64 (0x1ULL << ID_AA64PFR0_EL3_SHIFT) 564#define ID_AA64PFR0_EL3_64_32 (0x2ULL << ID_AA64PFR0_EL3_SHIFT) 565#define ID_AA64PFR0_FP_SHIFT 16 566#define ID_AA64PFR0_FP_MASK (0xfULL << ID_AA64PFR0_FP_SHIFT) 567#define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) 568#define ID_AA64PFR0_FP_IMPL (0x0ULL << ID_AA64PFR0_FP_SHIFT) 569#define ID_AA64PFR0_FP_NONE (0xfULL << ID_AA64PFR0_FP_SHIFT) 570#define ID_AA64PFR0_ADV_SIMD_SHIFT 20 571#define ID_AA64PFR0_ADV_SIMD_MASK (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT) 572#define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK) 573#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0ULL << ID_AA64PFR0_ADV_SIMD_SHIFT) 574#define ID_AA64PFR0_ADV_SIMD_NONE (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT) 575#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 576#define ID_AA64PFR0_GIC_SHIFT 24 577#define ID_AA64PFR0_GIC_MASK (0xfULL << ID_AA64PFR0_GIC_SHIFT) 578#define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) 579#define ID_AA64PFR0_GIC_CPUIF_NONE (0x0ULL << ID_AA64PFR0_GIC_SHIFT) 580#define ID_AA64PFR0_GIC_CPUIF_EN (0x1ULL << ID_AA64PFR0_GIC_SHIFT) 581#define ID_AA64PFR0_RAS_SHIFT 28 582#define ID_AA64PFR0_RAS_MASK (0xfULL << ID_AA64PFR0_RAS_SHIFT) 583#define ID_AA64PFR0_RAS(x) ((x) & ID_AA64PFR0_RAS_MASK) 584#define ID_AA64PFR0_RAS_NONE (0x0ULL << ID_AA64PFR0_RAS_SHIFT) 585#define ID_AA64PFR0_RAS_IMPL (0x1ULL << ID_AA64PFR0_RAS_SHIFT) 586#define ID_AA64PFR0_RAS_IMPL_V1P1 (0x2ULL << ID_AA64PFR0_RAS_SHIFT) 587#define ID_AA64PFR0_SVE_SHIFT 32 588#define ID_AA64PFR0_SVE_MASK (0xfULL << ID_AA64PFR0_SVE_SHIFT) 589#define ID_AA64PFR0_SVE(x) ((x) & ID_AA64PFR0_SVE_MASK) 590#define ID_AA64PFR0_SVE_NONE (0x0ULL << ID_AA64PFR0_SVE_SHIFT) 591#define ID_AA64PFR0_SVE_IMPL (0x1ULL << ID_AA64PFR0_SVE_SHIFT) 592#define ID_AA64PFR0_SEL2_SHIFT 36 593#define ID_AA64PFR0_SEL2_MASK (0xfULL << ID_AA64PFR0_SEL2_SHIFT) 594#define ID_AA64PFR0_SEL2(x) ((x) & ID_AA64PFR0_SEL2_MASK) 595#define ID_AA64PFR0_SEL2_NONE (0x0ULL << ID_AA64PFR0_SEL2_SHIFT) 596#define ID_AA64PFR0_SEL2_IMPL (0x1ULL << ID_AA64PFR0_SEL2_SHIFT) 597#define ID_AA64PFR0_MPAM_SHIFT 40 598#define ID_AA64PFR0_MPAM_MASK (0xfULL << ID_AA64PFR0_MPAM_SHIFT) 599#define ID_AA64PFR0_MPAM(x) ((x) & ID_AA64PFR0_MPAM_MASK) 600#define ID_AA64PFR0_MPAM_NONE (0x0ULL << ID_AA64PFR0_MPAM_SHIFT) 601#define ID_AA64PFR0_MPAM_IMPL (0x1ULL << ID_AA64PFR0_MPAM_SHIFT) 602#define ID_AA64PFR0_AMU_SHIFT 44 603#define ID_AA64PFR0_AMU_MASK (0xfULL << ID_AA64PFR0_AMU_SHIFT) 604#define ID_AA64PFR0_AMU(x) ((x) & ID_AA64PFR0_AMU_MASK) 605#define ID_AA64PFR0_AMU_NONE (0x0ULL << ID_AA64PFR0_AMU_SHIFT) 606#define ID_AA64PFR0_AMU_IMPL (0x1ULL << ID_AA64PFR0_AMU_SHIFT) 607#define ID_AA64PFR0_DIT_SHIFT 48 608#define ID_AA64PFR0_DIT_MASK (0xfULL << ID_AA64PFR0_DIT_SHIFT) 609#define ID_AA64PFR0_DIT(x) ((x) & ID_AA64PFR0_DIT_MASK) 610#define ID_AA64PFR0_DIT_UNKNOWN (0x0ULL << ID_AA64PFR0_DIT_SHIFT) 611#define ID_AA64PFR0_DIT_IMPL (0x1ULL << ID_AA64PFR0_DIT_SHIFT) 612#define ID_AA64PFR0_CSV2_SHIFT 56 613#define ID_AA64PFR0_CSV2_MASK (0xfULL << ID_AA64PFR0_CSV2_SHIFT) 614#define ID_AA64PFR0_CSV2(x) ((x) & ID_AA64PFR0_CSV2_MASK) 615#define ID_AA64PFR0_CSV2_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV2_SHIFT) 616#define ID_AA64PFR0_CSV2_IMPL (0x1ULL << ID_AA64PFR0_CSV2_SHIFT) 617#define ID_AA64PFR0_CSV2_SCXT (0x2ULL << ID_AA64PFR0_CSV2_SHIFT) 618#define ID_AA64PFR0_CSV2_HCXT (0x3ULL << ID_AA64PFR0_CSV2_SHIFT) 619#define ID_AA64PFR0_CSV3_SHIFT 60 620#define ID_AA64PFR0_CSV3_MASK (0xfULL << ID_AA64PFR0_CSV3_SHIFT) 621#define ID_AA64PFR0_CSV3(x) ((x) & ID_AA64PFR0_CSV3_MASK) 622#define ID_AA64PFR0_CSV3_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV3_SHIFT) 623#define ID_AA64PFR0_CSV3_IMPL (0x1ULL << ID_AA64PFR0_CSV3_SHIFT) 624 625/* ID_AA64PFR1_EL1 */ 626#define ID_AA64PFR1_MASK 0x000000000000ffffULL 627#define ID_AA64PFR1_BT_SHIFT 0 628#define ID_AA64PFR1_BT_MASK (0xfULL << ID_AA64PFR1_BT_SHIFT) 629#define ID_AA64PFR1_BT(x) ((x) & ID_AA64PFR1_BT_MASK) 630#define ID_AA64PFR1_BT_NONE (0x0ULL << ID_AA64PFR1_BT_SHIFT) 631#define ID_AA64PFR1_BT_IMPL (0x1ULL << ID_AA64PFR1_BT_SHIFT) 632#define ID_AA64PFR1_SSBS_SHIFT 4 633#define ID_AA64PFR1_SSBS_MASK (0xfULL << ID_AA64PFR1_SSBS_SHIFT) 634#define ID_AA64PFR1_SSBS(x) ((x) & ID_AA64PFR1_SSBS_MASK) 635#define ID_AA64PFR1_SSBS_NONE (0x0ULL << ID_AA64PFR1_SSBS_SHIFT) 636#define ID_AA64PFR1_SSBS_PSTATE (0x1ULL << ID_AA64PFR1_SSBS_SHIFT) 637#define ID_AA64PFR1_SSBS_PSTATE_MSR (0x2ULL << ID_AA64PFR1_SSBS_SHIFT) 638#define ID_AA64PFR1_MTE_SHIFT 8 639#define ID_AA64PFR1_MTE_MASK (0xfULL << ID_AA64PFR1_MTE_SHIFT) 640#define ID_AA64PFR1_MTE(x) ((x) & ID_AA64PFR1_MTE_MASK) 641#define ID_AA64PFR1_MTE_NONE (0x0ULL << ID_AA64PFR1_MTE_SHIFT) 642#define ID_AA64PFR1_MTE_IMPL (0x1ULL << ID_AA64PFR1_MTE_SHIFT) 643#define ID_AA64PFR1_RAS_FRAC_SHIFT 12 644#define ID_AA64PFR1_RAS_FRAC_MASK (0xfULL << ID_AA64PFR1_RAS_FRAC_SHIFT) 645#define ID_AA64PFR1_RAS_FRAC(x) ((x) & ID_AA64PFR1_RAS_FRAC_MASK) 646#define ID_AA64PFR1_RAS_FRAC_NONE (0x0ULL << ID_AA64PFR1_RAS_FRAC_SHIFT) 647#define ID_AA64PFR1_RAS_FRAC_IMPL (0x1ULL << ID_AA64PFR1_RAS_FRAC_SHIFT) 648 649/* MAIR_EL1 - Memory Attribute Indirection Register */ 650#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 651#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 652#define MAIR_DEVICE_nGnRnE 0x00 653#define MAIR_NORMAL_NC 0x44 654#define MAIR_NORMAL_WT 0x88 655#define MAIR_NORMAL_WB 0xff 656 657/* PAR_EL1 - Physical Address Register */ 658#define PAR_F_SHIFT 0 659#define PAR_F (0x1 << PAR_F_SHIFT) 660#define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 661/* When PAR_F == 0 (success) */ 662#define PAR_SH_SHIFT 7 663#define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 664#define PAR_NS_SHIFT 9 665#define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 666#define PAR_PA_SHIFT 12 667#define PAR_PA_MASK 0x0000fffffffff000 668#define PAR_ATTR_SHIFT 56 669#define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 670/* When PAR_F == 1 (aborted) */ 671#define PAR_FST_SHIFT 1 672#define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 673#define PAR_PTW_SHIFT 8 674#define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 675#define PAR_S_SHIFT 9 676#define PAR_S_MASK (0x1 << PAR_S_SHIFT) 677 678/* SCTLR_EL1 - System Control Register */ 679#define SCTLR_RES0 0xffffffffc8222400 /* Reserved, write 0 */ 680#define SCTLR_RES1 0x0000000030d00800 /* Reserved, write 1 */ 681 682#define SCTLR_M 0x0000000000000001 683#define SCTLR_A 0x0000000000000002 684#define SCTLR_C 0x0000000000000004 685#define SCTLR_SA 0x0000000000000008 686#define SCTLR_SA0 0x0000000000000010 687#define SCTLR_CP15BEN 0x0000000000000020 688#define SCTLR_THEE 0x0000000000000040 689#define SCTLR_ITD 0x0000000000000080 690#define SCTLR_SED 0x0000000000000100 691#define SCTLR_UMA 0x0000000000000200 692#define SCTLR_I 0x0000000000001000 693#define SCTLR_EnDB 0x0000000000002000 694#define SCTLR_DZE 0x0000000000004000 695#define SCTLR_UCT 0x0000000000008000 696#define SCTLR_nTWI 0x0000000000010000 697#define SCTLR_nTWE 0x0000000000040000 698#define SCTLR_WXN 0x0000000000080000 699#define SCTLR_SPAN 0x0000000000800000 700#define SCTLR_EOE 0x0000000001000000 701#define SCTLR_EE 0x0000000002000000 702#define SCTLR_UCI 0x0000000004000000 703#define SCTLR_EnDA 0x0000000008000000 704#define SCTLR_EnIB 0x0000000040000000 705#define SCTLR_EnIA 0x0000000080000000 706#define SCTLR_BT0 0x0000000800000000 707#define SCTLR_BT1 0x0000001000000000 708#define SCTLR_EPAN 0x0200000000000000 709 710/* SPSR_EL1 */ 711/* 712 * When the exception is taken in AArch64: 713 * M[4] is 0 for AArch64 mode 714 * M[3:2] is the exception level 715 * M[1] is unused 716 * M[0] is the SP select: 717 * 0: always SP0 718 * 1: current ELs SP 719 */ 720#define PSR_M_EL0t 0x00000000 721#define PSR_M_EL1t 0x00000004 722#define PSR_M_EL1h 0x00000005 723#define PSR_M_EL2t 0x00000008 724#define PSR_M_EL2h 0x00000009 725#define PSR_M_MASK 0x0000001f 726 727#define PSR_F 0x00000040 728#define PSR_I 0x00000080 729#define PSR_A 0x00000100 730#define PSR_D 0x00000200 731#define PSR_BTYPE 0x00000c00 732#define PSR_SSBS 0x00001000 733#define PSR_IL 0x00100000 734#define PSR_SS 0x00200000 735#define PSR_PAN 0x00400000 736#define PSR_UAO 0x00800000 737#define PSR_DIT 0x01000000 738#define PSR_TCO 0x02000000 739#define PSR_V 0x10000000 740#define PSR_C 0x20000000 741#define PSR_Z 0x40000000 742#define PSR_N 0x80000000 743 744/* TCR_EL1 - Translation Control Register */ 745#define TCR_AS (1UL << 36) 746 747#define TCR_IPS_SHIFT 32 748#define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT) 749#define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT) 750#define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT) 751#define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT) 752#define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) 753#define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) 754 755#define TCR_TG1_SHIFT 30 756#define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) 757#define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) 758#define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) 759 760#define TCR_SH1_SHIFT 28 761#define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) 762#define TCR_ORGN1_SHIFT 26 763#define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) 764#define TCR_IRGN1_SHIFT 24 765#define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) 766 767#define TCR_A1 (1UL << 22) 768 769#define TCR_TG0_SHIFT 14 770#define TCR_TG0_4K (0UL << TCR_TG0_SHIFT) 771#define TCR_TG0_64K (1UL << TCR_TG0_SHIFT) 772#define TCR_TG0_16K (2UL << TCR_TG0_SHIFT) 773 774#define TCR_SH0_SHIFT 12 775#define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) 776#define TCR_ORGN0_SHIFT 10 777#define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) 778#define TCR_IRGN0_SHIFT 8 779#define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) 780 781#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 782 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 783#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 784 785#define TCR_T1SZ_SHIFT 16 786#define TCR_T0SZ_SHIFT 0 787#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 788#define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 789#define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 790 791/* Monitor Debug System Control Register */ 792#define DBG_MDSCR_SS (0x1 << 0) 793#define DBG_MDSCR_TDCC (0x1 << 12) 794#define DBG_MDSCR_KDE (0x1 << 13) 795#define DBG_MDSCR_MDE (0x1 << 15) 796 797/* Performance Monitoring Counters */ 798#define PMCR_E (1 << 0) /* Enable all counters */ 799#define PMCR_P (1 << 1) /* Reset all counters */ 800#define PMCR_C (1 << 2) /* Clock counter reset */ 801#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 802#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 803#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 804#define PMCR_LC (1 << 6) /* Long cycle count enable */ 805#define PMCR_IMP_SHIFT 24 /* Implementer code */ 806#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 807#define PMCR_IDCODE_SHIFT 16 /* Identification code */ 808#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 809#define PMCR_IDCODE_CORTEX_A57 0x01 810#define PMCR_IDCODE_CORTEX_A72 0x02 811#define PMCR_IDCODE_CORTEX_A53 0x03 812#define PMCR_N_SHIFT 11 /* Number of counters implemented */ 813#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 814 815/* Individual CPUs are probably best IDed by everything but the revision. */ 816#define CPU_ID_CPU_MASK 0xfffffff0 817 818/* ARM64 CPUs */ 819#define CPU_ID_CORTEX_A53 0x410fd030 820#define CPU_ID_CORTEX_A53_R1 0x411fd030 821#define CPU_ID_CORTEX_A53_MASK 0xff0ffff0 822#define CPU_ID_CORTEX_A57 0x410fd070 823#define CPU_ID_CORTEX_A57_R1 0x411fd070 824#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 825#define CPU_ID_CORTEX_A72 0x410fd080 826#define CPU_ID_CORTEX_A72_R1 0x411fd080 827#define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 828 829#define I_bit (1 << 7) /* IRQ disable */ 830#define F_bit 0 /* FIQ disable - not actually used */ 831 832#endif /* !_MACHINE_ARMREG_H_ */ 833